CN112346920A - Integrated circuit test data analysis method and system - Google Patents
Integrated circuit test data analysis method and system Download PDFInfo
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Abstract
The invention provides an integrated circuit test data analysis method and a system, wherein the method comprises the following steps: the test machine analyzes first test data of a first integrated circuit to be tested and sends the first test data to the analysis database; the analysis database receives and stores first test data; the analysis equipment captures first test data from an analysis database and calculates performance parameters of the first integrated circuit; the analysis equipment captures benchmark test data from an analysis database, and calculates benchmark performance parameters, wherein the benchmark test data are m batches of test data before the first test data, the m batches of test data are adjacent in sequence, one batch of test data in the m batches of test data is adjacent to the first test data, and m is a positive integer; the analysis equipment determines whether the first integrated circuit is good or not according to the performance parameter of the tested first integrated circuit and the reference performance parameter. The method and the device realize dynamic analysis of key indexes (yield, BIN and the like), and improve accuracy and efficiency of chip testing.
Description
Technical Field
The invention belongs to the field of chip testing, and particularly relates to an integrated circuit test data analysis method and system.
Background
Integrated circuits (chips) are widely used in various industries such as consumer electronics/security/industrial equipment/automotive electronics. All integrated circuit (chip) products must be tested rigorously before they are finally assembled into a product, ensuring that they have the designed functionality and quality before they can be used. The integrated circuit Test comprises a Wafer level Test (Wafer Test) before packaging and a finished product level Test (Final Test) after packaging; the integrated circuit manufacturing has a complex multi-process flow, which can bring certain manufacturing failures (defective products), the defective products need to be screened out and removed through wafer level testing, the packaging process is also complex, which can bring certain packaging failures (defective products), and the defective products need to be screened out and removed through finished product level testing.
In the prior art, the following methods are generally adopted for integrated circuit testing: the average yield and the average BIN number are obtained by directly using an empirical value (very wide range) or manually counting the yield and the BIN number of a certain batch (such as 100 batches) in the early stage of introducing the product, then the average value is used as a comparison standard and set into a corresponding control system, and the data of the current test batch is compared with the preset data after the test of each batch is finished so as to find whether a problem exists. The accuracy and efficiency of the test method are poor.
Disclosure of Invention
In order to solve the problem that the accuracy and the efficiency of the existing integrated circuit test data analysis method are poor, the embodiment of the application provides an integrated circuit test data analysis method and system.
In a first aspect, an embodiment of the present application provides an integrated circuit test data analysis method, including:
the test machine analyzes first test data of a first integrated circuit to be tested and sends the analyzed first test data to an analysis database;
the analysis database receives and stores the analyzed first test data;
the analysis equipment captures first test data from the analysis database and calculates performance parameters of the first integrated circuit to be tested;
the analysis equipment captures benchmark test data from the analysis database and calculates benchmark performance parameters, wherein the benchmark test data are m batches of test data before the first test data, the m batches of test data are adjacent in sequence, one batch of test data in the m batches of test data is adjacent to the first test data, and m is a positive integer;
the analysis equipment determines whether the first integrated circuit is good or not according to the performance parameter of the tested first integrated circuit and the reference performance parameter.
Wherein the analyzing device fetches the first test data from the analysis database and calculates the performance parameter of the first integrated circuit under test, including:
the analysis equipment captures the product model and station information of the first integrated circuit corresponding to the first test data from the analysis database, and calculates the yield and BIN information of the first integrated circuit;
the analysis equipment captures benchmark test data from the analysis database, and calculates benchmark performance parameters, including:
and the analysis equipment captures reference test data from the analysis database according to the product model and the station information of the first integrated circuit, and calculates reference yield and reference BIN information.
The method for determining whether the first integrated circuit is good or not by the analysis equipment according to the performance parameter of the first integrated circuit to be tested and the reference performance parameter comprises the following steps:
the analysis equipment compares the yield of the first integrated circuit with a reference yield, and if the yield of the first integrated circuit is smaller than the reference yield, the first integrated circuit is a defective product;
the analysis equipment compares the BIN information of the first integrated circuit with reference BIN information, and if the BIN information of the first integrated circuit is greater than the reference BIN information, the first integrated circuit is a defective product;
and if the yield of the first integrated circuit is greater than the reference yield, the BIN information of the first integrated circuit is less than the reference BIN information, and the first integrated circuit passes the test.
Wherein, still include:
and if the first integrated circuit is a defective product, the analysis equipment sends alarm information to a triggering alarm device.
After receiving the alarm information, the triggering alarm device gives an alarm through the three-color lamp flashing and the buzzer.
In a second aspect, an embodiment of the present application provides an integrated circuit test data analysis system, including:
the testing machine is used for analyzing first test data of a first integrated circuit to be tested and sending the analyzed first test data to the analysis database;
the analysis database is used for receiving and storing the analyzed first test data;
the analysis equipment is used for grabbing first test data from the analysis database and calculating the performance parameters of the first integrated circuit to be tested;
the analysis device is further configured to: capturing benchmark test data from the analysis database, and calculating benchmark performance parameters, wherein the benchmark test data are m batches of test data before the first test data, the m batches of test data are adjacent in sequence, one batch of test data in the m batches of test data is adjacent to the first test data, and m is a positive integer;
the analysis device is further configured to: and determining whether the first integrated circuit is good or not according to the performance parameter of the tested first integrated circuit and the reference performance parameter.
Wherein the analysis device is configured to:
capturing the product model and station information of the first integrated circuit corresponding to the first test data from the analysis database, and calculating the yield and BIN information of the first integrated circuit;
and capturing reference test data from the analysis database according to the product model and the station information of the first integrated circuit, and calculating reference yield and reference BIN information.
Wherein the analysis device is configured to:
comparing the yield of the first integrated circuit with a reference yield, wherein if the yield of the first integrated circuit is less than the reference yield, the first integrated circuit is a defective product;
comparing the BIN information of the first integrated circuit with reference BIN information, and if the BIN information of the first integrated circuit is greater than the reference BIN information, determining that the first integrated circuit is a defective product;
and if the yield of the first integrated circuit is greater than the reference yield, the BIN information of the first integrated circuit is less than the reference BIN information, and the first integrated circuit passes the test.
Wherein, still include triggering alarm device, analytical equipment is still used for: and if the first integrated circuit is a defective product, the analysis equipment sends alarm information to the trigger alarm device.
Wherein the triggering alarm device is used for: after receiving the alarm information, the alarm is given out through the three-color lamp flashing and the buzzer.
The method and the system for analyzing the test data of the integrated circuit have the following beneficial effects:
the method for analyzing the test data of the integrated circuit comprises the following steps: the test machine analyzes first test data of a first integrated circuit to be tested and sends the analyzed first test data to an analysis database; the analysis database receives and stores the analyzed first test data; the analysis equipment captures first test data from an analysis database and calculates performance parameters of a first integrated circuit to be tested; the analysis equipment captures benchmark test data from an analysis database, and calculates benchmark performance parameters, wherein the benchmark test data are m batches of test data before the first test data, the m batches of test data are adjacent in sequence, one batch of test data in the m batches of test data is adjacent to the first test data, and m is a positive integer; the analysis equipment determines whether the first integrated circuit is good or not according to the performance parameter of the tested first integrated circuit and the reference performance parameter. In the application, the analytical equipment captures the latest m batches of the same product models and other test data of the stations in the database, the calculation and comparison are carried out, the analytical equipment realizes the dynamic analysis of key indexes (yield, BIN and the like), the trouble and workload of manual setting are avoided, the yield change caused by the process change is more fit, and the accuracy and efficiency of chip testing are improved.
Drawings
FIG. 1 is a schematic flow chart illustrating a method for analyzing test data of an integrated circuit according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of an integrated circuit test data analysis system according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of an analysis device of an integrated circuit test data analysis system according to an embodiment of the present application.
Detailed Description
The present application is further described with reference to the following figures and examples.
In the following description, the terms "first" and "second" are used for descriptive purposes only and are not intended to indicate or imply relative importance. The following description provides embodiments of the invention, which may be combined or substituted for various embodiments, and this application is therefore intended to cover all possible combinations of the same and/or different embodiments described. Thus, if one embodiment includes feature A, B, C and another embodiment includes feature B, D, then this application should also be considered to include an embodiment that includes one or more of all other possible combinations of A, B, C, D, even though this embodiment may not be explicitly recited in text below.
The following description provides examples, and does not limit the scope, applicability, or examples set forth in the claims. Changes may be made in the function and arrangement of elements described without departing from the scope of the disclosure. Various examples may omit, substitute, or add various procedures or components as appropriate. For example, the described methods may be performed in an order different than the order described, and various steps may be added, omitted, or combined. Furthermore, features described with respect to some examples may be combined into other examples.
Integrated circuits (chips) are widely used in various industries such as consumer electronics/security/industrial equipment/automotive electronics. All integrated circuit (chip) products must be tested rigorously before they are finally assembled into a product, ensuring that they have the designed functionality and quality before they can be used. The integrated circuit Test comprises a Wafer level Test (Wafer Test) before packaging and a finished product level Test (Final Test) after packaging; the integrated circuit manufacturing has a complex multi-process flow, which can bring certain manufacturing failures (defective products), the defective products need to be screened out and removed through wafer level testing, the packaging process is also complex, which can bring certain packaging failures (defective products), and the defective products need to be screened out and removed through finished product level testing.
The test requires the use of various test equipment such as a precise integrated circuit tester, a probe station, a handler, and the like, and various accessories such as a probe card, a contact plate, a test socket, and the like, and also requires the setting and use of highly technical rack parameters. The test usually uses LOT as a unit, each LOT is put into a tester, and after hardware simulation and software program execution, the test is finally completed, and relevant test data including yield, BIN (number of bad product distribution), test log and the like are output. The abnormal or error of any link can cause the distortion of the test result, and the original good product can be mistakenly detected as a failure defective product, and the failure of the non-product property is called as misslaughter.
From the above analysis, it is known that software and hardware anomalies in wafer fabrication, packaging, and testing itself all cause anomalies in the test data (yield/BIN, etc.), and are therefore particularly important for analysis and alarm of the test data.
In the prior art, the following methods are generally adopted for integrated circuit testing: the average yield and the average BIN number are obtained by directly using an empirical value (very wide range) or manually counting the yield and the BIN number of a certain batch (such as 100 batches) in the early stage of introducing the product, then the average value is used as a comparison standard and set into a corresponding control system, and the data of the current test batch is compared with the preset data after the test of each batch is finished so as to find whether a problem exists. The above test method has the following disadvantages: 1. the analysis method belongs to static analysis, and the comparison standard is preset and generally wider. 2. Manual statistics brings certain workload, and missing statistics and error statistics are easy to occur; 3. wafer manufacturing process, packaging process and testing process are all continuously promoted, testing yield is also continuously improved, and references in the prior art cannot be synchronously promoted.
As shown in fig. 1, the method for analyzing the test data of the integrated circuit of the present application includes the steps of: s101, a testing machine analyzes first test data of a first integrated circuit to be tested and sends the analyzed first test data to an analysis database; s103, analyzing the first test data received and stored by the database; s105, the analysis equipment captures first test data from the analysis database and calculates the performance parameters of the first integrated circuit to be tested; s107, the analysis equipment captures benchmark test data from the analysis database, and calculates benchmark performance parameters, wherein the benchmark test data are m batches of test data before the first test data, the m batches of test data are adjacent in sequence, one batch of test data in the m batches of test data is adjacent to the first test data, and m is a positive integer; and S109, the analysis equipment determines whether the first integrated circuit is a good product according to the performance parameter of the tested first integrated circuit and the reference performance parameter. Each step is described below.
S101, the testing machine analyzes first test data of a first integrated circuit to be tested, and sends the analyzed first test data to an analysis database.
The test data supports multiple formats such as MAP, STDF and the like, the analyzed and uploaded program runs on each Tester computer, the script is automatically started after each batch of products are tested, and the analysis of the batch of test data is realized and the test data is inserted into an analysis Database eagleEye Database.
And S103, receiving and storing the analyzed first test data by the analysis database.
The analysis database receives and stores test data uploaded by Update Script software in the tester, and meanwhile, correctness verification is carried out on some key information.
And S105, the analysis equipment captures first test data from the analysis database and calculates the performance parameters of the first integrated circuit to be tested.
The steps include, for example: and the analysis equipment captures the product model and station information of the first integrated circuit corresponding to the first test data from the analysis database, and calculates the yield and BIN information of the first integrated circuit. The station information refers to a process or step of processing the integrated circuit. The BIN-level information is: there are many kinds of failures in the chip test, and the BIN type information indicates the kind of failures in the chip test and the number of defective products in the kind.
The analysis equipment captures and calculates the product model Product and station information STEPX of the current upward-throwing analysis database test data, yield YieldX, and the number of BINX (n) in array format, such as BINX (2) ═ 30, BINX (3) ═ 50 … …
S107, the analysis equipment captures benchmark test data from the analysis database, and calculates benchmark performance parameters, wherein the benchmark test data are m batches of test data before the first test data, the m batches of test data are adjacent in sequence, one batch of test data in the m batches of test data is adjacent to the first test data, and m is a positive integer.
The analysis equipment captures reference test data from an analysis database according to the product model and the station information of the first integrated circuit, and calculates reference yield and reference BIN information. That is, the product model and the station information of the benchmark test data are the same as those of the first integrated circuit. The benchmark test data is m test data batches before the first test data, the m test data batches are adjacent in sequence, one test data batch in the m test data batches is adjacent to the first test data, m is a positive integer, namely the benchmark test data is the m test data batch nearest to the first test data batch.
The analyzer captures the test data of the latest M batches (e.g. 60 batches) of the same product model and station in the database, and calculates the Yield _ M60 and BIN _ M60 (n).
And S109, the analysis equipment determines whether the first integrated circuit is a good product according to the performance parameter of the tested first integrated circuit and the reference performance parameter.
The steps include, for example: the analysis equipment compares the yield of the first integrated circuit with the reference yield, and if the yield of the first integrated circuit is smaller than the reference yield, the first integrated circuit is a defective product;
the analysis equipment compares the BIN information of the first integrated circuit with the reference BIN information, and if the BIN information of the first integrated circuit is greater than the reference BIN information, the first integrated circuit is a defective product;
if the yield of the first integrated circuit is greater than the reference yield, the BIN information of the first integrated circuit is less than the reference BIN information, and the first integrated circuit passes the test.
If YIeldX < YIeld _ M60, marking as comparison FAIL; if BINX (n) > BIN _ M60(n), it is labeled as comparison FAIL.
If PASS is compared, the analysis equipment writes a log of comparison success in the background, and the batch of products is directly released.
In some embodiments, the method for analyzing integrated circuit test data further comprises: if the first integrated circuit is a defective product, the analysis equipment sends alarm information to the triggering alarm device. After the triggering alarm device receives the alarm information, the three-color lamp flickers and the buzzer alarms.
The triggering alarm device comprises a USB control circuit, a three-color lamp and a buzzer, and once an alarm instruction is received, real-time three-color lamp flashing and buzzer alarming are realized to remind technicians of finding abnormality and intervening treatment. After being informed, the field technicians can stop the equipment production at the first time, so that batch scrapping caused by a large number of abnormal tests is avoided; meanwhile, the analysis equipment sends an alarm mail to a product responsible person. In the present application, the analysis device includes software and hardware.
The method provides a brand-new complete solution for analyzing and early warning of test data of the integrated circuit; avoid the trouble that the industry supplier can only provide partial or incomplete service. In the application, the analytical equipment captures the latest m batches of the same product models and other test data of the stations in the database, the calculation and comparison are carried out, the analytical equipment realizes the dynamic analysis of key indexes (yield, BIN and the like), the trouble and workload of manual setting are avoided, the yield change caused by the process change is more fit, and the accuracy and efficiency of chip testing are improved.
As shown in fig. 2, the present application provides an integrated circuit test data analysis system, comprising: the tester is used for analyzing first test data of a first integrated circuit to be tested and sending the analyzed first test data to the analysis database. The number of testers may be plural, for example, tester 1201, tester 2202, tester 3203, and tester n 204.
The analysis database 205 is used for receiving and storing the analyzed first test data;
an analyzing device 206 for fetching first test data from the analysis database and calculating performance parameters of the first integrated circuit under test;
the analysis device 206 is further configured to: capturing benchmark test data from an analysis database, and calculating a benchmark performance parameter, wherein the benchmark test data is m batches of test data before the first test data, the m batches of test data are adjacent in sequence, one batch of test data in the m batches of test data is adjacent to the first test data, and m is a positive integer;
the analysis device 206 is further configured to: and determining whether the first integrated circuit is good or not according to the performance parameter of the tested first integrated circuit and the reference performance parameter.
Wherein the analysis device 206 is configured to: capturing the product model and station information of the first integrated circuit corresponding to the first test data from the analysis database, and calculating the yield and BIN information of the first integrated circuit;
and capturing reference test data from the analysis database according to the product model and the station information of the first integrated circuit, and calculating the reference yield and the reference BIN information.
Wherein the analysis device 206 is configured to: comparing the yield of the first integrated circuit with the reference yield, and if the yield of the first integrated circuit is less than the reference yield, determining that the first integrated circuit is a defective product;
comparing the BIN information of the first integrated circuit with the reference BIN information, wherein if the BIN information of the first integrated circuit is greater than the reference BIN information, the first integrated circuit is a defective product;
if the yield of the first integrated circuit is greater than the reference yield, the BIN information of the first integrated circuit is less than the reference BIN information, and the first integrated circuit passes the test.
Wherein, still including triggering alarm device, analytical equipment still is used for: if the first integrated circuit is a defective product, the analysis equipment sends alarm information to the triggering alarm device.
Wherein, trigger alarm device is used for: after receiving the alarm information, the alarm is given out through the three-color lamp flashing and the buzzer.
In the present application, the embodiment of the system for analyzing test data of an integrated circuit is substantially similar to the embodiment of the method for analyzing test data of an integrated circuit, and reference is made to the description of the embodiment of the method for analyzing test data of an integrated circuit for related purposes.
It is clear to a person skilled in the art that the solution according to the embodiments of the invention can be implemented by means of software and/or hardware. The "unit" and "module" in this specification refer to software and/or hardware that can perform a specific function independently or in cooperation with other components, where the hardware may be, for example, an FPGA (Field-Programmable Gate Array), an IC (Integrated Circuit), or the like.
Each processing unit and/or module according to the embodiments of the present invention may be implemented by an analog circuit that implements the functions described in the embodiments of the present invention, or may be implemented by software that executes the functions described in the embodiments of the present invention.
Embodiments of the present invention further provide a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of the method for analyzing test data of an integrated circuit. The computer-readable storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, DVD, CD-ROMs, microdrive, and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic or optical cards, nanosystems (including molecular memory ICs), or any type of media or device suitable for storing instructions and/or data.
Fig. 3 is a schematic structural diagram of an analysis device of an integrated circuit test data analysis system according to an embodiment of the present invention, as shown in fig. 3, the analysis device is, for example, a desktop computer, a workbench, a server, a blade server, a mainframe computer, or other suitable computers. The analysis apparatus of the present application comprises a processor 401, a memory 402, an input device 403 and an output device 404. The processor 401, memory 402, input device 403, and output device 404 may be connected by a bus 405 or otherwise. The memory 402 stores thereon a computer program that is executable on the processor 401, and the processor 401, when executing the program, implements the steps belonging to the analysis device in the integrated circuit test data analysis method described above.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.
All functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. An integrated circuit test data analysis method, comprising:
the test machine analyzes first test data of a first integrated circuit to be tested and sends the analyzed first test data to an analysis database;
the analysis database receives and stores the analyzed first test data;
the analysis equipment captures first test data from the analysis database and calculates performance parameters of the first integrated circuit to be tested;
the analysis equipment captures benchmark test data from the analysis database and calculates benchmark performance parameters, wherein the benchmark test data are m batches of test data before the first test data, the m batches of test data are adjacent in sequence, one batch of test data in the m batches of test data is adjacent to the first test data, and m is a positive integer;
the analysis equipment determines whether the first integrated circuit is good or not according to the performance parameter of the tested first integrated circuit and the reference performance parameter.
2. The method of claim 1, wherein the analyzing device retrieves first test data from the analysis database and calculates performance parameters of the first integrated circuit under test, comprising:
the analysis equipment captures the product model and station information of the first integrated circuit corresponding to the first test data from the analysis database, and calculates the yield and BIN information of the first integrated circuit;
the analysis equipment captures benchmark test data from the analysis database, and calculates benchmark performance parameters, including:
and the analysis equipment captures reference test data from the analysis database according to the product model and the station information of the first integrated circuit, and calculates reference yield and reference BIN information.
3. The method of claim 2, wherein the analyzing device determines whether the first integrated circuit is good based on the performance parameter of the first integrated circuit under test and the reference performance parameter, and comprises:
the analysis equipment compares the yield of the first integrated circuit with a reference yield, and if the yield of the first integrated circuit is smaller than the reference yield, the first integrated circuit is a defective product;
the analysis equipment compares the BIN information of the first integrated circuit with reference BIN information, and if the BIN information of the first integrated circuit is greater than the reference BIN information, the first integrated circuit is a defective product;
and if the yield of the first integrated circuit is greater than the reference yield, the BIN information of the first integrated circuit is less than the reference BIN information, and the first integrated circuit passes the test.
4. The method for analyzing integrated circuit test data according to any one of claims 1 to 3, further comprising:
and if the first integrated circuit is a defective product, the analysis equipment sends alarm information to a triggering alarm device.
5. The method of claim 4, wherein the triggering alarm device flashes a tri-color light and alarms with a buzzer after receiving the alarm information.
6. An integrated circuit test data analysis system, comprising:
the testing machine is used for analyzing first test data of a first integrated circuit to be tested and sending the analyzed first test data to the analysis database;
the analysis database is used for receiving and storing the analyzed first test data;
the analysis equipment is used for grabbing first test data from the analysis database and calculating the performance parameters of the first integrated circuit to be tested;
the analysis device is further configured to: capturing benchmark test data from the analysis database, and calculating benchmark performance parameters, wherein the benchmark test data are m batches of test data before the first test data, the m batches of test data are adjacent in sequence, one batch of test data in the m batches of test data is adjacent to the first test data, and m is a positive integer;
the analysis device is further configured to: and determining whether the first integrated circuit is good or not according to the performance parameter of the tested first integrated circuit and the reference performance parameter.
7. The integrated circuit test data analysis system of claim 6, wherein the analysis device is configured to:
capturing the product model and station information of the first integrated circuit corresponding to the first test data from the analysis database, and calculating the yield and BIN information of the first integrated circuit;
and capturing reference test data from the analysis database according to the product model and the station information of the first integrated circuit, and calculating reference yield and reference BIN information.
8. The integrated circuit test data analysis system of claim 7, wherein the analysis device is configured to:
comparing the yield of the first integrated circuit with a reference yield, wherein if the yield of the first integrated circuit is less than the reference yield, the first integrated circuit is a defective product;
comparing the BIN information of the first integrated circuit with reference BIN information, and if the BIN information of the first integrated circuit is greater than the reference BIN information, determining that the first integrated circuit is a defective product;
and if the yield of the first integrated circuit is greater than the reference yield, the BIN information of the first integrated circuit is less than the reference BIN information, and the first integrated circuit passes the test.
9. The integrated circuit test data analysis system of any one of claims 6-8, further comprising a trigger alarm device, the analysis apparatus further configured to: and if the first integrated circuit is a defective product, the analysis equipment sends alarm information to the trigger alarm device.
10. The integrated circuit test data analysis system of claim 9, wherein the trigger alert device is configured to: after receiving the alarm information, the alarm is given out through the three-color lamp flashing and the buzzer.
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| CN202011328711.3A CN112346920A (en) | 2020-11-24 | 2020-11-24 | Integrated circuit test data analysis method and system |
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| CN202011328711.3A CN112346920A (en) | 2020-11-24 | 2020-11-24 | Integrated circuit test data analysis method and system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113779910A (en) * | 2021-11-10 | 2021-12-10 | 海光信息技术股份有限公司 | Product performance distribution prediction method and device, electronic equipment and storage medium |
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| CN111751702A (en) * | 2020-05-28 | 2020-10-09 | 杭州芯讯科技有限公司 | Integrated circuit testing method and system |
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| CN111751702A (en) * | 2020-05-28 | 2020-10-09 | 杭州芯讯科技有限公司 | Integrated circuit testing method and system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113779910A (en) * | 2021-11-10 | 2021-12-10 | 海光信息技术股份有限公司 | Product performance distribution prediction method and device, electronic equipment and storage medium |
| CN113779910B (en) * | 2021-11-10 | 2022-02-22 | 海光信息技术股份有限公司 | Product performance distribution prediction method and device, electronic equipment and storage medium |
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