CN114416514B - Automatic checking and verifying method and system based on test packaging Mapping - Google Patents
Automatic checking and verifying method and system based on test packaging Mapping Download PDFInfo
- Publication number
- CN114416514B CN114416514B CN202210299882.0A CN202210299882A CN114416514B CN 114416514 B CN114416514 B CN 114416514B CN 202210299882 A CN202210299882 A CN 202210299882A CN 114416514 B CN114416514 B CN 114416514B
- Authority
- CN
- China
- Prior art keywords
- test
- mapping information
- template
- module
- map
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
- G06F11/324—Display of status information
- G06F11/327—Alarm or error message display
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F40/00—Handling natural language data
- G06F40/10—Text processing
- G06F40/166—Editing, e.g. inserting or deleting
- G06F40/186—Templates
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Audiology, Speech & Language Pathology (AREA)
- Computational Linguistics (AREA)
- General Health & Medical Sciences (AREA)
- Health & Medical Sciences (AREA)
- Artificial Intelligence (AREA)
- Computer Hardware Design (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention relates to a Mapping automatic checking and verifying method and a system based on test packaging, wherein the automatic checking and verifying method comprises the following steps: s1, determining key parameters to be measured; s2, constructing a test flow and a storage path of test data; s3, creating a template Mapping information source; s4, obtaining the Mapping information of the tested product; s5, analyzing the testing Mapping information and comparing the analyzed testing Mapping information with the template Mapping information source; s6, if the comparison result in S5 is completely consistent, entering the next process, and if the sub-item information corresponding to any item is inconsistent, repeating S5; the automatic checking and checking system comprises a processing unit, an input unit, a storage unit, a standard unit, a probe station, an analysis unit and an analysis unit, wherein the input unit, the storage unit, the standard unit, the probe station, the analysis unit and the analysis unit are in communication connection with the processing unit; the method and the device can ensure the reliability and accuracy of the Map information of the wafer test.
Description
Technical Field
The invention belongs to the technical field of semiconductor wafer packaging test, and particularly relates to a test packaging Mapping-based automatic checking and checking method and system.
Background
In the process of testing semiconductor wafers, the test Map is produced after a new product is imported and confirmed to be accurate, but in the process of testing the semiconductor wafers produced in quantity, the generated test Map is abnormal or even wrong due to various reasons such as abnormal test or abnormal testing of a Bug analysis tool or a Prober testing platform, the accuracy of the test Map cannot be verified by the control of a system according to the conventional standard steps, and even if the test Map is abnormal, the test Map cannot be found, so that the abnormal wafer of the test Map flows out, the packaging is abnormal, and finally serious quality accidents are caused.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a test packaging Mapping-based automatic checking and verifying method and system which can effectively ensure the reliability and accuracy of the Map information of wafer test.
The technical scheme of the invention is as follows:
the technical scheme of the invention is that the automatic checking and checking method based on the test packaging Mapping is provided, and comprises the following steps:
s1, determining key parameters to be measured of the target product according to the performance requirement of the target product;
s2, constructing a test flow of the tested product according to the key parameters to be tested determined in S1, and constructing a storage path of test data obtained through the test flow;
s3, testing the target product according to the testing flow established in the S2, and taking the testing data of the target product as a Mapping information creation template Mapping information source;
s4, testing each tested product according to the testing flow constructed in the S2, and storing the testing data of each tested product as testing Mapping information into the unique storage path corresponding to the tested product;
s5, when each tested product completes the S4, analyzing the testing Mapping information in the storage path corresponding to the tested product, and comparing the analyzed testing Mapping information with the template Mapping information source in the S3 one by one according to a preset flow;
s6, after S5 is completed, when the analytic data of the testing Mapping information of the tested product is completely consistent with the template Mapping information source, the tested product enters the next processing flow; and when the analysis data of the testing Mapping information of the tested product is inconsistent with any corresponding sub-item information in the template Mapping information source, executing S5 on the tested product until the analysis data of the testing Mapping information of the tested product is completely consistent with any corresponding sub-item information in the template Mapping information source, and entering the next processing flow.
Further, the key parameters to be tested at least comprise a Map naming rule, a Map format and Map contents, wherein the Map contents at least comprise a Notch direction, a testing Die number and a testing Die position.
Further, the template Mapping information source at least comprises a template Map naming rule module, a template Map format module and a template Map content module, and the template Map content module at least comprises a template Notch direction module, a template testing Die number module and a template testing Die position module.
Further, the storage path comprises a test Map naming rule module, a test Map format module and a test Map content module which are arranged according to a test sequence and are at the same level, the test Map content module at least comprises a test Notch direction submodule, a test Die number submodule and a test Die position submodule, and the Notch direction submodule, the test Die number submodule and the test Die position submodule are stored in the Map content module.
Further, in the step of S5, the test Map naming rule module and the test Map format module of the product to be tested, and the test Notch direction sub-module, the test Die number sub-module and the test Die position sub-module under the test Map content module are respectively compared with the template Map naming rule module and the template Map format module of the template Mapping information source, and the template Notch direction module, the template test Die number module and the template test Die position module under the template Map content module one by one.
Further, the creating process of the template Mapping information source in S3 is to test the target product according to the test flow constructed in S2, and store the test data of the target product as Mapping information into the unique storage path corresponding to the target product to serve as the template Mapping information source.
It can be understood that the target products in S1 and S3 in the automatic inspection and verification method based on test packaging Mapping provided by the present invention are engineering sheets (i.e., wafer samples meeting the requirements) meeting the enterprise customization requirements, the obtained test data of the template Mapping information source are obtained after the engineering sheets are tested according to the built test flow, and the obtained test data of the engineering sheets are confirmed by the enterprise to ensure that the test data of the template Mapping information source is accurate and error-free standard template data.
Another technical solution of the present invention is to provide an automatic checking and verifying system based on test package Mapping, including:
the input unit is used for constructing a test flow of a tested product according to the determined key parameters to be tested of the target product and constructing a storage path of test data obtained through the test flow;
the processing unit is in communication connection with the input unit and can receive instructions of the input unit to generate a test flow and a storage path;
the standard unit is in communication connection with the processing unit and can store the template Mapping information source according to the storage path generated by the processing unit;
the probe station is in communication connection with the processing unit, receives the instruction of the processing unit, tests the tested product according to the test flow, and transmits the obtained test data serving as test Mapping information to the processing unit;
the storage unit is in communication connection with the processing unit and can store the test Mapping information transmitted from the probe station to the processing unit according to a storage path generated by the processing unit;
the analysis unit is in communication connection with the processing unit and calls the test Mapping information in the storage unit to analyze to obtain analysis data;
and the analysis unit is in communication connection with the processing unit and compares the analysis data obtained by the analysis unit with the key parameters of the template Mapping information source in the standard unit one by one.
Further, when the analysis unit detects that the primary analysis data of the testing Mapping information of the tested product is inconsistent with any corresponding key parameter in the template Mapping information source, the analysis unit analyzes the testing Mapping information again to obtain secondary analysis data; and the analysis unit compares the secondary analysis data obtained by the analysis unit with the template Mapping information source again for key parameters one by one.
Furthermore, the automatic checking and checking system based on the test packaging Mapping further comprises an alarm unit, the alarm unit is in communication connection with the processing unit, and the alarm unit can send alarm information according to the alarm instruction of the processing unit.
Further, the alarm unit can at least send out second-level alarm information, when the analysis unit detects that the primary analysis data of the testing Mapping information of the tested product is inconsistent with any one corresponding key parameter in the Mapping information source of the template, the processing unit sends out an alarm instruction to the alarm unit, and the alarm unit sends out first-level alarm according to the alarm instruction; when the analysis unit detects that the secondary analysis data of the testing Mapping information of the tested product is inconsistent with any corresponding key parameter in the template Mapping information source, the processing unit sends a secondary alarm instruction to the alarm unit, and the alarm unit sends a secondary alarm according to the secondary alarm instruction.
Compared with the prior art, the invention has the beneficial effects that:
1. in the process of detecting the wafer, a verification program of Map information is added, a test flow is established according to key parameters to be detected of a target product, test data are stored according to a set storage rule, and then the test data stored according to the storage rule are compared with a template Mapping information source, so that the reliability and the accuracy of a wafer test Map result are effectively ensured, the condition that the Map is abnormal and not verified due to reasons such as midway test abnormity, tool Bug generation, test Prober platform abnormity and the like is effectively avoided, the condition that mispackaging abnormity is finally caused by misputting in storage is avoided, and the wafer outflow of Map information abnormity is avoided;
2. the invention provides an automatic checking and verifying system based on test packaging Mapping for effectively checking Map information, which can be used for accurately checking the Map information of a wafer in a high-efficiency matching manner and carrying out secondary alarm according to the detection condition so as to facilitate timely intervention of an operator and effectively ensure the reliability and the accuracy of the Map information test result of the wafer;
in short, the automatic checking and checking method and system based on test packaging Mapping provided by the invention can effectively ensure the reliability and accuracy of the Map information of wafer test and effectively avoid the wafer outflow with abnormal Map information.
Drawings
FIG. 1 is a flow chart of an automatic checking and verifying method based on test packaging Mapping according to the present invention;
FIG. 2 is a block diagram of the automatic checking and verifying system based on test packaging Mapping according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, an automatic checking and verifying method based on test package Mapping includes the following steps:
s1, determining key parameters to be measured of the target product according to the performance requirement of the target product;
s2, constructing a test flow of the tested product according to the key parameters to be tested determined in S1, and constructing a storage path of test data obtained through the test flow;
s3, testing the target product according to the testing flow established in the S2, and taking the testing data of the target product as a Mapping information creation template Mapping information source;
s4, testing each tested product according to the testing flow constructed in the S2, and storing the testing data of each tested product as testing Mapping information into the unique storage path corresponding to the tested product;
s5, when each tested product completes the S4, analyzing the testing Mapping information in the storage path corresponding to the tested product, and comparing the analyzed testing Mapping information with the template Mapping information source in the S3 one by one according to a preset flow;
s6, after S5 is completed, when the analytic data of the testing Mapping information of the tested product is completely consistent with the template Mapping information source, the tested product enters the next processing flow; and when the analysis data of the testing Mapping information of the tested product is inconsistent with any corresponding sub-item information in the template Mapping information source, executing S5 on the tested product until the analysis data of the testing Mapping information of the tested product is completely consistent with any corresponding sub-item information in the template Mapping information source, and entering the next processing flow.
Specifically, the key parameters to be tested at least comprise a Map naming rule, a Map format and Map contents, wherein the Map contents at least comprise a Notch direction, a test Die number and a test Die position.
Specifically, the template Mapping information source at least comprises a template Map naming rule module, a template Map format module and a template Map content module, and the template Map content module at least comprises a template Notch direction module, a template testing Die number module and a template testing Die position module.
Specifically, the storage path includes a test Map naming rule module, a test Map format module and a test Map content module, which are arranged in the test sequence and are at the same level, the test Map content module at least includes a test Notch direction submodule, a test Die number submodule and a test Die position submodule, and the Notch direction submodule, the test Die number submodule and the test Die position submodule are stored in the Map content module.
Specifically, when the S5 is performed, the test Map naming rule module and the test Map format module of the product to be tested, and the test Notch direction sub-module, the test Die number sub-module and the test Die position sub-module under the test Map content module are respectively compared with the template Map naming rule module and the template Map format module of the template Mapping information source, and the template Notch direction module, the template test Die number module and the template test Die position module under the template Map content module one by one; specifically, the Mapping information and template Mapping information source comparison process of the tested product is as follows:
sequentially comparing the test Map naming rule module and the template Map naming rule module of the tested product, comparing the corresponding information in the test Map format module and the template Map format module, comparing the corresponding information in the test Map content module and the template Map content module, when the corresponding information in the test Map content module and the template Map content module is compared, sequentially comparing the corresponding information in the test Notch direction sub-module and the template Notch direction module, the corresponding information in the test Die quantity sub-module and the template test Die quantity module, and the corresponding information in the test Die position sub-module and the template test Die position module, and all the comparison results are recorded in sequence, when any one or more comparison results are abnormal, the Mapping information is re-analyzed so as to compare one by one again.
Specifically, the creating process of the template Mapping information source in S3 is to test the target product according to the test flow established in S2, and store the test data of the target product as Mapping information into the unique storage path corresponding to the target product to serve as the template Mapping information source.
It should be noted that the test flow is established according to the critical parameters to be tested of the wafer and the storage requirements of the critical test parameters, and the corresponding critical test parameters are stored synchronously according to the established storage path as the test flow is performed.
As shown in fig. 2, an automatic checking and verifying system based on test package Mapping includes:
the input unit is used for constructing a test flow of a tested product according to the determined key parameters to be tested of the target product and constructing a storage path of test data obtained through the test flow;
a processing unit, wherein the processing unit is connected with the input unit in a communication way, and the processing unit can receive the instruction of the input unit to generate a test flow and a storage path;
the standard unit is in communication connection with the processing unit and can store the template Mapping information source according to the storage path generated by the processing unit;
the probe station is in communication connection with the processing unit, receives the instruction of the processing unit, tests the tested product according to the test flow and transmits the obtained test data to the processing unit as test Mapping information;
the storage unit is in communication connection with the processing unit and can store the test Mapping information transmitted from the probe station to the processing unit according to a storage path generated by the processing unit;
the analysis unit is in communication connection with the processing unit and calls the test Mapping information in the storage unit to analyze to obtain analysis data; specifically, because the test Map naming and the test Map format of the test Mapping information generated after each wafer is tested are unique, the test Map content of the test Mapping information of the wafer is stored corresponding to the test Map naming and the test Map format, and when the analysis unit analyzes the test data, the test Notch direction, the test Die number and the test Die position in the test Map content corresponding to the test Map naming and the test Map format can be obtained according to the test Map naming and the test Map format;
the analysis unit is in communication connection with the processing unit and compares the analysis data obtained by the analysis unit with the key parameters of the template Mapping information source in the standard unit one by one; specifically, the analysis unit firstly compares the related information in the test Map naming rule module, the test Map format module and the template Map naming rule module and the template Map format module respectively, and after the comparison is completed, the analysis unit compares the related information of the test Notch direction sub-module, the test Die number sub-module, the test Die position sub-module and the template Notch direction sub-module, the template test Die number module and the template test Die position sub-module under the test Map content module of the wafer analyzed by the analysis unit one by one; of course, for the work of the analysis unit, after the analysis unit compares the test Map naming rule module, the test Map format module, the template Map naming rule module, and the template Map format module, the analysis unit may obtain the related information in the test Notch direction module, the test Die number module, and the test Die position module under the test Map content module corresponding to the test Map naming rule module and the test Map format module of the wafer, and then the analysis unit compares the related information obtained by the analysis unit with the template Mapping information source.
Specifically, when the analysis unit detects that the primary analysis data of the testing Mapping information of the tested product is inconsistent with any corresponding key parameter in the template Mapping information source, the analysis unit analyzes the testing Mapping information again to obtain secondary analysis data; and the analysis unit compares the secondary analysis data obtained by the analysis unit with the template Mapping information source again for key parameters one by one.
Specifically, the automatic checking and checking system based on test packaging Mapping further comprises an alarm unit, wherein the alarm unit is in communication connection with the processing unit, and the alarm unit can send alarm information according to an alarm instruction of the processing unit.
Specifically, the alarm unit can at least send out secondary alarm information, when the analysis unit detects that the primary analysis data of the testing Mapping information of the tested product is inconsistent with any corresponding key parameter in the Mapping information source of the template, the processing unit sends out an alarm instruction to the alarm unit, and the alarm unit sends out primary alarm according to the alarm instruction; when the analysis unit detects that the secondary analysis data of the testing Mapping information of the tested product is inconsistent with any corresponding key parameter in the template Mapping information source, the processing unit sends a secondary alarm instruction to the alarm unit, and the alarm unit sends a secondary alarm according to the secondary alarm instruction.
The database based on the test encapsulation Mapping automatic check verification system provided by the invention is developed based on a programming C language, a matrix database of a test Map is constructed through the C language, and the format and the content of each cell are defined in a matrix diagram of the database, for example: the first row and the first column of the test Map are product names named according to a certain naming rule; the second row and the second column are the product batch number of the product, the third row and the third column are the Map content of the product, and the third row and the fourth column to the fifth column are respectively the Notch direction, the number of the testing Die and the position of the testing Die under the Map content; when testing the wafer, testing the wafer according to the constructed testing flow, and correspondingly storing the testing data of the wafer according to the constructed matrix database; and in the working process of the analysis unit and the analysis unit, data are called from the matrix database corresponding to the wafer for analysis and analysis.
It should be noted that the english words in the technical solution provided by the present invention are all common words in the semiconductor technology field, and the meaning of the english words in the technical solution provided by the present invention is the same as that in the semiconductor technology field, for example, Map is a yield distribution Map, Die is a chip, and Notch is a Notch/flat edge.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described in the foregoing embodiments, or equivalents may be substituted for elements thereof.
Claims (9)
1. A testing package Mapping based automatic checking and checking method is characterized by comprising the following steps:
s1, determining key parameters to be measured of the target product according to the performance requirement of the target product; the target product is a wafer sample meeting the requirements; the key parameters to be tested at least comprise a Map naming rule, a Map format and Map contents, wherein the Map contents at least comprise a Notch direction, a test Die number and a test Die position;
s2, constructing a test flow of the tested product according to the key parameters to be tested determined in S1, and constructing a storage path of test data obtained through the test flow;
s3, testing the target product according to the testing flow established in the S2, and taking the testing data of the target product as a Mapping information creation template Mapping information source;
s4, testing each tested product according to the testing flow constructed in the S2, and storing the testing data of each tested product as testing Mapping information into the unique storage path corresponding to the tested product;
s5, when each tested product completes the S4, analyzing the testing Mapping information in the storage path corresponding to the tested product, and then comparing the analyzed testing Mapping information with the template Mapping information source in the S3 one by one according to a preset flow;
s6, after S5 is completed, when the analytic data of the testing Mapping information of the tested product is completely consistent with the template Mapping information source, the tested product enters the next processing flow; and when the analysis data of the testing Mapping information of the tested product is inconsistent with any corresponding sub-item information in the template Mapping information source, executing S5 on the tested product until the analysis data of the testing Mapping information of the tested product is completely consistent with any corresponding sub-item information in the template Mapping information source, and entering the next processing flow.
2. The test package Mapping based automatic check verification method according to claim 1, wherein: the template Mapping information source at least comprises a template Map naming rule module, a template Map format module and a template Map content module, wherein the template Map content module at least comprises a template Notch direction module, a template testing Die number module and a template testing Die position module.
3. The test package Mapping based automatic check verification method according to claim 2, wherein: the memory path comprises a test Map naming rule module, a test Map format module and a test Map content module which are arranged according to a test sequence and are at the same level, wherein the test Map content module at least comprises a test Notch direction sub-module, a test Die number sub-module and a test Die position sub-module, and the Notch direction sub-module, the test Die number sub-module and the test Die position sub-module are stored in the Map content module.
4. The test package Mapping based automatic check verification method according to claim 3, wherein: when the S5 is performed, the test Map naming rule module and the test Map format module of the tested product, and the test Notch direction sub-module, the test Die number sub-module and the test Die position sub-module under the test Map content module are respectively compared with the template Map naming rule module and the template Map format module of the template Mapping information source, and the template Notch direction module, the template test Die number module and the template test Die position module under the template Map content module one by one.
5. The test package Mapping based automatic check verification method according to claim 1, wherein: the creating process of the template Mapping information source in the S3 is to test the target product according to the test flow constructed in the S2, and store the test data of the target product as Mapping information into the corresponding and unique storage path of the target product to serve as the template Mapping information source.
6. An automatic checking and checking system based on test package Mapping, comprising:
the input unit is used for constructing a test flow of a tested product according to the determined key parameters to be tested of the target product and constructing a storage path of test data obtained through the test flow; the target product is a wafer sample meeting the requirements; the key parameters to be tested at least comprise a Map naming rule, a Map format and Map contents, wherein the Map contents at least comprise a Notch direction, a test Die number and a test Die position;
the processing unit is in communication connection with the input unit and can receive instructions of the input unit to generate a test flow and a storage path;
the standard unit is in communication connection with the processing unit and can store the template Mapping information source according to the storage path generated by the processing unit;
the probe station is in communication connection with the processing unit, receives the instruction of the processing unit, tests the tested product according to the test flow, and transmits the obtained test data serving as test Mapping information to the processing unit;
the storage unit is in communication connection with the processing unit and can store the test Mapping information transmitted from the probe station to the processing unit according to the storage path generated by the processing unit;
the analysis unit is in communication connection with the processing unit and calls the test Mapping information in the storage unit to analyze to obtain analysis data;
and the analysis unit is in communication connection with the processing unit and compares the analysis data obtained by the analysis unit with the key parameters of the template Mapping information source in the standard unit one by one.
7. The test package Mapping based automatic inspection verification system according to claim 6, wherein: when the analysis unit detects that the primary analysis data of the testing Mapping information of the tested product is inconsistent with any corresponding key parameter in the template Mapping information source, the analysis unit analyzes the testing Mapping information again to obtain secondary analysis data; and the analysis unit compares the secondary analysis data obtained by the analysis unit with the template Mapping information source again for key parameters one by one.
8. The test package Mapping based automatic inspection verification system according to claim 7, wherein: the alarm device is characterized by further comprising an alarm unit, wherein the alarm unit is in communication connection with the processing unit and can send alarm information according to an alarm instruction of the processing unit.
9. The test package Mapping based automatic check verification system according to claim 8, wherein: the alarm unit can at least send out secondary alarm information, when the analysis unit detects that primary analysis data of the testing Mapping information of the tested product is inconsistent with any corresponding key parameter in a template Mapping information source, the processing unit sends out an alarm instruction to the alarm unit, and the alarm unit sends out primary alarm according to the alarm instruction; when the analysis unit detects that the secondary analysis data of the testing Mapping information of the tested product is inconsistent with any corresponding key parameter in the template Mapping information source, the processing unit sends a secondary alarm instruction to the alarm unit, and the alarm unit sends a secondary alarm according to the secondary alarm instruction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210299882.0A CN114416514B (en) | 2022-03-25 | 2022-03-25 | Automatic checking and verifying method and system based on test packaging Mapping |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210299882.0A CN114416514B (en) | 2022-03-25 | 2022-03-25 | Automatic checking and verifying method and system based on test packaging Mapping |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114416514A CN114416514A (en) | 2022-04-29 |
| CN114416514B true CN114416514B (en) | 2022-06-24 |
Family
ID=81263446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210299882.0A Active CN114416514B (en) | 2022-03-25 | 2022-03-25 | Automatic checking and verifying method and system based on test packaging Mapping |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114416514B (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008218259A (en) * | 2007-03-06 | 2008-09-18 | Topcon Corp | Inspection method and inspection device |
| CN103646900A (en) * | 2013-12-03 | 2014-03-19 | 西安神光皓瑞光电科技有限公司 | Test method and test system for LED wafer |
| CN105224776A (en) * | 2014-05-26 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | A kind of wafer sort result comparison method and system |
| CN108598013A (en) * | 2018-04-19 | 2018-09-28 | 上海华力微电子有限公司 | A kind of test method of wafer |
| CN109726234A (en) * | 2018-09-14 | 2019-05-07 | 上海华岭集成电路技术股份有限公司 | Integrated circuit testing Information Management System based on industry internet |
| CN111190919A (en) * | 2019-12-27 | 2020-05-22 | 上海华岭集成电路技术股份有限公司 | Automatic judgment system for integrated circuit wafer test data |
| CN111220902A (en) * | 2020-03-03 | 2020-06-02 | 北京中电华大电子设计有限责任公司 | Engineering analysis test method based on integrated circuit wafer coordinate partition |
| CN112306879A (en) * | 2020-11-02 | 2021-02-02 | 平安普惠企业管理有限公司 | Interface parameter checking method, device, equipment and storage medium |
| CN112802771A (en) * | 2021-01-28 | 2021-05-14 | 上海华力微电子有限公司 | Defect detection wafer map optimization method and optimization system thereof |
| CN112988601A (en) * | 2021-04-29 | 2021-06-18 | 中国工商银行股份有限公司 | Test script development method and device |
| CN113012410A (en) * | 2021-02-10 | 2021-06-22 | 杭州广立微电子股份有限公司 | Wafer test early warning method |
| CN113505563A (en) * | 2021-06-15 | 2021-10-15 | 安测半导体技术(江苏)有限公司 | Probe station MAP generation method and system |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108919083A (en) * | 2018-06-08 | 2018-11-30 | 上海华岭集成电路技术股份有限公司 | A method of improving Serdes IP wafer test efficiency |
| US20220011678A1 (en) * | 2020-07-13 | 2022-01-13 | Changxin Memory Technologies, Inc. | Processing method and processing system for measurement data of semiconductor device, computer device and computer readable storage medium |
| CN112597742A (en) * | 2020-12-02 | 2021-04-02 | 长春光华微电子设备工程中心有限公司 | Method for realizing self-defined test path of wafer probe station |
-
2022
- 2022-03-25 CN CN202210299882.0A patent/CN114416514B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008218259A (en) * | 2007-03-06 | 2008-09-18 | Topcon Corp | Inspection method and inspection device |
| CN103646900A (en) * | 2013-12-03 | 2014-03-19 | 西安神光皓瑞光电科技有限公司 | Test method and test system for LED wafer |
| CN105224776A (en) * | 2014-05-26 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | A kind of wafer sort result comparison method and system |
| CN108598013A (en) * | 2018-04-19 | 2018-09-28 | 上海华力微电子有限公司 | A kind of test method of wafer |
| CN109726234A (en) * | 2018-09-14 | 2019-05-07 | 上海华岭集成电路技术股份有限公司 | Integrated circuit testing Information Management System based on industry internet |
| CN111190919A (en) * | 2019-12-27 | 2020-05-22 | 上海华岭集成电路技术股份有限公司 | Automatic judgment system for integrated circuit wafer test data |
| CN111220902A (en) * | 2020-03-03 | 2020-06-02 | 北京中电华大电子设计有限责任公司 | Engineering analysis test method based on integrated circuit wafer coordinate partition |
| CN112306879A (en) * | 2020-11-02 | 2021-02-02 | 平安普惠企业管理有限公司 | Interface parameter checking method, device, equipment and storage medium |
| CN112802771A (en) * | 2021-01-28 | 2021-05-14 | 上海华力微电子有限公司 | Defect detection wafer map optimization method and optimization system thereof |
| CN113012410A (en) * | 2021-02-10 | 2021-06-22 | 杭州广立微电子股份有限公司 | Wafer test early warning method |
| CN112988601A (en) * | 2021-04-29 | 2021-06-18 | 中国工商银行股份有限公司 | Test script development method and device |
| CN113505563A (en) * | 2021-06-15 | 2021-10-15 | 安测半导体技术(江苏)有限公司 | Probe station MAP generation method and system |
Non-Patent Citations (1)
| Title |
|---|
| 陶雪芬.提高自动测试设备ATE测试板的设计效率.《集成电路应用》.2020,第37卷(第07期),42-44. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114416514A (en) | 2022-04-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112382582B (en) | Wafer test classification method and system | |
| WO2022183675A1 (en) | Semiconductor intelligent inspection system, intelligent inspection method, and storage medium | |
| CN113010413A (en) | Automatic interface testing method and device | |
| CN113888480A (en) | MES-based quality tracing method and system | |
| CN115032523A (en) | Chip automatic test method, system, computer equipment and storage medium | |
| CN113779919A (en) | Tool and method for checking integrated circuit layout design rule file | |
| CN114416514B (en) | Automatic checking and verifying method and system based on test packaging Mapping | |
| CN105653455A (en) | Program vulnerability detection method and detection system | |
| CN103336739B (en) | Method for testing software and platform | |
| US6697691B1 (en) | Method and apparatus for fault model analysis in manufacturing tools | |
| CN106033210A (en) | Wafer testing data processing method and wafer testing data processing device | |
| CN107515368B (en) | Method for dynamically modifying limit value of test program in microcircuit test | |
| US20240053398A1 (en) | Composite testing machine and method for using composite testing machine | |
| CN115147236A (en) | Processing method, processing device and electronic equipment | |
| CN112346920A (en) | Integrated circuit test data analysis method and system | |
| CN113268947A (en) | Method, system and equipment for detecting consistency of chip layout and readable storage medium | |
| CN113094258A (en) | Precise test method and device, computer equipment and medium | |
| US7137085B1 (en) | Wafer level global bitmap characterization in integrated circuit technology development | |
| US11983480B2 (en) | Check tool and check method for design rule check rule deck of integrated circuit layout | |
| CN114546845B (en) | Authentication method of functional safety software tool chain | |
| CN113393422B (en) | Method and device for determining probe card abnormity, terminal equipment and storage medium | |
| TW478087B (en) | Automatic control test system | |
| CN116067618B (en) | Automatic production and adjustment method for 800G high-speed optical module | |
| CN112819751B (en) | Method and device for processing data of detection result of polypeptide chip | |
| JP5015227B2 (en) | Defect analysis method, program, and electronic device manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |