CN108919083A - A method of improving Serdes IP wafer test efficiency - Google Patents
A method of improving Serdes IP wafer test efficiency Download PDFInfo
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- CN108919083A CN108919083A CN201810587200.XA CN201810587200A CN108919083A CN 108919083 A CN108919083 A CN 108919083A CN 201810587200 A CN201810587200 A CN 201810587200A CN 108919083 A CN108919083 A CN 108919083A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
Abstract
The invention discloses a kind of methods for improving Serdes IP wafer test efficiency, include the following steps：S10：The MAP chart of wafer test is read in real time, record corresponding coordinate, test result and failure classification information；S20：Analysing whether to test there are some site obviously has continuous failure than more or some site of other site failure, and if it exists, then carries out the project Failure Alarm when difference failure number between site or continuous failure number exceed preset quantity；S30：The characteristics of for area failures, it designs corresponding algorithm and completes statistics, quickly test result can be analyzed automatically by the realization of this method, for Serdes IP to the test more sensitive characteristic of hardware, hidden danger can be discovered and ruled out early, reduces and accidentally surveys, and to the quick extraction and analysis of area failures energy, greatly reduce the workload of artificial data analysis, improves the efficiency of Serdes IP wafer test production.
Description
Technical field
The present invention relates to communication technique field, specially a kind of method for improving Serdes IP wafer test efficiency.
Background technique
It is higher and higher to the rate of data transmission, efficiency requirements with the development of Information and Communication Technology, Traditional parallel interface
Speed have reached a bottleneck, the faster serial line interface of speed is technology trends, and Serdes is replacing tradition simultaneously
Row bus and the mainstream for becoming high-speed interface technology, the wafer test of Serdes IP sets test because of the characteristic of itself high speed
The design of standby transmission rate and test hardware all proposes higher requirement, and corresponding testing cost also just increases accordingly, but
Often in test process meeting because of such as ATE equipment (automatic test equipment, the test system being composed of test machine and computer
System) it is abnormal, probe station contact is bad etc., and several factors cause accidentally to survey, so after completing wafer test, Test Engineer is still needed to pair
A large amount of test data is analyzed and processed work, to ensure the correctness of test result.
Include tube core coordinate, test result and failure classification information in existing wafer test MAP chart, needs when practical volume production
Will manually according to MAP chart analyze and determine with the presence or absence of accidentally survey and whether because chip problem itself caused by fail, including
It is continuously accidentally surveyed caused by site failure and region chip failure, the above yield that will affect when chip die is tested, this portion
The division of labor is made often because data volume is larger and the not noticeable feature of information itself, and larger workload and erroneous judgement etc. is caused to ask
Topic influences the yield of test.
Summary of the invention
The problem of for background technique, the present invention provides a kind of raising Serdes IP wafer test efficiency
Method.
To achieve the above object, the present invention provides the following technical solutions：It is a kind of to improve Serdes IP wafer test efficiency
Method includes the following steps：
S10：The MAP chart of wafer test is read in real time, record corresponding coordinate, test result and failure classification letter
Breath；
S20：Analysing whether to test there are some site obviously has continuously than more or some site of other site failure
Failure, and if it exists, then carry out the project failure when difference failure number between site or continuous failure number exceed preset quantity
Alarm；
S30：The characteristics of for area failures, is presented continuous blocky failure, designs corresponding algorithm and complete that is, in MAP chart
Statistics, when limit value of the continuous failure number beyond setting of statistics label, then recording and marking the region is area failures；When
It is a piece of surveyed after, algorithm programming count goes out the information of these area failures and is rapidly performed by corresponding process flow so as to subsequent.
As a preferred technical solution of the present invention, in the S30 algorithm the specific steps are：When grabbing first
Fail die, records coordinate and result information, and traverse coupled coordinate pass/fail as a result, then marking if any fail
Note comes out, and continues centered on new fail die, searches the pass/fail for the coordinate die that is connected as a result, and completing corresponding mark
Note, is gone down with this.
Compared with prior art, the beneficial effects of the invention are as follows：It can be automatically quickly to survey by the realization of this method
Test result is analyzed, and for Serdes IP to the test more sensitive characteristic of hardware, can discover and rule out hidden danger early,
It reduces and accidentally surveys, and to the quick extraction and analysis of area failures energy, greatly reduce the workload of artificial data analysis, improve
The efficiency of Serdes IP wafer test production.
Detailed description of the invention
Fig. 1 is the MAP chart generated after wafer test in the prior art；
Fig. 2 is that the site analysis chart after MAP chart is tested in embodiment；
Fig. 3 is that algorithm realizes test structures statistics figure in embodiment；
Fig. 4 is MAP chart failed areas display figure in embodiment；
Fig. 5 is failed areas data statistics figure in embodiment；
Fig. 6 is that process flow diagram is analyzed in on-line testing in embodiment；
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The present invention provides a kind of method for improving Serdes IP wafer test efficiency, includes the following steps：
S10：The MAP chart of wafer test is read in real time, record corresponding coordinate, test result and failure classification letter
Breath；
S20：Analysing whether to test there are some site obviously has continuously than more or some site of other site failure
Failure, and if it exists, then carry out the project failure when difference failure number between site or continuous failure number exceed preset quantity
Alarm；
S30：The characteristics of for area failures, is presented continuous blocky failure, designs corresponding algorithm and complete that is, in MAP chart
Statistics, when limit value of the continuous failure number beyond setting of statistics label, then recording and marking the region is area failures；When
It is a piece of surveyed after, algorithm programming count goes out the information of these area failures and is rapidly performed by corresponding process flow so as to subsequent.
Wherein it is the step of algorithm in the S30：When grabbing first failure die, coordinate and result letter are recorded
Breath, and coupled coordinate pass/fail is traversed as a result, being then marked if any fail, and is continued with new fail die
Centered on, search be connected coordinate die pass/fail as a result, and complete respective markers, gone down with this.
Embodiment
Referring to Fig. 1, the MAP chart being illustrated in fig. 1 shown below can be generated after wafer test according to the prior art, wherein including XY
Coordinate information；Each coordinate pair answers the pass/fail information of die (packed integrated circuit die)：For not test zone,It is shown as test pass,It is shown as test fail；For the die of fail, ATE can be according to different test item knots
The corresponding failure bin of fruit distribution, so client can be then to fail to test at which according to specific chip is obtained in failure bin information
?.
1, testing sequence is pressed, read in real time by test machine MAP chart as a result, first test die information as shown in figure 1：x
=4, y=5, pass, Bin=1；The result of first fail die：X=7, y=3, fail, Bin=2；
2, further, since according to the relative position between sites on needle card, the coordinate of each site test has been determining
, needle card in the present embodiment is 4site needle card, and site Rankine-Hugoniot relations is vertical setting of types arrangement, it is followed successively by site1 from top to bottom,
First die coordinate of site2, site3, site4, site1 test is x=8, y=2, then all y-coordinates are 2+4i (i=0
Integer to 6) it is site1 test, all y-coordinates are that 3+4i (integer of i=0 to 6) is site2 test, and so on.
From the first step, we can read every test result for having surveyed die in real time, here, we can be to the survey of each site
Test result does real-time statistics, once encounter some site continuously fail beyond setting number or statistics failure conditions it is obviously different
In other site, difference is greater than the allowed band that we are arranged, then provides warning message in real time, search online in time and solve to ask
Topic, so as not to cause more accidentally survey and it is subsequent go again for accidentally survey situation arrange repetition measurement matters, as shown in Fig. 2, site2 exist
Continuous 5 bin2 failure, and site2 yield is significantly lower than other 3 site in terms of statistical result, difference exceeds 5%, therefore
We need to immediately search the problem of site2, and the generation of phenomenon is accidentally surveyed in reduction etc；
3, further, the case where the area failures being commonly encountered for us, corresponding algorithm is designed, the present embodiment
Specific algorithm is realized as follows：The failure die being successively read on MAP, reads its coordinate information, establishes array and saves information (x seat
Mark, y-coordinate, failed areas number, area failures number fail No. bin), the traversal MAP chart test die adjacent with its coordinate, such as
There is failure that the same failed areas is then marked to number, area failures number adds one, and saves with array formats；When in same region
It is area failures, example by the zone marker when continuous failure quantity is more than setting index：Setting area failure number is beyond 5
It is then area failures, as shown in figure 4, reading first failure die, records (7,3,1,1,2), traverse seat adjacent thereto
Mark, do not fail die, then the region, which is not sentenced, makees failed areas；Second failure die is read, with first, does not sentence and makees failure area
Domain；Third failure die is read, records (7,9,3, Isosorbide-5-Nitrae), traverses die adjacent thereto, be recorded as respectively (6,10,3,2,
4), (7,10,3,3,3)；Continue to read new failure die, traverses 8 adjacent coordinates, it is such as markd, then it marks identical
Area failures number (6,11,3,4,4), equally mark remaining Unrecorded failure die (7,11,3,5,3), (7,12,3,6,
3)；Gone down with this and records (8,11,3,7,3) respectively, (8,12,3,8,3)；When running through full wafer MAP, every failure die is completed
Label such as exceeds 5 labeled as the failure number of the same area, is then judged as area failures, can be rapidly completed one by the algorithm
The reading of piece MAP and label, and automatically come out area failures Information Statistics, faster to analyze whether it is chip itself
Problem, and feedback is made in time.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within mind and principle.
Claims (2)
1. a kind of method for improving Serdes IP wafer test efficiency, it is characterised in that include the following steps：
S10：The MAP chart of wafer test is read in real time, record corresponding coordinate, test result and failure classification information；
S20：Analysing whether to test there are some site obviously has continuous mistake than more or some site of other site failure
Effect, and if it exists, then carry out the project Failure Alarm when difference failure number between site or continuous failure number exceed preset quantity；
S30：The characteristics of for area failures, is presented continuous blocky failure, designs corresponding algorithm and complete system that is, in MAP chart
Meter, when limit value of the continuous failure number beyond setting of statistics label, then recording and marking the region is area failures；When one
After piece has been surveyed, algorithm programming count goes out the information of these area failures and is rapidly performed by corresponding process flow so as to subsequent.
2. a kind of method for improving Serdes IP wafer test efficiency according to claim 1, it is characterised in that：It is described
In S30 algorithm the specific steps are：When grabbing first failure die, record coordinate and result information, and traverse and its
Connected coordinate pass/fail if any fail as a result, be then marked, and continue centered on new fail die, lookup phase
Be punished for being related to mark die pass/fail as a result, and complete respective markers, gone down with this.
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| CN111143211A (en) * | 2019-12-24 | 2020-05-12 | 上海华岭集成电路技术股份有限公司 | Method for quickly detecting test setting accuracy in offline manner |
| CN111308318A (en) * | 2019-12-30 | 2020-06-19 | 上海华岭集成电路技术股份有限公司 | Semiconductor chip test data processing method |
| CN112462233A (en) * | 2020-11-25 | 2021-03-09 | 北京确安科技股份有限公司 | Site control method and system in integrated circuit test |
| CN112710942A (en) * | 2021-03-24 | 2021-04-27 | 上海伟测半导体科技股份有限公司 | System and method for analyzing wafer regional problem |
| CN112988792A (en) * | 2021-04-15 | 2021-06-18 | 筏渡(上海)科技有限公司 | Searching method and device for wafer yield problem database |
| CN113130342A (en) * | 2021-04-15 | 2021-07-16 | 筏渡(上海)科技有限公司 | Method and device for marking wafer low-reliability failed tube core |
| CN113270342A (en) * | 2021-04-20 | 2021-08-17 | 深圳米飞泰克科技有限公司 | Wafer test dislocation monitoring method, device, equipment and storage medium |
| CN113514753A (en) * | 2021-04-15 | 2021-10-19 | 筏渡(上海)科技有限公司 | Method and device for determining relation of wafer failure functions |
| CN113917305A (en) * | 2021-10-13 | 2022-01-11 | 海光信息技术股份有限公司 | Test method, test system, electronic device and readable storage medium |
| WO2022022164A1 (en) * | 2020-07-28 | 2022-02-03 | 长鑫存储技术有限公司 | Method and apparatus for determining abnormality of probe card |
| CN114416514A (en) * | 2022-03-25 | 2022-04-29 | 南京伟测半导体科技有限公司 | Automatic checking and verifying method and system based on test packaging Mapping |
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| CN112462233A (en) * | 2020-11-25 | 2021-03-09 | 北京确安科技股份有限公司 | Site control method and system in integrated circuit test |
| CN112710942A (en) * | 2021-03-24 | 2021-04-27 | 上海伟测半导体科技股份有限公司 | System and method for analyzing wafer regional problem |
| CN112710942B (en) * | 2021-03-24 | 2021-06-08 | 上海伟测半导体科技股份有限公司 | System and method for analyzing wafer regional problem |
| CN112988792A (en) * | 2021-04-15 | 2021-06-18 | 筏渡(上海)科技有限公司 | Searching method and device for wafer yield problem database |
| CN113514753A (en) * | 2021-04-15 | 2021-10-19 | 筏渡(上海)科技有限公司 | Method and device for determining relation of wafer failure functions |
| CN113130342A (en) * | 2021-04-15 | 2021-07-16 | 筏渡(上海)科技有限公司 | Method and device for marking wafer low-reliability failed tube core |
| CN112988792B (en) * | 2021-04-15 | 2022-05-31 | 筏渡(上海)科技有限公司 | Searching method and device for wafer yield problem database |
| CN113270342A (en) * | 2021-04-20 | 2021-08-17 | 深圳米飞泰克科技有限公司 | Wafer test dislocation monitoring method, device, equipment and storage medium |
| CN113917305A (en) * | 2021-10-13 | 2022-01-11 | 海光信息技术股份有限公司 | Test method, test system, electronic device and readable storage medium |
| CN114416514A (en) * | 2022-03-25 | 2022-04-29 | 南京伟测半导体科技有限公司 | Automatic checking and verifying method and system based on test packaging Mapping |
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Application publication date: 20181130 |