CN115270675B - Method for checking ESD cross-domain interface based on command file - Google Patents
Method for checking ESD cross-domain interface based on command file Download PDFInfo
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- CN115270675B CN115270675B CN202211200522.7A CN202211200522A CN115270675B CN 115270675 B CN115270675 B CN 115270675B CN 202211200522 A CN202211200522 A CN 202211200522A CN 115270675 B CN115270675 B CN 115270675B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The invention discloses a method for checking an ESD cross-domain interface based on a command file, which relates to the field of chip control and comprises the following steps: step 1: collecting client feedback information; step 2: finding out the position of the internal ESD protection circuit by using a cross-power domain checker; and step 3: and carrying out ESD failure analysis based on the position of the ESD protection circuit and the customer feedback information. Compared with the prior art, the invention has the beneficial effects that: according to the invention, the fault chip is comprehensively analyzed through the cross-power-domain detector, the ESD engineer experience is not excessively relied on, the integrity of damage analysis and inspection can be increased by integrating the innovative cross-power-domain detection process and the traditional chip ESD fault detection process, and the high success rate of failure analysis is achieved.
Description
Technical Field
The invention relates to the field of chip control, in particular to a method for checking an ESD cross-domain interface based on a command file.
Background
In order to obtain more performance, a chip usually includes a plurality of different power domains, however, when a chip product having a plurality of different power domains is subjected to ESD stress, an unexpected discharge current path is often generated, and interface circuits between different power domains are easily damaged, thereby causing a fault across the power domains. When a product fails, the fault position and the forming mechanism thereof need to be analyzed, in the prior art, analysis can be usually performed only based on the experience of an ESD engineer, the dependence on the experience of the engineer is strong, and the fault position and the forming mechanism thereof are difficult to determine and difficult to obtain quickly, effectively and accurately due to uncertain discharge circuit paths.
Disclosure of Invention
The present invention is directed to a method for checking an ESD cross-domain interface based on a command file, so as to solve the problems mentioned in the background art.
In order to achieve the purpose, the invention provides the following technical scheme:
a method for checking an ESD cross-domain interface based on a command file comprises the following steps:
step 1: collecting client feedback information;
step 2: finding out the position of the internal ESD protection circuit by using a cross-power domain checker;
and step 3: and carrying out ESD failure analysis based on the position of the ESD protection circuit and the customer feedback information.
As a still further scheme of the invention: the finding the location of the internal ESD protection circuit using the cross-power domain checker comprises: the cross-power domain checker checks a circuit network table and/or a circuit layout of the chip, and finds out the position of the ESD protection circuit in the chip from the circuit network table and/or the circuit layout.
As a still further scheme of the invention: and making the cross-power domain checker by using the command file, then selecting a cross-domain projection equipment library, acquiring a chip internal netlist file and/or performing design rule check through the cross-power domain checker, and forming a core ESD risk point mapping report based on the internal netlist file and/or performing the design rule check.
As a still further scheme of the invention: and using the command file to check an ESD (electro-static discharge) cross-power domain interface, searching or extracting specified conditions and information which accord with the ESD protection circuit from the circuit network table and/or the circuit layout, and determining the position of the ESD protection circuit based on the specified conditions and information.
As a still further scheme of the invention: the step 12 is included between the step 1 and the step 2: performing preliminary judgment on failure analysis, and preliminarily determining an ESD failure mechanism and reason; or the step 12 is included between the step 2 and the step 3: and carrying out primary judgment on failure analysis, and primarily determining an ESD failure mechanism and a reason.
As a still further scheme of the invention: step 12 is followed by step 13: and performing nondestructive analysis to obtain a nondestructive analysis result.
As a still further scheme of the invention: step 13 is followed by step 14: based on the non-destructive analysis results of step 13, the analysis method is improved.
As a still further scheme of the invention: step 14 is followed by step 15: a destructive analysis is performed and a destructive analysis result is obtained.
As a still further scheme of the invention: said step 15 is followed by a step 16: a fault or damage location is obtained based on the destructive analysis results.
As a still further scheme of the invention: before the destructive analysis is executed, selecting the corresponding destructive analysis position based on the position information of the ESD protection circuit.
Compared with the prior art, the invention has the beneficial effects that: according to the invention, the fault chip is comprehensively analyzed through the cross-power-domain inspector, the ESD engineer experience is not excessively relied on, the integrity of damage analysis and inspection can be increased by integrating the innovative cross-power-domain inspection flow and the traditional chip ESD fault detection flow, the high success rate of failure analysis is achieved, and the failure analysis result can be rapidly, effectively and accurately and completely obtained; furthermore, the cross-power-domain checker is made by using a command file, analyzes the cross-power-domain interface, can analyze without increasing hardware, has wide applicability, and is suitable for various chips with multiple power domains.
Drawings
Fig. 1 is a schematic diagram of a possible ESD failure of a chip.
FIG. 2 is a flow chart of the chip ESD fault detection according to the present invention.
FIG. 3 is a flow chart of a method for checking an ESD cross-power interface based on a command file.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and all other embodiments obtained by a person of ordinary skill in the art without creative efforts based on the embodiments of the present invention belong to the protection scope of the present invention.
As shown in fig. 1, when a chip product with multiple power domains, specifically, a driving buffer and a receiving buffer, experiences ESD stress, an unexpected discharge current path often exists, and an interface circuit between different power domains is easily damaged, such as an abnormal discharge path shown by an arrow in fig. 1.
To solve the above technical problem, as shown in fig. 2, a flow chart of chip ESD fault detection is provided, according to the following technical solution:
a method for checking an ESD cross-domain interface based on a command file comprises the following steps:
step 1: collecting client feedback information;
step 2: finding out the position of the internal ESD protection circuit by using a cross-power domain checker;
and step 3: and carrying out ESD failure analysis based on the position of the ESD protection circuit and the customer feedback information.
Specifically, customer feedback information is collected firstly to determine that the chip has ESD cross-power domain faults, so that fault analysis is carried out on the chip based on faults, and the fault position and the forming mechanism of the chip are found. When the feedback information of the client is collected, the testing method can be collected, and a proper testing method is selected based on the internal structure of the chip and the fault characteristics. In order to rapidly, accurately and effectively analyze the fault, the invention creatively uses a cross-power-domain checker to find out the position of an internal ESD protection circuit, and carries out ESD failure analysis based on the position of the ESD protection circuit and the customer feedback information. For an ESD fault, an ESD protection circuit is usually triggered when the ESD protection circuit fails, a substantial difference exists between the triggered ESD protection circuit and the non-triggered ESD protection circuit, and a certain position relationship and a certain signal connection relationship exist between the position of the ESD protection circuit and each power domain, so that more comprehensive related information can be provided for finding out the position of the internal ESD protection circuit, and the position can be used for identifying an accurate entity damage position.
As a still further scheme of the invention: as shown in fig. 3, a flowchart of a method for checking an ESD cross-power interface based on a command file is provided, where the finding of the location of the internal ESD protection circuit using a cross-power domain checker includes: the cross-power domain checker checks a circuit network table and/or a circuit layout of the chip, and finds out the position of the ESD protection circuit in the chip from the circuit network table and/or the circuit layout. The chip is manufactured by referring to the circuit layout, the circuit layout is an materialization of the circuit netlist, and the command file method can search and extract specified conditions and information from the circuit netlist or the circuit layout, so that the position of the internal ESD protection circuit is creatively found based on the circuit netlist and/or the circuit layout.
As a still further scheme of the invention: the cross-power domain checker is built using a command file. In the practical application process, if excessive hardware is additionally added, the cost is increased, the use is difficult, and the applicability is poor, the invention creatively uses the command file to make the cross-power domain checker, and searches and extracts the specified conditions and information from the circuit netlist or the circuit layout by the command file method. After the cross-power domain checker is made, a cross-domain projection device library (including ggMOS and/or diode types) is selected, a chip internal netlist file is obtained through the cross-power domain checker and/or design rule check is carried out, and a core ESD risk point mapping report is formed on the basis of the internal netlist file and/or the design rule check.
As a still further scheme of the invention: and using the command file to check an ESD (electro-static discharge) cross-power domain interface, searching or extracting specified conditions and information which accord with the ESD protection circuit from the circuit network table and/or the circuit layout, and determining the position of the ESD protection circuit based on the specified conditions and information. When the chip is designed, a corresponding interface exists across the power domain, and the interface has a certain corresponding relation with the ESD protection circuit or the power domain.
As a still further scheme of the invention: as shown in fig. 3, step 12 is included between step 1 and step 2: performing preliminary judgment on failure analysis, and preliminarily determining an ESD failure mechanism and reason; or the step 12 is included between the step 2 and the step 3: and carrying out primary judgment on failure analysis, and primarily determining an ESD failure mechanism and a reason. In order to preliminarily determine the ESD failure mechanism and the cause, the determination is performed only through the experience of an engineer in the prior art, but the determination may also be performed based on the position of the internal ESD protection circuit found by the cross-power-domain checker, in which case, the dependence on the experience of the engineer is not strong, and even in some cases, the preliminary determination may be performed only through the position of the internal ESD protection circuit found by the cross-power-domain checker. The position of the ESD protection circuit can be obtained after the preliminary judgment, so that the preliminary judgment is further optimized according to the position of the ESD protection circuit, and the accuracy of the preliminary judgment is improved.
As a still further scheme of the invention: the step 12 is followed by a step 13: and performing nondestructive analysis to obtain a nondestructive analysis result. After the position of the ESD protection circuit and the preliminary failure determination, nondestructive analysis is required to further determine the failure and failure mechanism, so that the analysis method is improved based on the nondestructive analysis result of step 13.
As a still further scheme of the invention: after said step 14, a step 15 is included: performing a destructive analysis and obtaining a destructive analysis result, said step 15 being followed by a step 16 of: obtaining a fault or damage location based on the destructive analysis result, and selecting a corresponding destructive analysis location based on the location information of the ESD protection circuit before performing the destructive analysis. In order to accurately obtain a fault or damaged position and a failure mechanism thereof and perform destructive analysis on a chip, the invention can quickly, accurately and effectively find the position for performing destructive analysis based on the position of the ESD protection circuit and a non-destructive analysis result, and can obtain a corresponding fault position, a failure mechanism and a root cause thereof even under one-time simple damage.
According to the invention, the fault chip is comprehensively analyzed through the cross-power-domain inspector, the ESD engineer experience is not excessively relied on, the integrity of damage analysis and inspection can be increased by integrating the innovative cross-power-domain inspection flow and the traditional chip ESD fault detection flow, the high success rate of failure analysis is achieved, and the failure analysis result can be rapidly, effectively and accurately and completely obtained; furthermore, the cross-power-domain checker is made by using a command file, analyzes the cross-power-domain interface, can analyze without increasing hardware, has wide applicability, and is suitable for various chips with multiple power domains.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (6)
1. A method for checking an ESD cross-domain interface based on a command file comprises the following steps:
step 1: collecting client feedback information;
step 2: finding the location of internal ESD protection circuits using a cross-power domain checker, comprising: the cross-power domain checker checks a circuit network table and/or a circuit layout of a chip, and finds out the position of an ESD protection circuit in the chip from the circuit network table and/or the circuit layout;
and 3, step 3: carrying out ESD failure analysis based on the position of the ESD protection circuit and the customer feedback information;
wherein, still include in step 2: using a command file to make the cross-power domain checker, then selecting a cross-power domain projection equipment library, obtaining a chip internal netlist file and/or performing design rule check through the cross-power domain checker, and forming a core ESD risk point mapping report based on the internal netlist file and/or performing the design rule check;
wherein, still include in step 2: using the command file to check an ESD (electro-static discharge) cross-power domain interface, searching or extracting specified conditions and information which accord with the ESD protection circuit from the circuit netlist and/or the circuit layout, and determining the position of the ESD protection circuit based on the specified conditions and information;
the step 12 is included between the step 1 and the step 2: performing preliminary judgment on failure analysis, and preliminarily determining an ESD failure mechanism and reason; or the step 12 is included between the step 2 and the step 3: and carrying out primary judgment on the failure analysis, and primarily determining an ESD failure mechanism and a reason.
2. The method for checking the ESD cross-domain interface based on the command file according to claim 1, wherein the step 12 is followed by the step 13 of: and performing nondestructive analysis to obtain a nondestructive analysis result.
3. The method for checking the ESD cross-domain interface based on the command file according to claim 2, wherein the step 13 is followed by the step 14 of: based on the non-destructive analysis results of step 13, the analysis method is improved.
4. The method for checking ESD cross-domain interface based on command file according to claim 3, characterized in that said step 14 is followed by the step 15: a destructive analysis is performed and a destructive analysis result is obtained.
5. The method for checking ESD cross-domain interface based on command file according to claim 4, characterized in that the step 15 is followed by the step 16: a fault or damage location is obtained based on the destructive analysis results.
6. The method for checking ESD cross-domain interface based on command file according to claim 4 or 5, characterized in that before performing the destructive analysis, the corresponding destructive analysis location is selected based on the location information of the ESD protection circuit.
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| US11233046B1 (en) * | 2019-03-29 | 2022-01-25 | Jesse Conrad Newcomb | Logical detection of electronic circuit power sequence risks |
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| CN111239590B (en) * | 2020-02-24 | 2020-12-04 | 珠海格力电器股份有限公司 | Method and device for positioning electrostatic damage of chip |
| US20230153512A1 (en) * | 2020-03-25 | 2023-05-18 | Cady Solutions Ltd. | Electrical circuit design inspection system and method |
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