CN111220902A

CN111220902A - Engineering analysis test method based on integrated circuit wafer coordinate partition

Info

Publication number: CN111220902A
Application number: CN202010137844.6A
Authority: CN
Inventors: 鲁小妹; 姜京哲
Original assignee: Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Beijing CEC Huada Electronic Design Co Ltd
Priority date: 2020-03-03
Filing date: 2020-03-03
Publication date: 2020-06-02

Abstract

The invention discloses an engineering analysis evaluation and test verification method based on integrated circuit wafer coordinate partition. The whole process of engineering analysis at the chip level comprises a plurality of links such as wafer processing, wafer testing, sample wafer packaging, sample wafer verification, sample wafer performance analysis and the like. The method provided by the invention can effectively improve the efficiency of verification and evaluation of the multi-factor combined debugging item. The method is based on the design of a wafer coordinate partition scheme, different combined debugging items are executed on the chip partitions on one wafer in the wafer testing stage, the difference marking of various chips is realized through map post-processing, and finally the classification verification and evaluation of the packaged chips are realized. The method has the advantages that serial verification can be converted into parallel verification, and meanwhile, the problem that local characteristic failure patterns generated by process differences among different wafers influence final evaluation conclusions can be effectively avoided. But also reduces the difficulty of developing the wafer test program and is easier to realize.

Description

Engineering analysis test method based on integrated circuit wafer coordinate partition

Technical Field

The invention belongs to the field of test development of integrated circuit chips, and particularly relates to engineering verification work for verifying chip functional performance of different combined debugging items.

Background

With the further reduction of the size of the semiconductor processing technology, at the deep submicron level, it is difficult for many integrated circuit chips to ensure the yield and the consistency without adjusting Trim or configuration parameters. Especially, for some critical simulation parameters such as the inside of a module with a small-sized pattern set, such as NVM or RAM, or with a small margin in system design, it is usually necessary to adjust Trim or configuration parameters to ensure the consistency of chip functional performance. And some parameters may exist that only certain specific combined debug items can optimize them. For product analysis evaluation and test verification, sometimes the chip overall performance is not always exposed in one test, and sufficient evaluation and verification in a chip application environment is required. This requires the engineer to find several optimal debugging items from dozens or even dozens of combined optimal debugging items. However, if each optimized debugging item is processed, tested, packaged, verified, analyzed and evaluated according to the conventional method, the engineering period is inevitably very long, and the requirement of rapidly selling the product is difficult to meet.

In view of the above, it is necessary to reduce the whole engineering cycle as much as possible, fully utilize the characteristics of the wafer stage, and perform test verification and analysis and evaluation of various optimized debugging items in parallel. Therefore, the invention combines the coordinate information inherent in the wafer test, realizes the block test through an ATE program, generates the pickup map in blocks, and then carries out the block packaging and block verification. The parallel output of various optimized debugging item configuration chips is realized, the targeted verification of process characteristics can be realized according to the previous process characteristics, and the possibility that the influence of local process deviation on the final evaluation conclusion is eliminated.

Disclosure of Invention

The invention aims to shorten the process of screening several optimal optimized debugging items from a great number of combined debugging items by engineering technicians and solve the problems that the period is long and the final evaluation conclusion is easily influenced by local process defects.

The invention relates to an engineering analysis test method based on wafer coordinate partition. The wafer test is a necessary link for wafer delivery, and a map can be automatically generated according to inherent coordinate information in the process for packaging and picking. During the packaging and picking process, the coordinate of the chip is determined according to the coordinate. The method utilizes the link, realizes automatic partition configuration of different debugging items through an ATE program, realizes chip classification by utilizing a coordinate partition scheme during wafer level testing, further realizes chip classification packaging, and realizes parallel analysis evaluation and test verification of combined debugging items.

The specific technical scheme is described as follows:

1. because the whole thought adopts the coordinates as the basis for chip identification, in order to facilitate the wafer to reduce the marking and packaging, and then identify which debugging item is adopted by the chip for testing, the internal storage unit of the chip is needed to be utilized, and the parameters of the combined debugging item and the coordinates of the chip on the wafer can be recorded in the chip. And simultaneously, parameters and coordinates written in the chip can be read out through an external command.

2. For the design of the wafer coordinate partition scheme, the X, Y coordinates of the chips on the wafer are used as the reference, and partition is carried out according to the requirement. The partitioning method can be various, and can be divided into matrix type, strip type or specific region type. In order to ensure that chips with various processing conditions can be configured with the conditions of various debugging items as much as possible. It is simply common to periodically change the debug item in X-axis coordinates. By way of example, fig. 1 is illustrated in detail: and adding 1 to the combined debugging item number every time the X coordinate is increased by 1, if n debugging items are in total, testing all chips with the X coordinate of 1 by using the debugging item 1 as a condition, testing all chips with the X coordinate of 2 by using the debugging item 2 as a condition, … …, testing all chips with the X coordinate of n by using the debugged item n as a condition, testing all chips with the X coordinate of n +1 by using the debugging item 1 as a condition, and thus, corresponding the chips to the debugging item numbers in a mode of taking the remainder of X/n as the debugging item number. In order to realize automatic configuration, the test items can be packaged into a specific test item, and the test item is used for realizing the branching of program flow and realizing the partition parallel of subsequent parameter writing. Completing the test of the whole wafer; in order to realize uniform distribution of the final samples, the samples of each debugging item are recommended to cover the process areas of the whole wafer in all directions, such as the area division of the samples according to the periodic areas of the process processing can be realized without considering the development complexity. And then, testing the selected wafer only by a test program with a partition scheme, and recording the combined debugging item and the coordinates of the chip on the wafer in the chip by parameter configuration so as to confirm the corresponding relationship between the parameters and the coordinates of the chip sample in the follow-up process.

3. Because the test program containing the region division algorithm is used for respectively carrying out parameter configuration and test on different partitions of the wafer, the yield and the Bin value distribution of various configured regions can be subjected to secondary processing of software through the test log, Bin map and inkless map of the chip. And distinguishing pass chips of different regions and different debugging items by using different marks on the bin map and the inkless map so as to respectively pick up the pass chips by using picking-up equipment according to the distinguishing marks and realize the classified picking-up and packaging of the samples.

4. After the log and bin map of various debugging item configurations and tests are obtained, the influence of each debugging item on the yield can be analyzed according to the actual bin value distribution condition of each partition, and the influence of each debugging item on each electrical parameter or AC parameter can be quantitatively analyzed. Meanwhile, the influence of the position on the wafer is considered in the early stage partitioning scheme, and the sensitivity of the process graph to various debugging items can be determined.

5. After the classified and packaged samples are obtained, comprehensive evaluation and verification can be performed by using samples configured by various debugging items. And parallel testing and parallel comparison of various debugging items are realized, and reliability verification can be performed in parallel under the condition of resource permission. And acquiring the configured results of various debugging items in a verification period. And analyzing how different debugging item configurations influence the functions and the performances of the chip to acquire quantitative transverse comparison data.

Drawings

FIG. 1 is a schematic view of the X-coordinate division

FIG. 2 is a comparison of the conventional combined debugging item evaluation process and the overall process of the method

FIG. 3 is a schematic diagram of a map after processing after partition testing of the map according to X coordinates

Detailed Description

The invention relates to a method for evaluating and analyzing a debugging item combination scheme. Based on the partition of a wafer test link, the packaging grouping of chips on the wafer is realized by matching with a map picking technology, and the grouping test verification of packaged samples is realized by the aid of the packaging grouping technology, so that the aim of transverse comparison and evaluation of various combination schemes is fulfilled. The flow chart is shown in figure 2.

According to the traditional method, the combined debugging items need to be subjected to CP, packaging and test verification one by one, and the purpose of selecting the optimal scheme can be finally achieved. If there is a combined debugging item, n rounds of the above-mentioned process are required. After the method is adopted, n serial tests can be combined into one test. Greatly shortening the whole time course. The key technical points used in the process comprise:

1. the partitioning algorithm module in the ATE program of the invention is performed based on the X coordinate. The basic principle of the program is that the chip coordinate information acquired from the probe station is calculated by division and remainder calculation according to the number of required combination types, and the test flow of the chip is divided into the appointed subsequent test flow according to the value of the remainder. Taking the case of 3 debug items as an example, the difference between the wafer test performed by the method and the conventional wafer test is shown in fig. 3:

2. a test data analysis tool required by partition test and generation of an inkless map is used for dividing and sorting data according to a coordinate rule based on chip coordinates and raw data output by ATE (automatic test equipment), independently taking a Bin value and coordinates of each type of coordinates to generate a new raw data file, and then generating corresponding Binmap and the inkless map of each partition by utilizing the raw data.

3. And the automatic picking equipment based on the map is utilized to realize the independent picking of the n map images corresponding to the n debugging items. And divided into n groups. Packaging and testing are performed separately.

4. The n groups of samples were individually validated and tested for lateral comparisons. And analyzes the correlation between the result and the debugging item. And ultimately the selection of debug items.

Claims

1. A project analysis test method based on integrated circuit wafer coordinate partition is characterized in that during wafer level test, chip classification is realized by using a coordinate partition scheme, chip classification packaging is further realized, and parallel analysis evaluation and test verification of combined debugging items are realized, and the method mainly comprises the following steps: 1) in the chip design stage, a corresponding method is designed to record the coordinate information of the chip in the wafer test in the chip; 2) designing a wafer coordinate partition scheme according to requirements, and writing configuration parameters of different combined debugging items into a chip of a specified area in an ATE test program according to the scheme; 3) performing post-processing on the map file after the wafer test to realize classification marking of chips in different partitions, and further performing classification picking and packaging; 4) analyzing the test yield and failure pattern of each partition wafer on the map of the classified marks; 5) and carrying out subsequent analysis evaluation and test verification on each partition sample on the classified and packaged samples.

2. The method as claimed in claim 1, wherein, in the chip design stage, step 1) designs a corresponding method to record the coordinate information of the chip during the wafer test in the chip: in order to facilitate the wafer to reduce the package, and identify which debugging item is adopted by the chip for testing, the mark of the combined debugging item and the coordinate of the chip on the wafer can be recorded in the chip by using a storage unit in the chip, and meanwhile, the parameter configuration and the coordinate written in the chip can be read out through an external command.

3. The method as claimed in claim 1, wherein the step 2) performs design of a wafer coordinate partition scheme as required, and writes configuration parameters of different combined debug items into the chips in the designated area according to the scheme in the ATE test program: according to the requirement of later-stage parallel analysis, designing a wafer coordinate partitioning scheme, namely, according to the requirement of parallel analysis, enabling the regular change of an X/Y coordinate to correspond to debugging items, and writing different combined debugging items into a chip in a specified area according to the scheme in an ATE test program; dividing the wafer into zones according to requirements by taking X, Y coordinates of the chips on the wafer as a reference to finish the test of the whole wafer; in order to realize uniform distribution of the final samples, the samples of each debugging item are recommended to cover the process areas of the whole wafer in all directions, such as the area division of the samples according to the periodic areas of the process processing can be realized without considering the development complexity.

4. The method as claimed in claim 1, wherein the step 3) performs post-processing on the map file after the wafer test to realize classification and marking of chips in different partitions, and further performs classification, picking and packaging: software post-processing is carried out on the infl map data of the wafer bin map to be tested and the infl map data according to the rule of the test subarea, different marks are utilized on the bin map and the infl map, and pass chips in different areas and different debugging items are distinguished, so that the samples are respectively picked up according to the distinguishing marks by using pickup equipment, and the classified pickup and encapsulation of the samples are realized.

5. The method as claimed in claim 1, wherein the step 4) is performed to analyze the test yield and failure pattern of each partition wafer on the map of the classification mark: due to the fact that different debugging item configurations are conducted on the chip partitions, the yield and the Bin value distribution of various configuration areas, regional analysis of failure conditions of various test items can be achieved through secondary processing of subsequent wafer test data.

6. The method of claim 1, wherein step 5) performs subsequent analytical evaluation and test validation of each partitioned sample on the classified packaged samples: through the classified pickup and packaging of samples in different areas, the final comparison verification and the determination of debugging items can be completed through the grouping test verification of subsequent samples.