KR102375702B1 - Test Apparatus and Method of Testing Wafer Using The Same - Google Patents

Abstract

It is a technology related to a test apparatus and a wafer test method using the same. An example of a wafer test method is as follows. First, a center zone and an edge zone of the wafer are divided. Next, the dies of the wafer positioned in the center zone are tested under a first test condition. The dies of the wafer located in the edge zone are tested under a second test condition different from the first test condition.

Description

Test Apparatus and Method of Testing Wafer Using The Same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer test method, and more particularly, to a wafer test method in which different test conditions are applied by dividing a wafer into regions.

In general, a semiconductor manufacturing process includes a fabrication (FAB) process of forming a plurality of semiconductor devices on a wafer, an electrical parameter monitoring (EPM) process of inspecting electrical characteristics of each device formed on the wafer, and separation of respective dies on the wafer. , including an assembly process for sealing.

Among them, the EPM process is a process for testing electrical characteristics of a semiconductor device formed on a die. By detecting and repairing or discarding a defective semiconductor device, the time and cost required for a subsequent assembly process and package inspection can reduce

Such an EPM process may be a process of applying excessive stress to the semiconductor device and determining a semiconductor device that cannot withstand the stress as defective. Such an EPM process may be performed, for example, in a probe test apparatus.

The probe test apparatus may include a plurality of dies constituting the wafer and a probe card respectively in contact with the plurality of dies. The probe test apparatus may provide a test signal to a corresponding die by using the probe card as an interface.

On the other hand, semiconductor wafers may have different characteristics of manufactured devices according to positions. This may be due to the fact that the process environment is not the same depending on the location of the wafer.

However, since the current semiconductor device test process is performed under the same conditions for all dies on the wafer, it is difficult to accurately find defects in the dies.

An object of the present invention is to provide a wafer test method capable of performing a test under different conditions for each position of the wafer.

A wafer test method according to an embodiment of the present invention includes the steps of distinguishing a center zone and an edge zone of a wafer; testing the dies of the wafer located in the center zone under a first test condition; and testing the dies of the wafer located in the edge zone under a second test condition different from the first test condition.

In addition, the wafer test method according to another embodiment of the present invention comprises the steps of classifying a die at a position where leaks and defects occur more than a predetermined number of times in a wafer through a plurality of wafer test processes into leak and error dies; testing normal dies excluding the leak and faulty dies under a first test condition; and testing the leak and fault dies under a second test condition different from the first test condition.

A tester according to an embodiment of the present invention is a probe test apparatus using, as an interface, a probe card that is in contact with a plurality of dies constituting a wafer and detects electrical characteristics of semiconductor devices formed on the dies as an interface, and location information of the dies. and a storage module including at least one test condition; and a control module that receives the location information and the test condition and applies the binary test condition to each die of the wafer.

According to the present invention, dies are classified on a wafer in consideration of positions according to positions or error occurrence frequencies, and different test conditions are applied to the classified dies to perform a probe test. Accordingly, it is possible to more accurately test a die in an edge region or a region having a high frequency of errors.

1 is a block diagram schematically showing a wafer test system according to an embodiment of the present invention.
2 is a schematic plan view of a wafer according to an embodiment of the present invention.
3 is a cross-sectional view illustrating a probe card and a die for explaining a probe test method according to an embodiment of the present invention.
4 is a flowchart illustrating a wafer test method according to an embodiment of the present invention.
5 is a plan view of a wafer according to another embodiment of the present invention.
6 is a flowchart illustrating a wafer test method according to another embodiment of the present invention.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims. Sizes and relative sizes of layers and regions in the drawings may be exaggerated for clarity of description. Like reference numerals refer to like elements throughout.

1 is a block diagram schematically illustrating a wafer test system according to an embodiment of the present invention. 2 is a schematic plan view of a wafer according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view showing a probe card and a die for explaining a probe test method according to an embodiment of the present invention.

Referring to FIG. 1 , a wafer test system 10 of the present invention may include a test apparatus 100 and an interface 200 .

The test apparatus 100 may be, for example, a probe test apparatus, and the test apparatus 100 may include a storage module 150 and a control module 160 therein. In the present embodiment, the control module 160 is provided in the test apparatus 100 , but in the case of a die-by-die test, it may be positioned on a wafer in the form of an element. The storage module 150 may be, for example, a per site RAM (PSR), and the storage module 150 may store at least one test condition.

Here, the test conditions include, for example, voltage conditions such as VPP, Vcore, VCP, VBB, and VBBW, and timing conditions such as write recovery time (tWR), row precharge time (tRP), and RAS to CAS delay (tRCD). can do.

The storage module 150 of this embodiment has a first test condition (TM1: VPP, Vcore, VCP, VBB, VBBW and tWR, tRP, tRCD,..) corresponding to a normal test condition and a first condition more severe than the first condition. The second test condition TM2 corresponding to the condition may be stored. For example, the second test condition TM2 is a voltage (VPP+a, Vcore+b, VCP+c, VBB+d, VBBW+e. .) and faster timings (tWR-t1, tRP-t2, tRCD-t3).

The interface 200 is a means for electrically connecting the wafer 300 and the test apparatus 100 , and may be, for example, a probe card. The probe card may be electrically connected to dies of the wafer 300 to transmit electrical signals to devices formed on the wafer 300 to the test apparatus 100 .

Meanwhile, the wafer 300 may include a plurality of dies 310 as shown in FIG. 2 . Each die 310 includes a plurality of electrical pads (not shown), and the pads are electrically connected to respective electrodes of a semiconductor device formed on the die 310 through interconnections (not shown). can be connected

In addition, the wafer 300 may be divided into a center zone (C) and an edge zone (E), and a predetermined number of dies may be positioned in each of the center zone (C) and the edge zone (E). The position information of the center die located in the center zone C and the position information of the edge die located in the edge zone E may be respectively stored in the storage module 150 of the test apparatus 100 .

Meanwhile, as shown in FIG. 3 , the probe cards 200a corresponding to the interfaces 200 may be respectively formed at positions corresponding to the respective dies 310 . The probe card 200a may include a probe substrate 210 and a plurality of needles 220 . During the test process, the plurality of needles 220 may be in contact with the pad 320 positioned on the die 310 to test electrical characteristics of a semiconductor device formed on the die 310 .

Referring again to FIG. 1 , the control module 160 of the test apparatus 100 may receive location information and test conditions TM1 and TM2 of the dies 310 stored in the storage module 150 . When testing the center zone die, the control module 160 applies the first test condition TM1 through the corresponding probe card 200a. When testing the edge zone die, the control module 160 applies the first test condition TM1 through the corresponding probe card 200a. 2 Apply the test condition (TM2).

In general, the center zone dies positioned in the center zone may have better electrical characteristics than the engine zone dies positioned in the edge zone because a semiconductor device manufacturing process is performed under relatively optimal process conditions.

As an example, in the case of the plasma deposition process, since the dies in the center zone are disposed to face the center of the shower head, a film having a desired thickness may be deposited under a set plasma density.

On the other hand, since the dies of the edge zone are disposed at the edge of the shower head, the plasma density is relatively lower than that of the center zone. Due to this, a film having a thickness smaller than the set thickness may be formed on the edge zone dies.

Accordingly, even if the same process is performed, the thickness and material properties of the device layer formed on the edge zone die and the thickness and material properties of the device layer formed on the center zone die may be poor.

In consideration of this point, in the present embodiment, by separately testing the center zone die and the edge zone die of the wafer, the performance of the semiconductor device formed on the edge zone die can be more precisely tested. In addition, in the case of the zone-by-zone test, the test may be performed through a control module in the test apparatus, and in the case of the die-by-die test, the test may be performed by adding a control module in the form of a control element in the wafer.

4 is a flowchart illustrating a wafer test method according to an embodiment of the present invention.

Referring to FIG. 4 , a center zone and an edge zone of the wafer are divided, and location information of a die positioned in the center zone and location information of a die positioned in the edge zone are stored in the storage module 150 of the test apparatus 100 . do (S1). As described above, the storage module 150 may store the first test condition TM1 corresponding to the normal test condition and the second test condition TM2 corresponding to the severe test condition.

Next, the control module 160 of the test apparatus 100 receives the position information of the dies and the first and second test conditions, and applies the first test condition TM1 to the probe card in contact with the center zone die, A second test condition TM2 is applied to the probe card in contact with the edge zone die (S2).

The performance of the semiconductor device formed on the edge zone die may be relatively lower than that of the semiconductor device formed on the die or the center zone die. Therefore, by performing the test under relatively harsh conditions, such as high voltage application and fast cycle condition, or low voltage application and slow cycle condition, a defect in the semiconductor device can be tested.

5 is a plan view of a wafer according to another embodiment of the present invention, and FIG. 6 is a flowchart of a wafer test method according to another embodiment of the present invention.

In the above embodiment, the wafer is divided into a center zone and an edge zone, and the test is dualized. However, as shown in FIG. 5, a die with high leakage and error (hereinafter referred to as a leak/error die) and You can test by dualizing the normal die.

That is, from the previous test results, information on the die in which leaks and errors frequently occur is collected (S11).

Next, through a plurality of test results, a die in which leaks and errors have occurred more than a predetermined number of times is classified as a leak/error die 320a, and a die in which leaks and errors have occurred less than the predetermined number of times is classified as a normal die 320b. Classify (S12). The information of the leak/error die 320a and the information of the normal die 320b and the test conditions may be stored in the storage module 150 of the test device 100 .

The control module 160 of the test device 100 is based on the information of the leak/error die 320a and the normal die 320b stored in the storage module 150 and the first and second test conditions TM1 and TM2. As a result, a first test condition corresponding to normal test information is applied to the normal die 320b through a corresponding probe card, and a second test condition corresponding to a severe test condition is applied to the leak/error die 320b. It is applied through the probe card (S13). Accordingly, it is possible to designate a die having a high error frequency to perform a test under severe conditions.

In the present embodiment, the binary test was performed by dividing the normal test condition and the severe test condition. However, the present embodiment is not limited thereto, and it goes without saying that the test conditions may be diversified.

According to the present invention, dies are classified on a wafer in consideration of positions according to positions or error occurrence frequencies, and different test conditions are applied to the classified dies to perform a probe test. Accordingly, it is possible to more accurately test a die in an edge region or a region having a high frequency of errors.

Although the present invention has been described in detail with reference to a preferred embodiment, the present invention is not limited to the above embodiment, and various modifications are possible by those skilled in the art within the scope of the technical spirit of the present invention. Do.

100: tester 200: interface
200a: probe card 300: wafer

Claims (8)

distinguishing a center zone and an edge zone of a wafer on which a plurality of dies are formed;
testing center zone dies positioned in a center zone of the wafer among the plurality of dies under a first test condition; and
testing, among the plurality of dies, edge zone dies positioned in an edge zone of the wafer under a second test condition different from the first test condition;
The first test condition and the second test condition include a voltage condition and a timing condition, respectively. ◈Claim 2 was abandoned when paying the registration fee.◈ The method of claim 1,
The second test condition is a condition more severe than the first test condition. ◈Claim 3 was abandoned when paying the registration fee.◈ 3. The method of claim 2,
The voltage condition of the second test condition includes a voltage having a higher voltage level or a lower voltage level than the voltage condition of the first test condition,
and wherein the timing condition of the second test condition includes a timing of a period that is faster or slower than the timing condition of the first test condition. ◈Claim 4 was abandoned when paying the registration fee.◈ The method of claim 1,
The test step is a probe test. collecting location information of a die in which leaks and defects occur more than a reference number of times through a plurality of wafer test processes;
classifying dies corresponding to the position information in the wafer under test as leak and error dies, and classifying the remaining dies except for the leak and error dies as normal dies;
testing the normal dies on the wafer under test under a first test condition; and
testing the leak and fault dies on the wafer under test under a second test condition different from the first test condition;
Wafer test method comprising a. ◈Claim 6 was abandoned when paying the registration fee.◈ 6. The method of claim 5,
The voltage condition of the second test condition includes a voltage having a higher voltage level or a lower voltage level than the voltage condition of the first test condition,
and wherein the timing condition of the second test condition includes a timing of a period that is faster or slower than the timing condition of the first test condition. A probe test apparatus using, as an interface, a probe card that is in contact with each of the plurality of dies on a wafer on which a plurality of dies are formed, and detects electrical characteristics of a semiconductor device formed on each of the plurality of dies, as an interface,
a storage module storing position information of each of the dies in the wafer, a first test condition, and a second test condition different from the first test condition; and
A control module that receives the location information, the first test condition, and the second test condition from the storage module and applies the first test condition or the second test condition for each location of the dies
A test device comprising a. ◈Claim 8 was abandoned when paying the registration fee.◈ 8. The method of claim 7,
The control module applies the first test condition, which is a normal test condition, to dies located in the center zone of the wafer, and a second test condition that is more severe than the normal test condition to dies located in the edge zone of the wafer. A test device configured to apply a test condition.

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