WO2014024178A1

WO2014024178A1 - Method of improving wafer yield

Info

Publication number: WO2014024178A1
Application number: PCT/IL2012/050296
Authority: WO
Inventors: Ronny HADDAD
Original assignee: Dsp Group Ltd.
Priority date: 2012-08-08
Filing date: 2012-08-08
Publication date: 2014-02-13
Also published as: IN2014DN07350A

Abstract

A method of detecting systematic defects in a wafer manufacturing process, including, receiving a batch of wafers each having a unique identifier and each having multiple dies containing an electronic circuit, testing the dies of each wafer to determine if each die is functional or non-functional; wherein the test keeps track of the wafer identifier and position of the die on the wafer, determining for each wafer from the results of said testing, if the wafer is of an acceptable quality or if it is a low quality wafer and removing low quality wafers, summating the number of functional dies for each die position on the wafers that were not removed, comparing the results of the summating; and detecting die positions (320, 330) that deviate in the number of functional dies relative to adjacent die positions.

Description

METHOD OF IMPROVING WAFER YIELD

TECHNICAL FIELD

The present disclosure relates generally to a method of improving wafer yield above a target yield provided by a semiconductor fabrication plant, and more specifically to detecting systematic defect patterns in wafers after wafer sort.

BACKGROUND

Semiconductor fabrication plants (generally referred to as FABs) specialize in the manufacture of semiconductor wafers for circuit designers. A typical wafer may have a diameter of 150, 200, 300 or 450 millimeters and may have anywhere from a few hundred integral functional die pieces (photo dies) to a few thousand (e.g. 500-2500) on each wafer depending on the size of the circuit and the wafer diameter.

The FAB generally provides an estimated yield (functional dies relative to non-functional dies) for a specific die size and silicon process technology based on their past results in wafer manufacturing. The yield calculation is based on a Bose-Einstein yield model assuming that the non-functional die defects are the result of random defects per process layer. The following equation is used to estimate the yield for a specific circuit:

Y=l/(l+AD₀)ⁿ

Where A represents the die size, D₀ represents the normalized defect density and n is a complexity value depending on the complexity of the circuit design relative to the manufacture process (e.g. number of layers). Generally if the FAB is aware of systematic defects in the manufacture process it can improve the quality of the process, reduce the value of Do and increase the yield. A FAB with a higher yield can charge more per wafer, since each wafer provides more functional dies.

Typically a wafer includes a central area from the center up to a specific radius in which the FAB expects to produce functional dies with the expected yield. Beyond the specific radius, for example 2-3mm from the edge is referred to as an exclusion area depending on the process technology. The FAB is not responsible for the quality of the dies situated in the exclusion area. It has however been shown that a higher yield in the central area will generally result in higher yield also in the exclusion area.

SUMMARY

An aspect of an embodiment of the disclosure relates to a method of detecting systematic defects in a wafer manufacturing process by analysis of the results of a circuit probe test that checks each die to determine if it is good or bad (i.e. functional or non-functional) for a batch of wafers. The analysis takes into account the results for each wafer and the position of the dies on the wafer. Low quality wafers (e.g. of low reliability or with low yield) are discarded in the analysis. Using the remaining wafers the number of functional dies for each position is summated and the results are analyzed to detect deviations from the expected result when having only random defects. Optionally, the expected result is that the percentage of functional dies be uniformly distributed over all angles and may slowly deteriorate as a function of the radial distance from the center of the wafer.

In an exemplary embodiment of the disclosure, low quality wafers include:

1. Wafers that fail the manufacturer wafer acceptance test;

2. Wafers with an absolute low yield (e.g. low number of functional dies such as less than 70% or 60% of the dies on the wafer);

3. Wafers with bad clusters, for example a large area of bad dies;

4. Wafers with a relative low yield (outlier wafers), for example a yield that deviates from the yield for most other wafers of the batch.

In an exemplary embodiment of the disclosure, non-functional wafers in the deviation positions are analyzed to trace the source of failure, for example by determining, the wafer numbers having non-functional dies at the deviation position, the type of failure in the non-functional dies, which layer caused the failure, which machines created the damage to the non-functional dies on the damaged wafers. Optionally, the above information can be used to correct the identified systematic failure and improve wafer yield.

There is thus provided according to an exemplary embodiment of the disclosure, a method of detecting systematic defects in a wafer manufacturing process, comprising:

Receiving a batch of wafers each having a unique identifier and each having multiple dies containing an electronic circuit;

Testing the dies of each wafer to determine if each die is functional or nonfunctional; wherein the test keeps track of the wafer identifier and position of the die on the wafer; Determining for each wafer from the results of said testing, if the wafer is of an acceptable quality relative to the rest of the batch or if it is a low quality wafer, and removing the wafer if it is a low quality wafer;

Summating the number of functional dies for each die position on the wafers that were not removed;

Comparing the results of said summating; and

Detecting die positions that deviate in the number of functional dies relative to adjacent die positions. Optionally, the received wafers were tested by a wafer acceptance test performed by the wafer manufacturer. In an exemplary embodiment of the disclosure, the testing is performed with a circuit probe. Alternatively or additionally, the testing is performed on packaged dies. Optionally, the low quality wafers include wafers with a low percentage of functional dies from the number of dies on a wafer, below a threshold value. In an exemplary embodiment of the disclosure, the low quality wafers include wafers with clusters of non-functional dies. Optionally, the low quality wafers include outlier wafers having a number of non-functional wafers that deviates noticeably for the worse from the rest of the wafers of the batch. In an exemplary embodiment of the disclosure, the adjacent die positions have the same radial position from the center of the wafer. Alternatively, the adjacent die positions have the same angular position on the wafer. In an exemplary embodiment of the disclosure, the method includes tracing the source of the deviation and amending the manufacturing process to increase manufacture yield. Optionally, the tracing is performed by categorizing the type of failure for each failed die at the detected die positions. In an exemplary embodiment of the disclosure, the method includes marking each die to allow tracing the wafer identifier and position on the wafer from which the die originated. Optionally, the marking is performed by recording the information in the electrical circuit of the die.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure will be understood and better appreciated from the following detailed description taken in conjunction with the drawings. Identical structures, elements or parts, which appear in more than one figure, are generally labeled with the same or similar number in all the figures in which they appear, wherein:

Fig. 1 is a schematic illustration of a wafer with a central area and an exclusion area, according to an exemplary embodiment of the disclosure;

Fig. 2 is a flow diagram of a method of improving wafer yield, according to an exemplary embodiment of the disclosure;

Fig. 3 is a schematic illustration of a wafer yield per position graph responsive to die sort, according to an exemplary embodiment of the disclosure; and

Fig. 4 is a schematic illustration of wafer yield per radius and wafer yield per angle, according to an exemplary embodiment of the disclosure.

DETAILED DESCRIPTION

Fig. 1 is a schematic illustration of a wafer 100 with a central area 110 and an exclusion area 120, according to an exemplary embodiment of the disclosure. The wafer 100 includes photo dies which are functional (good dies) and faulty dies 140 which are non-functional (bad dies). In an exemplary embodiment of the disclosure, a client orders a plurality of wafers 100 from a wafer manufacturer. The wafer manufacturer provides the wafers in multiple manufacturing batches and guarantees a target yield, for example 95% functional dies on the average from the central area 1 10 of the manufactured wafers 100. In an exemplary embodiment of the disclosure, by testing all the dies of a specific batch while keeping record of their initial position (unique wafer number, position in the wafer - e.g. the X, Y position of each die) it is possible to locate additional systematic defects both in the central area and in the exclusion area. By identifying the cause of the defects and improving the manufacturing process, the wafer manufacturer can increase the actual yield relative to the target yield that was initially guaranteed. Additionally, by improving the yield of the central area 110, the yield of the exclusion area will generally be improved and vice versa.

Typically the wafer manufacturer performs a wafer acceptance test (WAT) on the central area 110 to determine if a wafer 100 is of high enough quality to be provided to the client. The wafer manufacturer implants a test structure in scribe lines at specific locations between some of the dies on the wafer. The wafer manufacturer uses probes to test the test structure to evaluate the quality of the wafer without testing the actual dies. If the test structure is of poor quality the wafer will fail the test and will be discarded by the wafer manufacturer. If the wafer passes the test it can be provided to the client.

Fig. 2 is a flow diagram of a method 200 of improving wafer yield, according to an exemplary embodiment of the disclosure. In an exemplary embodiment of the disclosure, the wafers 100, which pass the wafer acceptance test (WAT) are selected (210) for undergoing a circuit probe test. In the circuit probe test each die is tested (220) using circuit probes to determine if the die is a functional die 130 or a faulty die 140. Optionally, during the circuit probe test the origin (wafer identifier/number) and position (Xj, Y_j as shown in Fig. 1) of the die are recorded, for example electronically in the circuit on each die. Alternatively, each die may be given a unique number to allow it to be tracked back to its origin. 0296

In some embodiments of the disclosure, the dies may be tested after they are packaged, for example by connecting them to a test circuit. Optionally, the package may be marked to track the origin of the die in the package.

In an exemplary embodiment of the disclosure, all wafers 100 of normal quality will be analyzed to determine if it is possible to locate additional systematic defects. To this effect problematic wafers 100 will be removed from the analysis.

In an exemplary embodiment of the disclosure, wafers having a low yield, for example with a percentage of functional dies 130 below a specific threshold value are removed (230) from the process of locating systematic defects, since a random low yield wafer is generally the result of a random failure in the manufacturing process. Optionally wafers with bad clusters of dies, for example a wafer with a damaged group of adjacent dies (e.g. more than a pre-selected number of adjacent dies) will also be removed (230). In an exemplary embodiment of the disclosure, the remaining wafers are analyzed to remove outliers. Outliers occur in wafers in which the number of damaged dies deviates markedly from the other wafers in the sample, for example if most of the wafers have between 10 to 20 faulty dies and a specific wafer has 35 then the deviating wafer can be considered an outlier wafer. Optionally, a Grubb test also commonly referred to as a maximum normed residual test is applied (240) to the results of the test (220) to locate outliers and then exclude (250) them from the analysis of method 200.

In an exemplary embodiment of the disclosure, the remaining dies from the normal wafers, after excluding low quality wafers 100, are analyzed (260) by summating the number of functional dies 130 for each position relative to the total number of wafers analyzed.

Fig. 3 is a schematic illustration of a wafer yield per position graph 300 responsive to the circuit probe die test, according to an exemplary embodiment of the disclosure. The wafer yield graph 300 shows the percentage of functional dies 130 from the total number of dies having that position.

At this stage it is expected that the average yield from all the remaining wafers should be essentially uniform, at least over all positions having the same radial distance from the center of the wafer. Optionally, the yield may deteriorate slightly as a function of the radial distance from the center of the wafer, but should be uniform as a function of the angle. In an exemplary embodiment of the disclosure, graph 300 is reviewed to detect (270) deviations from the expected uniformity between adjacent die positions, for example as illustrated by positions 320. Optionally, positions 320 and 330 express a low yield relative to adjacent die positions. In some embodiments of the disclosure, low yield may also be a function of the angle, for example in position 330 where two positions having the same angle, both have low yield relative to the adjacent die positions. Fig. 4 is a schematic illustration of wafer yield per radius and wafer yield per angle, according to an exemplary embodiment of the disclosure. Optionally, an abnormal deviation from the rest of the positions based on normal wafers provides indication of a systematic problem in the manufacturing process.

In an exemplary embodiment of the disclosure, the wafer manufacturer may further analyze the faulty dies 140 from the determined low yield positions (320, 330) to determine which layer or process caused the die failure. The manufacturer may trace the machines that were involved in their manufacture, for example by categorizing the type of failure for each failed die at the detected low yield positions (320, 330) to determine what type of failure increased at the low yield positions and also using a record of the machines involved in producing each wafer. Optionally, the low yield may indicate the existence of a repetitive defect in a specific machine or process layer. By correcting the defects the manufacturer can reduce occurrence of systematic defects and enhance production yield. In an exemplary embodiment of the disclosure the above method is used to increase yield both in the exclusion area 120 and in the central area 110.

In the short term an increase in production yield may benefit the client who receives more functional dies for the same cost. Additionally, as mentioned above an increase in the yield in the central area 110 generally leads to an increase in yield in the exclusion area 120 and vice versa. The extra dies from the exclusion area 120 may be provided as a bonus for the client. In the long run the manufacturer may increase costs since manufacturers that can guarantee a higher yield per wafer generally charge more per wafer. Optionally, the expected improvement for a manufacturer that guarantees above 90% functional dies may be between 0.1% to 1%, which can be quite beneficial when producing large quantities of an integrated circuit.

It should be appreciated that the above described methods and apparatus may be varied in many ways, including omitting or adding steps, changing the order of steps and the type of devices used. It should be appreciated that different features may be combined in different ways. In particular, not all the features shown above in a particular embodiment are necessary in every embodiment of the disclosure. Further combinations of the above features are also considered to be within the scope of some embodiments of the disclosure. It will also be appreciated by persons skilled in the art that the present disclosure is not limited to what has been particularly shown and described hereinabove.

Claims

CLAIMS I/We claim:

1. A method of detecting systematic defects in a wafer manufacturing process, comprising:

testing the dies of each wafer to determine if each die is functional or nonfunctional; wherein the test keeps track of the wafer identifier and position of the die on the wafer;

determining for each wafer from the results of said testing, if the wafer is of an acceptable quality relative to the rest of the batch or if it is a low quality wafer, and removing the wafer if it is a low quality wafer;

comparing the results of said summating; and

detecting die positions that deviate in the number of functional dies relative to adjacent die positions.

2. A method according to claim 1, wherein said received wafers were tested by a wafer acceptance test performed by the wafer manufacturer.

3. A method according to claim 1, wherein said testing is performed with a circuit probe.

4. A method according to claim 1, wherein said testing is performed on packaged dies.

5. A method according to claim 1, wherein said low quality wafers include wafers with a low percentage of functional dies from the number of dies on a wafer, below a threshold value.

6. A method according to claim 1, wherein said low quality wafers include wafers with clusters of non-functional dies.

7. A method according to claim 1, wherein said low quality wafers include outlier wafers having a number of non-functional wafers that deviates noticeably for the worse from the rest of the wafers of the batch.

8. A method according to claim 1, wherein said adjacent die positions have the same radial position from the center of the wafer.

9. A method according to claim 1, wherein said adjacent die positions have the same angular position on the wafer.

10. A method according to claim 1, further comprising tracing the source of the deviation and amending the manufacturing process to increase manufacture yield.

11. A method according to claim 10, wherein said tracing is performed by categorizing the type of failure for each failed die at the detected die positions.

12. A method according to claim 1, further comprising marking each die to allow tracing the wafer identifier and position on the wafer from which the die originated.

13. A method according to claim 12, wherein said marking is performed by recording the information in the electrical circuit of the die.