CN104134619A - Method for detecting alignment degree between polycrystalline silicon and connecting hole through insufficient etching defect - Google Patents
Method for detecting alignment degree between polycrystalline silicon and connecting hole through insufficient etching defect Download PDFInfo
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- CN104134619A CN104134619A CN201410390797.0A CN201410390797A CN104134619A CN 104134619 A CN104134619 A CN 104134619A CN 201410390797 A CN201410390797 A CN 201410390797A CN 104134619 A CN104134619 A CN 104134619A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
Abstract
A method for detecting the alignment degree between polycrystalline silicon and a connecting hole through the insufficient etching defect comprises the steps that a test silicon wafer module is manufactured, wherein the test silicon wafer module comprises a plurality of test sub-modules with successively increased critical sizes of polycrystalline silicon grids; after the test silicon wafer module is manufactured, the test silicon wafer module is taped out to the step in which evenness of the connecting hole is completed, and then an electron beam defect scanner is used for detecting the insufficient etching defect of the test sub-modules; the alignment degree between the polycrystalline silicon and the connecting hole is judged according to the result of detection, carried out by the electron beam defect scanner, of the insufficient etching defect. According to the method for detecting the alignment degree between the polycrystalline silicon and the connecting hole through the insufficient etching defect, the alignment degree, in the horizontal plane, between the contact hole of the polycrystalline silicon and the connecting hole of a product can be accurately reflected, the variation trend of the alignment degree on the wafer is reflected by detecting test module matrixes at different positions of the whole wafer, thus, methodology is provided for manufacture procedure window optimization and on-line monitoring, and guarantees are provided for on-line manufacturing and yield improvement of semiconductors.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of by the method for the not enough defects detection polysilicon of etching and connecting hole Aligning degree.
Background technology
Along with development and the critical size of integrated circuit technology are scaled, some new materials and new technology all can be introduced in the technique of integrated circuit to meet the requirement of allomeric function, and the precision connecting between different structure is just aobvious very important.When manufacturing process enters into 65 nanometers when following, even if the Aligning degree of contact hole and polysilicon gate has minor deviations all can cause the decline of device overall performance even to lose efficacy.At present, technique control is in this respect mainly by the method for optics, to detect the deviate of two structures alignings, but due to the restriction that is subject to resolution sizes of optics itself, when device size constantly dwindles, this method just can not meet the requirement that technique is accurately controlled.
Summary of the invention
Technical problem to be solved by this invention is for there being above-mentioned defect in prior art, and a kind of method that can pass through the not enough defects detection polysilicon of etching and connecting hole Aligning degree is provided.
In order to realize above-mentioned technical purpose, according to the present invention, provide a kind of by the method for the not enough defects detection polysilicon of etching and connecting hole Aligning degree, it is characterized in that comprising: the test silicon wafer module of manufacturing needles to the shared contact hole of polysilicon gate and substrate first, wherein test silicon wafer module comprises a plurality of test submodules that polysilicon gate critical size increases successively; After manufacturing test silicon chip module, by the flow of test silicon wafer module, to the step that executes connecting hole planarization, applying electronic harness defects scanner carries out the detection of the not enough defect of etching to the test submodule of test silicon wafer module subsequently; According to testing result judgement polysilicon and the connecting hole Aligning degree of the not enough defect of the etching of electron beam Defect Scanning instrument.
Preferably, according to testing result judgement polysilicon and the connecting hole Aligning degree of the not enough defect of the etching of electron beam Defect Scanning instrument, specifically comprise: calculate the minimum polysilicon gate critical size that occurs all test submodules of the not enough defect of etching in test silicon wafer module; Described minimum polysilicon gate critical size is larger, judges that polysilicon and connecting hole Aligning degree are higher; Described minimum polysilicon gate critical size is less, judges that polysilicon and connecting hole Aligning degree are lower.
Preferably, the deviation between judgement polysilicon and connecting hole is 1/2nd of difference between described minimum polysilicon gate critical size and standard polysilicon critical size.
Preferably, described test silicon wafer module at least comprises the second test test submodule group that has the first test submodule group of a plurality of the first test submodules and have a plurality of the second test submodules, in the first test submodule, connecting hole is vertically arranged for the level polysilicon of arranging, in the second test submodule, connecting hole is arranged for the polysilicon level of vertically arranging, and polysilicon gate critical size of first each the first test submodule in test submodule group increases successively, the polysilicon gate critical size of each the second test submodule in the second test submodule group also increases successively.
Preferably, the condition that applying electronic harness defects scanner scans is: landing energy 500～1200eV, electric current 10～100nA, Pixel Dimensions 10～50nm.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily to the present invention, there is more complete understanding and more easily understand its advantage of following and feature, wherein:
Fig. 1 schematically shows the schematic diagram of the test silicon wafer module of the method for passing through according to the preferred embodiment of the invention the not enough defects detection polysilicon of etching and connecting hole Aligning degree.
Fig. 2 schematically shows according to the 6T SRAM topology layout of preferred embodiment of the present invention sampling.
Fig. 3 schematically shows the schematic diagram that the larger connecting hole of polysilicon gate critical size forms the possibility increase of the not enough defect of etching.
It should be noted that, accompanying drawing is used for illustrating the present invention, and unrestricted the present invention.Note, the accompanying drawing that represents structure may not be to draw in proportion.And in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
Inventor advantageously finds, when contact hole and polysilicon gate are when the Aligning degree of some directions exists relatively large deviation, contact area between shared contact hole in static random-access memory SRAM structure will become large, contrary, the contact area of itself and silicon substrate will diminish, thereby cause its critical size less than normal and easily produce the not enough defect of etching.That is to say, for the not enough defect condition of etching of the shared contact hole under different deviates, side-play amount is larger, and etching is not enough, and defect is more serious.
As shown in Figure 3, polysilicon gate critical size CD1, CD2, CD3 ... increase gradually, can find out that polysilicon gate critical size is larger, the critical size of sharing contact hole and silicon substrate will be less, it produces the not enough defect of etching, and (etching is not enough, and defect means, the shared contact hole of polysilicon gate and substrate is connected to substrate no longer validly) possibility larger, its sensitivity to polysilicon and connecting hole deviation is higher.
According to this principle, design test structure of the present invention, monitors the Aligning degree between polysilicon and connecting hole.
By the method for the not enough defects detection polysilicon of etching and connecting hole Aligning degree, can take following step according to the preferred embodiment of the invention:
First, the test silicon wafer module of manufacturing needles to the shared contact hole of polysilicon gate and substrate, wherein test silicon wafer module comprises a plurality of test submodules that polysilicon gate critical size increases successively.And preferably, in order to test on both direction, described test silicon wafer module at least comprises the second test test submodule group that has the first test submodule group of a plurality of the first test submodules and have a plurality of the second test submodules, in the first test submodule, connecting hole is vertically arranged for the level polysilicon of arranging, in the second test submodule, connecting hole is arranged for the polysilicon level of vertically arranging, and polysilicon gate critical size of first each the first test submodule in test submodule group increases successively, the polysilicon gate critical size of each the second test submodule in the second test submodule group also increases successively.
For example, in specific embodiment, can be according to design test silicon chip module as shown in Figure 1, and for example test silicon wafer module, according to 6TSRAM topology layout (as shown in Figure 2), is chosen certain area (such as 2mmX2mm) as a test silicon wafer block size.Such as the product that will detect is 55nm device.Whole test silicon wafer module is identified as 21.In test submodule group 31～3n and test submodule group 41～4n, connecting hole 100 is arranged for level, and polysilicon gate 200 is vertically arranged.Accordingly, in test submodule group 51～5n and test submodule group 61～6n, connecting hole 100 is for vertically arranging, and polysilicon gate 200 is arranged for level, as shown in Figure 2.
Simultaneously, test submodule 31,41,51, in 61, the polysilicon gate critical size of the critical size of polysilicon gate and monitored product matches, test submodule 32,42,52, in 62, the critical size of polysilicon gate is gone up one group increases by 10%, and one group increases by 20% compared with first group thereafter, the like.
After manufacturing test silicon chip module, by the flow of test silicon wafer module, to the step that executes the planarization of (tungsten) connecting hole, applying electronic harness defects scanner (e-beam) carries out the detection (known etching is not enough, and defect can be detected by electron beam Defect Scanning instrument) of the not enough defect of etching to the test submodule of test silicon wafer module subsequently; Wherein, for example can apply positive potential pattern detects.
Preferably, the condition that applying electronic harness defects scanner scans is: landing energy 500～1200eV, electric current 10～100nA, Pixel Dimensions 10～50nm.
Finally, according to testing result judgement polysilicon and the connecting hole Aligning degree of the not enough defect of the etching of electron beam Defect Scanning instrument.That is, according to the testing result of the not enough defect of the etching of electron beam Defect Scanning instrument, the deviation situation between assessment polysilicon and connecting hole.
According to testing result judgement polysilicon and the connecting hole Aligning degree of the not enough defect of the etching of electron beam Defect Scanning instrument, specifically can comprise: (test submodule 33～3n and 43～4n all occur that serious etching is not enough to calculate the minimum polysilicon gate critical size that occurs all test submodules of the not enough defect of etching in test silicon wafer module, minimum polysilicon gate critical size is the polysilicon gate critical size of test submodule 33 and 43), described minimum polysilicon gate critical size is larger, judges that polysilicon and connecting hole Aligning degree are higher; Described minimum polysilicon gate critical size is less, judges that polysilicon and connecting hole Aligning degree are lower.
Particularly, can judge that deviation between polysilicon and connecting hole is 1/2nd of difference between described minimum polysilicon gate critical size and standard polysilicon critical size.
Specifically, confirm to produce when deviate is zero between connecting hole and polysilicon the polysilicon size of the not enough defect of Share interlinkage hole etching, if deviation is horizontal direction, and the polysilicon gate critical size that the critical dimension that produces the not enough defect of etching is monitored product 150% (critical size of setting surpasses critical dimension, there will be the not enough defect of etching), be test silicon wafer module 35～3n, 45～4n will can produce the not enough defect of serious etching.
Method by the not enough defects detection polysilicon of etching and connecting hole Aligning degree of the present invention can accurately reflect that product contact hole and polysilicon gate are in the alignment case of plane, and by detecting the test module matrix of diverse location on whole wafer, the variation tendency of Aligning degree on reflection wafer, thereby be process window optimization and on-line monitoring supplying method opinion, for semiconductor is online, manufactures with Yield lmproved and provide safeguard.And, in test silicon wafer module, exist two kinds of different connecting holes and polysilicon to arrange combination to monitor the Aligning degree of different directions.
For example, can on 55 nanometer products, apply principle of the present invention and set up test structure, by detecting the not enough defect condition of connecting hole etching, monitor actual connecting hole and the Aligning degree side-play amount between polysilicon.
In addition, it should be noted that, unless stated otherwise or point out, otherwise the descriptions such as the term in specification " first ", " second ", " the 3rd " are only for distinguishing each assembly, element, step of specification etc., rather than for representing logical relation between each assembly, element, step or ordinal relation etc.
Be understandable that, although the present invention with preferred embodiment disclosure as above, yet above-described embodiment is not in order to limit the present invention.For any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (5)
1. by a method for the not enough defects detection polysilicon of etching and connecting hole Aligning degree, it is characterized in that comprising:
First the test silicon wafer module of manufacturing needles to the shared contact hole of polysilicon gate and substrate, wherein test silicon wafer module comprises a plurality of test submodules that polysilicon gate critical size increases successively;
After manufacturing test silicon chip module, by the flow of test silicon wafer module, to the step that executes connecting hole planarization, applying electronic harness defects scanner carries out the detection of the not enough defect of etching to the test submodule of test silicon wafer module subsequently;
According to testing result judgement polysilicon and the connecting hole Aligning degree of the not enough defect of the etching of electron beam Defect Scanning instrument.
2. according to claim 1 by the method for the not enough defects detection polysilicon of etching and connecting hole Aligning degree, it is characterized in that, according to testing result judgement polysilicon and the connecting hole Aligning degree of the not enough defect of the etching of electron beam Defect Scanning instrument, specifically comprise: calculate the minimum polysilicon gate critical size that occurs all test submodules of the not enough defect of etching in test silicon wafer module; Described minimum polysilicon gate critical size is larger, judges that polysilicon and connecting hole Aligning degree are higher; Described minimum polysilicon gate critical size is less, judges that polysilicon and connecting hole Aligning degree are lower.
3. according to claim 1 and 2 by the method for the not enough defects detection polysilicon of etching and connecting hole Aligning degree, it is characterized in that, the deviation between judgement polysilicon and connecting hole is 1/2nd of difference between described minimum polysilicon gate critical size and standard polysilicon critical size.
4. according to claim 1 and 2 by the method for the not enough defects detection polysilicon of etching and connecting hole Aligning degree, it is characterized in that, described test silicon wafer module at least comprises the second test test submodule group that has the first test submodule group of a plurality of the first test submodules and have a plurality of the second test submodules, in the first test submodule, connecting hole is vertically arranged for the level polysilicon of arranging, in the second test submodule, connecting hole is arranged for the polysilicon level of vertically arranging, and polysilicon gate critical size of first each the first test submodule in test submodule group increases successively, the polysilicon gate critical size of each the second test submodule in the second test submodule group also increases successively.
5. according to claim 1 and 2 by the method for the not enough defects detection polysilicon of etching and connecting hole Aligning degree, it is characterized in that, the condition that applying electronic harness defects scanner scans is: landing energy 500～1200eV, electric current 10～100nA, Pixel Dimensions 10～50nm.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410390797.0A CN104134619B (en) | 2014-08-08 | 2014-08-08 | Method by the not enough defects detection polysilicon of etching and connecting hole Aligning degree |
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| CN201410390797.0A CN104134619B (en) | 2014-08-08 | 2014-08-08 | Method by the not enough defects detection polysilicon of etching and connecting hole Aligning degree |
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| CN104134619B CN104134619B (en) | 2017-03-08 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106206354A (en) * | 2016-08-30 | 2016-12-07 | 上海华力微电子有限公司 | The method of detection first floor metal etch deficiency defect |
| CN109712904A (en) * | 2018-12-27 | 2019-05-03 | 上海华力集成电路制造有限公司 | Contact hole in semiconductor device open circuit detection structure and open circuit detection method |
| CN110854092A (en) * | 2019-11-13 | 2020-02-28 | 上海华力集成电路制造有限公司 | Shared contact hole and etching defect detection method thereof |
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2014
- 2014-08-08 CN CN201410390797.0A patent/CN104134619B/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106206354A (en) * | 2016-08-30 | 2016-12-07 | 上海华力微电子有限公司 | The method of detection first floor metal etch deficiency defect |
| CN109712904A (en) * | 2018-12-27 | 2019-05-03 | 上海华力集成电路制造有限公司 | Contact hole in semiconductor device open circuit detection structure and open circuit detection method |
| CN110854092A (en) * | 2019-11-13 | 2020-02-28 | 上海华力集成电路制造有限公司 | Shared contact hole and etching defect detection method thereof |
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| CN104134619B (en) | 2017-03-08 |
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