CN102044462A - Method for testing wafer - Google Patents
Method for testing wafer Download PDFInfo
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- CN102044462A CN102044462A CN2009102054359A CN200910205435A CN102044462A CN 102044462 A CN102044462 A CN 102044462A CN 2009102054359 A CN2009102054359 A CN 2009102054359A CN 200910205435 A CN200910205435 A CN 200910205435A CN 102044462 A CN102044462 A CN 102044462A
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Abstract
The invention discloses a method for testing a wafer. The method comprises the following steps of: providing the wafer, wherein the wafer is provided with a plurality of chips which are divided into a plurality of types; providing a plurality of testing programs which are in one-to-one correspondence with the chip types respectively; testing the plurality of the chips one by one by using the plurality of the testing programs according to a position order; in the testing process, if a certain chip passes through the test of a certain testing program, classifying the chip as a chip type corresponding to the testing program, and testing the chip of the next position; and if a certain chip cannot pass through the test of all the testing programs, determining that the chip is disabled, and testing the chip of the next position until all the chips on the wafer are tested. The method reduces the testing time, improves the testing efficiency of the wafer, and saves the testing cost.
Description
Technical field
The present invention relates to the semiconductor test field, relate in particular to crystal round test approach.
Background technology
The manufacture process of semiconductor subassembly can be divided into wafer manufacturing, wafer sort, encapsulation and last test haply.The wafer manufacturing is the process of making electric circuitry packages on Silicon Wafer, after completing, form the chip (die) of arrayed on the wafer, carry out the wafer sort step then so that chip is made testing electrical property, underproof chip is eliminated, and wafer is cut into several chip; At last, encapsulation is that qualified chip is packed and routing, forms the chip after encapsulating, and needs to carry out testing electrical property at last to guarantee the quality of integrated circuit again.
About the wafer sort technology, the different phase according to wafer is made is divided into two kinds of chip testing and finished product tests.The former still is in the chip good and the bad test that wafer carried out during the fabrication stage with probe at product.The demand of volume chip littler, with better function is just promoted the development of IC industry, also promoting the development of integrated circuit (IC) design and test simultaneously.Reduce testing cost and become the primary goal of wafer sort development, the ultimate challenge that following integrated circuit testing equipment manufacturers face is how to reduce testing cost.
Improving test speed and testing intellectuality is the necessary ways that reduce the cost.The test principle that generally adopts as shown in Figure 1 at present, owing to comprise some unit (large square indicates among the figure) on every wafer 10, has multiclass project chip (9 classes shown in the figure) in described each unit, and each intermediate item chip all has definite test program corresponding with it, and wherein each test program uses corresponding test vector.Therefore, prior art is when test wafer, test the first kind project chip 1 of the same type in each unit earlier successively with first test program opsition dependent order, promptly the step pitch that wafer moves in the test process is for moving to the first kind project chip 1 of next unit in regular turn from the first kind project chip 1 of a unit; If, judge that then this chip is qualified and carry out the test of next chip of the same type by the test of first test program; If can not then judge this chip failure and carry out the test of next chip of the same type by the test of first test program.After the test of finishing all first kind project chips 1 on the wafer, move back sheet, correcting probe is tested the second intermediate item chip 2 in each unit with second test program successively by said sequence; If, judge that then this chip is qualified and carry out the test of next chip of the same type by the test of second test program; If can not then judge this chip failure and carry out the test of next chip of the same type by the test of second test program.... after the test of finishing all the 8th intermediate item chips 8 on the wafer, move back sheet, behind the correcting probe, test the 9th intermediate item chip 9 in each unit successively with the 9th test program; If, judge that then this chip is qualified and carry out the test of next chip of the same type by the test of the 9th test program; If can not then judge this chip failure and carry out the test of next chip of the same type by the test of the 9th test program.
The test program that Fig. 2 tests an intermediate item chip in the unit in the wafer for prior art, execution in step S11 begins test; Execution in step S12 sets test program, and described each test program uses corresponding test vector; Execution in step S13 judges whether by test; Execution in step S14 is if by test, judge that then this chip is qualified, and successively the chip of the same type in the next unit is tested; Execution in step S15 is if not by test, then judge this chip failure, and successively the chip of the same type in the next unit is tested.
The method of testing of existing wafer, because the chip that is same intermediate item is tested together, the step pitch that wafer moves in the test process is big, as shown in Figure 1 first kind project chip 1 is tested mobile route, the problem that causes wafer to survey or to damage.In addition, the chip of same intermediate item adopts a test program, and has multiclass project chip on the wafer, and the program that therefore needs different editions is corresponding with it, and program version is many, and efficient is low; And after testing a similar project chip, carry out the test of other intermediate item chip again through moving back sheet and correcting probe, testing efficiency is low.
Summary of the invention
The problem that the present invention solves provides a kind of crystal round test approach, prevents that testing efficiency is low, and wafer can not be surveyed or damage.
For addressing the above problem, the invention provides a kind of crystal round test approach, comprising: a wafer is provided, has several chip on the described wafer, described plurality of chips is divided into several types; Provide several respectively with chip type test program one to one; Described some test program opsition dependent orders are tested one by one to plurality of chips; In test process, if a certain chip classifies as the chip type of this test program correspondence with this chip, and carries out the next position chip testing by a certain test program test; If a certain chip can not then be judged this chip failure, and carry out the next position chip testing until testing all chips on the wafer by the test of all test programs.
Optionally, the quantity of described chip type is smaller or equal to the quantity of chip.
Optionally, described opsition dependent order successively to each chip test be by first chip to last chip by laterally successively each chip is tested or by last chip to first chip by laterally successively each chip is tested by first chip to last chip by vertically successively each chip is tested or by last chip to first chip by vertically successively each chip being tested.
Optionally, comprise at least one unit on the described wafer, have multiclass project chip array in each unit.
Compared with prior art, the present invention has the following advantages: described some test program opsition dependent orders are tested one by one to plurality of chips; In test process, if a certain chip classifies as the chip type of this test program correspondence with this chip, and carries out the next position chip testing by a certain test program test; If a certain chip can not then be judged this chip failure, and carry out the next position chip testing until testing all chips on the wafer by the test of all test programs.In the test process, be that opsition dependent order is tested each chip successively, the motion mode of wafer is that mobile step pitch is contracted to minimum in horizontal and vertical mobile basic chips length, has avoided the generation of the problem that wafer can not survey or damage.In addition,, reduced the testing time, improved the testing efficiency of wafer, saved testing expense owing to after finishing the test of full wafer wafer, just move back sheet.
Description of drawings
Fig. 1 is the principle schematic diagram of existing wafer sort;
Fig. 2 is the flow chart of chip testing on the existing wafer;
Fig. 3 is the first embodiment principle schematic diagram of wafer sort of the present invention;
Fig. 4 is the second embodiment principle schematic diagram of wafer sort of the present invention;
Fig. 5 is the 3rd an embodiment principle schematic diagram of wafer sort of the present invention;
Fig. 6 is the 4th an embodiment principle schematic diagram of wafer sort of the present invention;
Fig. 7 is the flow chart of chip testing on the wafer of the present invention.
Embodiment
Existing wafer sort technology, owing to the chip that is same intermediate item is tested together, the step pitch that wafer moves in the test process is big, the problem that causes wafer to survey or to damage.In addition, the chip of same intermediate item adopts a test program, and has multiclass project chip on the wafer, and the program that therefore needs different editions is corresponding with it, and program version is many, and efficient is low; And after testing a similar project chip, carry out the test of other intermediate item chip again through moving back sheet and correcting probe, testing efficiency is low.
Therefore, the invention provides a kind of crystal round test approach, comprising: a wafer is provided, has several chip on the described wafer, described plurality of chips is divided into several types; Provide several respectively with chip type test program one to one; Described some test program opsition dependent orders are tested one by one to plurality of chips; In test process, if a certain chip classifies as the chip type of this test program correspondence with this chip, and carries out the next position chip testing by a certain test program test; If a certain chip can not then be judged this chip failure, and carry out the next position chip testing until testing all chips on the wafer by the test of all test programs.
In the test process, be that opsition dependent order is tested each chip successively, the motion mode of wafer is that mobile step pitch is contracted to minimum in horizontal and vertical mobile basic chips length, has avoided the generation of the problem that wafer can not survey or damage.In addition,, reduced the testing time, improved the testing efficiency of wafer, saved testing expense owing to after finishing the test of full wafer wafer, just move back sheet.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Fig. 3 is the first embodiment principle schematic diagram of wafer sort of the present invention.As shown in Figure 3, comprise a plurality of unit (large square indicates among the figure) on every wafer 10, have multiclass project chip (9 classes shown in the figure) in each unit, each intermediate item chip all has definite test program corresponding with it, and each test program uses corresponding test vector.
Present embodiment chip testing principle is: by first chip A of chip top
1Last chip A to the chip below
MSuccessively each chip is tested from horizontal direction opsition dependent order.
Specifically test in conjunction with Fig. 7, execution in step S21 begins test;
Execution in step S24 adopts first test program to test; Promptly adopt and the first chip A of corresponding first test program of first kind project chip the wafer top
1Test.
Execution in step S25 judges the first chip A
1Whether test by first test program?
Execution in step S42 is if by the test of first test program, illustrate the first chip A
1Type is corresponding with first test program, i.e. the first chip A
1Be first kind project chip.
Execution in step S26 is if can not then adopt second test program to test by the test of first test program; Second test program that promptly adopts the second intermediate item chip correspondence is to the first chip A
1Test.
Execution in step S27 judges the first chip A
1Whether test by second test program?
Execution in step S42 is if by the test of second test program, illustrate the first chip A
1Type is corresponding with second test program, i.e. the first chip A
1It is the second intermediate item chip.
Execution in step S28 is if can not then adopt the 3rd test program to test by the test of second test program; The 3rd test program that promptly adopts the 3rd intermediate item chip correspondence is to the first chip A
1Test.
Execution in step S29 judges the first chip A
1Whether test by the 3rd test program?
Execution in step S42 is if by the test of the 3rd test program, illustrate the first chip A
1Type is corresponding with the 3rd test program, i.e. the first chip A
1It is the 3rd intermediate item chip.
Execution in step S30 is if can not then adopt the 4th test program to test by the test of the 3rd test program; The 4th test program that promptly adopts the 4th intermediate item chip correspondence is to the first chip A
1Test.
Execution in step S31 judges the first chip A
1Whether test by the 4th test program?
Execution in step S42 is if by the test of the 4th test program, illustrate the first chip A
1Type is corresponding with the 4th test program, i.e. the first chip A
1It is the 4th intermediate item chip.
Execution in step S32 is if can not then adopt the 5th test program to test by the test of the 4th test program; The 5th test program that promptly adopts the 5th intermediate item chip correspondence is to the first chip A
1Test.
Execution in step S33 judges the first chip A
1Whether test by the 5th test program?
Execution in step S42 is if by the test of the 5th test program, illustrate the first chip A
1Type is corresponding with the 5th test program, i.e. the first chip A
1It is the 5th intermediate item chip.
Execution in step S34 is if can not then adopt the 6th test program to test by the test of the 5th test program; The 6th test program that promptly adopts the 6th intermediate item chip correspondence is to the first chip A
1Test.
Execution in step S35 judges the first chip A
1Whether test by the 6th test program?
Execution in step S42 is if by the test of the 6th test program, illustrate the first chip A
1Type is corresponding with the 6th test program, i.e. the first chip A
1It is the 6th intermediate item chip.
Execution in step S36 is if can not then adopt the 7th test program to test by the test of the 6th test program; The 7th test program that promptly adopts the 7th intermediate item chip correspondence is to the first chip A
1Test.
Execution in step S37 judges the first chip A
1Whether test by the 7th test program?
Execution in step S42 is if by the test of the 7th test program, illustrate the first chip A
1Type is corresponding with the 7th test program, i.e. the first chip A
1It is the 7th intermediate item chip.
Execution in step S38 is if can not then adopt the 8th test program to test by the test of the 7th test program; The 8th test program that promptly adopts the 8th intermediate item chip correspondence is to the first chip A
1Test.
Execution in step S39 judges the first chip A
1Whether test by the 8th test program?
Execution in step S42 is if by the test of the 8th test program, illustrate the first chip A
1Type is corresponding with the 8th test program, i.e. the first chip A
1It is the 8th intermediate item chip.
……
By that analogy, execution in step S40 is if can not then adopt the N test program to test by the test of N-1 test program; The N test program that promptly adopts n intermediate item chip correspondence is to the first chip A
1Test, described N and n are natural number, and both equate.
In the present embodiment, 9 intermediate item chips are arranged on the described wafer, therefore N is 9 in this embodiment, and n is 9.
Execution in step S41 judges the first chip A
1Whether test by the N test program?
If execution in step S44 by N test program test then finish test, illustrates the first chip A
1Type is corresponding with the N test program, i.e. the first chip A
1It is n intermediate item chip.
Execution in step S43 is if can not then judge the first chip A by the test of N test program
1Lost efficacy.
In the present embodiment,, therefore 9 kinds of corresponding test programs are arranged,, then illustrate what this chip really lost efficacy if all lost efficacy after each test program test owing on the wafer 9 intermediate item chips are arranged.
Adopt above-mentioned flow process, successively to the second chip A
2, the 3rd chip A
3... M chip A
MTest.Described M chip A
MBe last sheet chip below the wafer that needs on the wafer to test.
In conjunction with Fig. 7 to last sheet chip M chip A
MTest, execution in step S21 begins test;
Execution in step S24 adopts first test program to test; Promptly adopt and the M chip A of corresponding first test program of first kind project chip the wafer top
MTest.
Execution in step S25 judges M chip A
MWhether test by first test program?
Execution in step S42 is if by the test of first test program, illustrate M chip A
MType is corresponding with first test program, i.e. M chip A
MBe first kind project chip.
Execution in step S26 is if can not then adopt second test program to test by the test of first test program; Second test program that promptly adopts the second intermediate item chip correspondence is to M chip A
MTest.
Execution in step S27 judges M chip A
MWhether test by second test program?
Execution in step S42 is if by the test of second test program, illustrate M chip A
MType is corresponding with second test program, i.e. M chip A
MIt is the second intermediate item chip.
Execution in step S28 is if can not then adopt the 3rd test program to test by the test of second test program; The 3rd test program that promptly adopts the 3rd intermediate item chip correspondence is to M chip A
MTest.
Execution in step S29 judges M chip A
MWhether test by the 3rd test program?
Execution in step S42 is if by the test of the 3rd test program, illustrate M chip A
MType is corresponding with the 3rd test program, i.e. M chip A
MIt is the 3rd intermediate item chip.
Execution in step S30 is if can not then adopt the 4th test program to test by the test of the 3rd test program; The 4th test program that promptly adopts the 4th intermediate item chip correspondence is to M chip A
MTest.
Execution in step S31 judges M chip A
MWhether test by the 4th test program?
Execution in step S42 is if by the test of the 4th test program, illustrate M chip A
MType is corresponding with the 4th test program, i.e. M chip A
MIt is the 4th intermediate item chip.
Execution in step S32 is if can not then adopt the 5th test program to test by the test of the 4th test program; The 5th test program that promptly adopts the 5th intermediate item chip correspondence is to M chip A
MTest.
Execution in step S33 judges M chip A
MWhether test by the 5th test program?
Execution in step S42 is if by the test of the 5th test program, illustrate M chip A
MType is corresponding with the 5th test program, i.e. M chip A
MIt is the 5th intermediate item chip.
Execution in step S34 is if can not then adopt the 6th test program to test by the test of the 5th test program; The 6th test program that promptly adopts the 6th intermediate item chip correspondence is to M chip A
MTest.
Execution in step S35 judges M chip A
MWhether test by the 6th test program?
Execution in step S42 is if by the test of the 6th test program, illustrate M chip A
MType is corresponding with the 6th test program, i.e. M chip A
MIt is the 6th intermediate item chip.
Execution in step S36 is if can not then adopt the 7th test program to test by the test of the 6th test program; The 7th test program that promptly adopts the 7th intermediate item chip correspondence is to M chip A
MTest.
Execution in step S37 judges M chip A
MWhether test by the 7th test program?
Execution in step S42 is if by the test of the 7th test program, illustrate M chip A
MType is corresponding with the 7th test program, i.e. M chip A
MIt is the 7th intermediate item chip.
Execution in step S38 is if can not then adopt the 8th test program to test by the test of the 7th test program; The 8th test program that promptly adopts the 8th intermediate item chip correspondence is to M chip A
MTest.
Execution in step S39 judges M chip A
MWhether test by the 8th test program?
Execution in step S42 is if by the test of the 8th test program, illustrate M chip A
MType is corresponding with the 8th test program, i.e. M chip A
MIt is the 8th intermediate item chip.
……
By that analogy, execution in step S40 is if can not then adopt the N test program to test by the test of N-1 test program; The N test program that promptly adopts n intermediate item chip correspondence is to M chip A
MTest, described N and n are natural number, and both equate.
Execution in step S41 judges M chip A
MWhether test by the N test program?
If execution in step S44 by N test program test then finish test, illustrates M chip A
MType is corresponding with the N test program, i.e. M chip A
MIt is n intermediate item chip.
Execution in step S43 is if can not then judge M chip A by the test of N test program
MLost efficacy.
Described N is the class number of chip.
Fig. 4 is the second embodiment principle schematic diagram of wafer sort of the present invention.As shown in Figure 4, comprise a plurality of unit (large square indicates among the figure) on every wafer 10, have multiclass project chip (9 classes shown in the figure) in each unit, each intermediate item chip all has definite test program corresponding with it, and each test program uses corresponding test vector.
Present embodiment chip testing principle is: by last chip M chip A of chip below
MFirst chip A to the chip top
1Successively each chip is tested from horizontal direction opsition dependent order.Concrete method of testing has a detailed description in first embodiment, does not repeat them here.
Fig. 5 is the 3rd an embodiment principle schematic diagram of wafer sort of the present invention.As shown in Figure 5, comprise a plurality of unit (large square indicates among the figure) on every wafer 10, have multiclass project chip (9 classes shown in the figure) in each unit, each intermediate item chip all has definite test program corresponding with it, and each test program uses corresponding test vector.
Present embodiment chip testing principle is: by first chip A at place, chip cutting limit
13Last chip A to chip cutting limit relative edge place
66Successively each chip is tested from longitudinal direction opsition dependent order.Concrete method of testing has a detailed description in first embodiment, does not repeat them here.
Fig. 6 is the 4th an embodiment principle schematic diagram of wafer sort of the present invention.As shown in Figure 6, comprise a plurality of unit (large square indicates among the figure) on every wafer 10, have multiclass project chip (9 classes shown in the figure) in each unit, each intermediate item chip all has definite test program corresponding with it, and each test program uses corresponding test vector.
Present embodiment chip testing principle is: by first chip A at chip cutting limit relative edge place
66Last chip A to place, chip cutting limit
13Successively each chip is tested from longitudinal direction opsition dependent order.Concrete method of testing has a detailed description in first embodiment, does not repeat them here.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and revise, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (4)
1. a crystal round test approach is characterized in that, comprising:
One wafer is provided, has several chip on the described wafer, described plurality of chips is divided into several types;
Provide several respectively with chip type test program one to one;
Described some test program opsition dependent orders are tested one by one to plurality of chips;
In test process, if a certain chip classifies as the chip type of this test program correspondence with this chip, and carries out the next position chip testing by a certain test program test;
If a certain chip can not then be judged this chip failure, and carry out the next position chip testing until testing all chips on the wafer by the test of all test programs.
2. according to the described crystal round test approach of claim 1, it is characterized in that the quantity of described chip type is smaller or equal to the quantity of chip.
3. according to the described crystal round test approach of claim 1, it is characterized in that, described opsition dependent order successively to each chip test be by first chip to last chip by laterally successively each chip is tested or by last chip to first chip by laterally successively each chip is tested by first chip to last chip by vertically successively each chip is tested or by last chip to first chip by vertically successively each chip being tested.
4. according to the described crystal round test approach of claim 1, it is characterized in that, comprise at least one unit on the described wafer, have multiclass project chip array in each unit.
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