CN113030701A - Method for measuring power bearing capacity of radio frequency device - Google Patents
Method for measuring power bearing capacity of radio frequency device Download PDFInfo
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- CN113030701A CN113030701A CN202110258196.4A CN202110258196A CN113030701A CN 113030701 A CN113030701 A CN 113030701A CN 202110258196 A CN202110258196 A CN 202110258196A CN 113030701 A CN113030701 A CN 113030701A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2822—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere of microwave or radiofrequency circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
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Abstract
The invention provides a method for measuring power bearing capacity of a radio frequency device, which comprises the following steps: providing a multi-project wafer, wherein the multi-project wafer comprises at least two types of chips to be tested; establishing a test file, wherein the test file comprises test conditions and test methods of at least two types of chips to be tested; and calling the test conditions and the test method of the type of the current chip to be tested from the test file, measuring the power bearing capacity of the current chip to be tested, and simultaneously detecting the type of the next chip to be tested so as to measure the power bearing capacity of all chips to be tested. The file established by the invention does not comprise the position coordinates of the chips to be tested which are distinguished and sorted according to different types, thereby reducing the preliminary test preparation time and shortening the test preparation time.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit testing, in particular to a method for measuring power bearing capacity of a radio frequency device.
Background
With the development of semiconductor technology, SOI technology has been widely applied to radio frequency, and especially, radio frequency switches occupy a certain market share and have the advantage of integration with other modules, and further growth is expected. During the design development phase of the SOI structure, MPW (Multi Project Wafer) is required to verify the power handling capability of the rf switch (typically by testing the power carrying capability of the rf switch). The MPW includes a plurality of independent products (chips), and aims to improve design efficiency and reduce manufacturing cost.
In order to verify the nonlinear characteristics of the rf switch, it is necessary to verify the power handling capability of the series branch, the parallel branch, and the ESD (electrostatic discharge) branch of the rf device. Because different branch structures need to be measured by different test conditions and test methods, each branch needs to be measured by multiple measurements in the prior art, that is, the power processing capability of the serial branch, the power processing capability of the parallel branch and the power processing capability of the ESD branch are measured by multiple (e.g., three) tests on the MPW, which results in long test time, low test efficiency and prolonged design and development time.
In addition, since the distribution of multiple designed chips contained in the same branch (e.g., serial branch) on the multi-project wafer is irregular, it may be gathered in the same area, or may be mixed with other branches (e.g., parallel branch and ESD branch) into one piece, so that before testing, different test files (e.g., test file of serial branch, test file of parallel branch, test file of ESD branch) need to be created for different branch structures, and the files include the position coordinates, test conditions, test methods, and the like of each chip of the same branch. Because of the large number of chips on a multi-project wafer, the process of creating a file is a complex process requiring significant effort and time to prepare for testing.
Disclosure of Invention
The invention provides a method for measuring the power bearing capacity of a radio frequency device, which can improve the test efficiency and shorten the test preparation time.
In order to solve the above technical problem, the present invention provides a method for measuring power carrying capacity of a radio frequency device, comprising the following steps:
step S1: providing a multi-project wafer, wherein the multi-project wafer comprises at least two types of chips to be tested;
step S2: establishing a test file, wherein the test file comprises test conditions and test methods of at least two types of chips to be tested; and
step S3: and calling the test conditions and the test method of the type of the current chip to be tested from the test file, measuring the current power bearing capacity of the chip to be tested, and simultaneously detecting the type of the next chip to be tested so as to measure the power bearing capacity of all chips to be tested.
Optionally, step S3 includes:
confirming the type of a first chip to be tested, calling a test condition and a test method of the type of the first chip to be tested from the test file, measuring the power bearing capacity of the first chip to be tested, and detecting the type of a second chip to be tested; and
and starting from the second chip to be tested, taking each chip to be tested as the current chip to be tested, calling the test conditions and the test method of the type of the current chip to be tested from the test file, measuring the power bearing capacity of the current chip to be tested, and simultaneously detecting the type of the next chip to be tested so as to measure the power bearing capacity of all the chips to be tested.
Further, in step S3, each of the chips to be tested on the multi-project wafer is tested in sequence.
Further, testing each chip to be tested on the multi-item wafer according to the sequence of each row from left to right, the sequence of each row from right to left, the sequence of each column from top to bottom, the sequence of each column from bottom to top, or the serpentine sequence.
Further, measuring the current power bearing capacity of the chip to be tested by using a first group of probes; and simultaneously, detecting the type of the next chip to be detected by using a second group of probes.
And further, testing each chip to be tested on the multi-project wafer according to the sequence of each row from left to right.
Further, measuring the power bearing capacity of the current chip to be tested by using a plurality of probes special for the radio frequency device; and simultaneously, detecting the electrical characteristics of the next chip to be tested by using a plurality of common direct current probes to determine the type of the chip.
Optionally, the multi-project wafer includes a plurality of chips to be tested, and each chip to be tested includes a serial branch, a parallel branch and an ESD branch.
Further, the multi-project wafer includes three types of chips to be tested, which are chips to be tested having different designs for a serial branch, chips to be tested having different designs for a parallel branch, and chips to be tested having different designs for an ESD branch.
Further, each type has a plurality of chips to be tested.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a method for measuring power bearing capacity of a radio frequency device, which comprises the following steps: step S1: providing a multi-project wafer, wherein the multi-project wafer comprises at least two types of chips to be tested; step S2: establishing a test file, wherein the test file comprises test conditions and test methods of at least two types of chips to be tested; and step S3: and calling the test conditions and the test method of the type of the current chip to be tested from the test file, measuring the current power bearing capacity of the chip to be tested, and simultaneously detecting the type of the next chip to be tested so as to measure the power bearing capacity of all chips to be tested. The invention establishes a test condition and a test method comprising at least two types of chips to be tested, the file comprises the test condition and the test method of the at least two types of chips to be tested, but the file does not comprise the steps of distinguishing and sorting the position coordinates of the chips to be tested aiming at different types, thereby greatly reducing the preliminary test preparation time, shortening the test preparation time, completing the test of the chips to be tested of different types through one test, shortening the test time, shortening the design development time and quickening the appearance of new products.
Further, testing each chip to be tested on the multi-project wafer according to the sequence of each row from left to right; the power bearing capacity of the current chip to be tested is measured by using a plurality of special probes for the radio frequency device, and meanwhile, the type (right 6 and right 7) of the next chip to be tested is determined by using a plurality of common direct current probes to detect the electrical characteristics of the next chip to be tested, so that the test cost is reduced, and the design and development expenses are reduced.
Drawings
FIG. 1 is a schematic diagram of the distribution of three design types of a block in MPW;
fig. 2 is a schematic flowchart of a method for measuring a power carrying capacity of a radio frequency device according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a testing sequence of a method for measuring a power carrying capacity of an rf device according to an embodiment of the invention.
Detailed Description
As shown in fig. 1, a block of MPW includes three sub-regions, which are regions A, B, C, each of which includes a plurality of chips to be tested, and each of the chips to be tested may include a serial branch, a parallel branch, and an ESD branch. Specifically, there are a plurality of series branches of different designs in region a, a plurality of parallel branches of different designs in region B, and a plurality of ESD branches of different designs in region C. As can be seen from fig. 1, the distribution of the chips to be tested in different types (serial branches in different designs, parallel branches in different designs, and ESD branches in different designs) on the MPW is not regular, so that in the early test preparation, the corresponding chip position coordinates need to be determined for each type of test, and the whole test preparation work is relatively tedious, which affects the time of design and development. Moreover, each type of test needs a special step (i.e. each type needs to test the MPW once), so that the test time is long, the time for design and development is also affected, and the test efficiency is low.
Based on the research, the invention provides a method for measuring the power bearing capacity of a radio frequency device, which comprises the following steps: step S1: providing a multi-project wafer, wherein the multi-project wafer comprises at least two types of chips to be tested; step S2: establishing a test file, wherein the test file comprises test conditions and test methods of at least two types of chips to be tested; and step S3: and calling the test conditions and the test method of the type of the current chip to be tested from the test file, measuring the current power bearing capacity of the chip to be tested, and simultaneously detecting the type of the next chip to be tested so as to measure the power bearing capacity of all chips to be tested. The invention establishes a test condition and a test method comprising at least two types of chips to be tested, the file comprises the test condition and the test method of the at least two types of chips to be tested, but the file does not comprise the steps of distinguishing and sorting the position coordinates of the chips to be tested aiming at different types, thereby greatly reducing the preliminary test preparation time, shortening the test preparation time, completing the test of the chips to be tested of different types through one test, shortening the test time, shortening the design development time and quickening the appearance of new products.
Further, testing each chip to be tested on the multi-project wafer according to the sequence of each row from left to right; the power bearing capacity of the current chip to be tested is measured by using a plurality of special probes for the radio frequency device, and meanwhile, the type (right 6 and right 7) of the next chip to be tested is determined by using a plurality of common direct current probes to detect the electrical characteristics of the next chip to be tested, so that the test cost is reduced, and the design and development expenses are reduced.
The method for measuring the power carrying capacity of the rf device according to the present invention will be described in further detail below. The present invention will now be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise ratio for the purpose of facilitating and distinctly aiding in the description of the embodiments of the invention.
Fig. 2 is a schematic flowchart of a method for measuring power carrying capacity of a radio frequency device according to this embodiment. As shown in fig. 2, the present embodiment provides a method for measuring a power carrying capacity of a radio frequency device, the method includes the following steps:
step S1: providing a multi-project wafer, wherein the multi-project wafer comprises at least two types of chips to be tested;
step S2: establishing a test file, wherein the test file comprises test conditions and test methods of at least two types of chips to be tested; and
step S3: and calling the test conditions and the test method of the type of the current chip to be tested from the test file, measuring the current power bearing capacity of the chip to be tested, and simultaneously detecting the type of the next chip to be tested so as to measure the power bearing capacity of all chips to be tested.
The following describes the method for measuring the power carrying capacity of the rf device according to the present embodiment in detail with reference to fig. 2 and 3.
First, step S1 is executed to provide a multi-project wafer including at least two types of chips to be tested.
In this embodiment, the multi-project wafer includes a plurality of chips to be tested, and each chip to be tested may include a serial branch, a parallel branch and an ESD branch. The multi-project wafer comprises three types of chips to be tested, namely chips to be tested with different designs in a serial branch, chips to be tested with different designs in a parallel branch and chips to be tested with different designs in an ESD branch, wherein each type is provided with a plurality of chips to be tested, each type of chip to be tested is irregularly distributed, the chips to be tested can be distributed according to blocks, and a plurality of chips to be tested of other types or several types can be mixed in a concentrated block of one type.
It is a great project to establish a test file for each type in the prior art, and for this purpose, step S2 is executed to establish a test file including test conditions and test methods for at least two types of chips to be tested.
In the steps, a test condition and a test method comprising at least two types of chips to be tested are established, the file comprises the test condition and the test method of the at least two types of chips to be tested, but the file does not comprise the step of distinguishing and sorting out the position coordinates of the chips to be tested aiming at different types, so that the early test preparation time is greatly reduced, the test preparation time is shortened, the design and development time is shortened, and the step of coming up of new products is accelerated.
Then, step S3 is executed to retrieve the test conditions and the test methods of the types of the current chips to be tested from the test files, and to measure the power carrying capacity of the current chip to be tested, and to detect the type of the next chip to be tested at the same time, so as to measure the power carrying capacities of all chips to be tested.
The method comprises the following steps:
step S31 is executed first, the type of the first chip to be tested is confirmed, the test condition and the test method of the type of the first chip to be tested are retrieved from the test file, the power carrying capacity of the first chip to be tested is measured, and the type of the second chip to be tested is detected at the same time. In the step, when the current power bearing capacity is tested, the type of the next chip to be tested can be simultaneously detected, so that after the current test is finished, the test condition and the test method of the type of the next chip to be tested can be directly called and measured. The method specifically comprises the following steps: firstly, at the beginning of the test, a tester firstly confirms the type of a first chip to be tested so as to confirm the specific type of the chip to be tested, namely whether the first chip to be tested needs to test the power bearing capacity of a series branch, a parallel branch or an ESD branch. Then, calling the testing conditions and the testing method of the type of the first chip to be tested from the testing file, and measuring the power bearing capacity of the first chip to be tested; and simultaneously, detecting the type of the second chip to be detected.
Next, step S32 is executed to retrieve the current test condition and test method of the type of the chip to be tested from the test file, measure the power carrying capacity of the current chip to be tested, and detect the type of the next chip to be tested at the same time to measure the power carrying capacity of all chips to be tested.
The method specifically comprises the following steps: firstly, starting from a second chip to be tested, taking each chip to be tested as the current chip to be tested, calling the test conditions and the test method of the type of the current chip to be tested from the test file, measuring the power bearing capacity of the current chip to be tested, and simultaneously detecting the type of the next chip to be tested. In this step, the type of the second chip to be tested is determined while the first chip to be tested is tested, so that all chips to be tested except the first chip to be tested can know the type of the first chip to be tested in advance before the test of the first chip to be tested is started, and the test starting time of the current chip to be tested is directly started after the test of the last chip to be tested is finished. And then, outputting the test result of each chip to be tested after the test of each chip to be tested is finished. And finally, testing each chip to be tested in the multi-project wafer by adopting the steps, thereby completing the test of each type of power bearing capacity. The whole process has short testing time and high testing efficiency.
In this embodiment, each chip to be tested may be tested in a certain sequence, for example, the multiple chips to be tested in the first row of the multi-project wafer 1 are sequentially measured from left to right, and then the multiple chips to be tested in the second row to the multiple chips to be tested in the last row are sequentially measured from left to right (as shown in fig. 3); the method can also sequentially measure a plurality of chips to be measured in a first row of the multi-project wafer from top to bottom, and then sequentially measure a plurality of chips to be measured in a second row to a plurality of chips to be measured in a last row from top to bottom; the measurement sequence of the chips to be measured in the odd-numbered rows is the same as that of the chips to be measured in the first row, and the measurement sequence of the chips to be measured in the even-numbered rows is the same as that of the chips to be measured in the second row, namely the whole test process is in a snake shape; other ways may also be used, such as measuring from right to left in each row, from bottom to top in each column, etc.
The measuring method can test each chip to be tested on the multi-project wafer in sequence, so that the test of at least two types of chips to be tested can be completed by one-time test of one multi-project wafer, the further test time is shortened, the test efficiency is improved, and the design and development time is further shortened.
Due to the distribution inside the chips, a plurality of chips to be tested in a first row of the multi-project wafer are sequentially measured from left to right, then a plurality of chips to be tested in a second row to a plurality of chips to be tested in a last row are sequentially measured from left to right, and the power bearing capacity of the current chips to be tested can be measured by using a first group of probes (namely a plurality of probes special for radio frequency); meanwhile, a second group of probes (namely a plurality of common direct current probes) are used for detecting the electrical characteristics of the next chip to be tested to determine the type of the next chip to be tested; other test sequences require two sets of probes dedicated to radio frequency to test the power carrying capacity of the current chip under test and to detect the electrical characteristics of the next chip under test to determine the type of the chip.
This embodiment adopts a plurality of chips that await measuring of first line from many project wafer to measure from left to right in proper order, all measures from left to right in proper order a plurality of chips that await measuring of second line to a plurality of chips that await measuring of last line for it only needs a set of dedicated a plurality of probe of radio frequency, can reduce test cost, thereby has reduced the expense of design and development.
In summary, the present invention provides a method for measuring power carrying capacity of a radio frequency device, including the following steps: step S1: providing a multi-project wafer, wherein the multi-project wafer comprises at least two types of chips to be tested; step S2: establishing a test file, wherein the test file comprises test conditions and test methods of at least two types of chips to be tested; and step S3: and calling the test conditions and the test method of the type of the current chip to be tested from the test file, measuring the current power bearing capacity of the chip to be tested, and simultaneously detecting the type of the next chip to be tested so as to measure the power bearing capacity of all chips to be tested. The invention establishes a test condition and a test method comprising at least two types of chips to be tested, the file comprises the test condition and the test method of the at least two types of chips to be tested, but the file does not comprise the steps of distinguishing and sorting the position coordinates of the chips to be tested aiming at different types, thereby greatly reducing the preliminary test preparation time, shortening the test preparation time, completing the test of the chips to be tested of different types through one test, shortening the test time, shortening the design development time and quickening the appearance of new products.
Further, testing each chip to be tested on the multi-project wafer according to the sequence of each row from left to right; the power bearing capacity of the current chip to be tested is measured by using a plurality of special probes for the radio frequency device, and meanwhile, the type (right 6 and right 7) of the next chip to be tested is determined by using a plurality of common direct current probes to detect the electrical characteristics of the next chip to be tested, so that the test cost is reduced, and the design and development expenses are reduced.
In addition, it should be noted that the description of the terms "first", "second", and the like in the specification is only used for distinguishing each component, element, step, and the like in the specification, and is not used for representing a logical relationship or a sequential relationship between each component, element, step, and the like, unless otherwise specified or indicated.
It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (10)
1. A method for measuring power bearing capacity of a radio frequency device is characterized by comprising the following steps:
step S1: providing a multi-project wafer, wherein the multi-project wafer comprises at least two types of chips to be tested;
step S2: establishing a test file, wherein the test file comprises test conditions and test methods of at least two types of chips to be tested; and
step S3: and calling the test conditions and the test method of the type of the current chip to be tested from the test file, measuring the current power bearing capacity of the chip to be tested, and simultaneously detecting the type of the next chip to be tested so as to measure the power bearing capacity of all chips to be tested.
2. The method for measuring power carrying capacity of a radio frequency device according to claim 1, wherein the step S3 includes:
confirming the type of a first chip to be tested, calling a test condition and a test method of the type of the first chip to be tested from the test file, measuring the power bearing capacity of the first chip to be tested, and detecting the type of a second chip to be tested; and
and starting from the second chip to be tested, taking each chip to be tested as the current chip to be tested, calling the test conditions and the test method of the type of the current chip to be tested from the test file, measuring the power bearing capacity of the current chip to be tested, and simultaneously detecting the type of the next chip to be tested so as to measure the power bearing capacity of all the chips to be tested.
3. The method for measuring power carrying capacity of a radio frequency device according to claim 2, wherein in step S3, each of the chips to be tested on the multi-project wafer is tested in sequence.
4. The method of claim 3, wherein each of the chips under test on the multi-item wafer is tested in a left-to-right sequence, a right-to-left sequence, a top-to-bottom sequence, a bottom-to-top sequence, or a serpentine sequence.
5. The method for measuring power carrying capacity of a radio frequency device according to claim 4, wherein a first set of probes is used to measure the current power carrying capacity of the chip under test; and simultaneously, detecting the type of the next chip to be detected by using a second group of probes.
6. The method for measuring power carrying capacity of a radio frequency device according to claim 5, wherein each chip to be tested on the multi-project wafer is tested according to a sequence of each row of the multi-project wafer from left to right.
7. The method for measuring power carrying capacity of a radio frequency device according to claim 6, wherein the power carrying capacity of the chip under test is measured by using a plurality of probes dedicated to the radio frequency device; and simultaneously, detecting the electrical characteristics of the next chip to be tested by using a plurality of common direct current probes to determine the type of the chip.
8. The method of claim 1, wherein the multi-project wafer comprises a plurality of chips under test, and each chip under test comprises a serial branch, a parallel branch and an ESD branch.
9. The method according to claim 8, wherein the multi-project wafer comprises three types of chips to be tested, which are chips to be tested with different designs in serial branches, chips to be tested with different designs in parallel branches, and chips to be tested with different designs in ESD branches.
10. The method of claim 9, wherein each type has a plurality of chips under test.
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