CN110164789A - Crystal round test approach and wafer tester - Google Patents
Crystal round test approach and wafer tester Download PDFInfo
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- CN110164789A CN110164789A CN201910486619.0A CN201910486619A CN110164789A CN 110164789 A CN110164789 A CN 110164789A CN 201910486619 A CN201910486619 A CN 201910486619A CN 110164789 A CN110164789 A CN 110164789A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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Abstract
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of crystal round test approach and wafer tester.The crystal round test approach includes the following steps: to provide a wafer have multiple tube cores in the wafer；It selects at least one tube core as target tube core in the edge of the wafer, and obtains the essential information of multiple adjacent tube cores around the coordinates of targets and the target tube core of the target tube core；At traveling probe to the coordinates of targets, and using the tube core at position corresponding to current probe as test dies；Multiple adjacent tube cores around the test dies are tested using probe, obtain multiple test information；Judge whether multiple essential informations match one by one with multiple test information, if it is not, then focusing offset occurs for exact p-value board.The present invention can quickly determine whether wafer test board occurs focusing offset, improve the reliability of wafer test.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of crystal round test approach and wafer tester.
Background technique
As the mobile terminals such as smart phone, tablet computer develop to the direction of miniaturization, intelligence, energy-saving, chip
High-performance, integrated trend it is obvious, promote chip manufacturing enterprise active adoption advanced technologies, to produce faster, more power saving
The pursuit of chip grow in intensity.The main element of especially many wireless telecommunications systems need to use 40nm or less sophisticated semiconductor skill
Art and technique, therefore the demand to advanced technologies production capacity significantly rises as compared with the past, and integrated circuit suppliers is driven constantly to promote work
Skill technical level, by reduce wafer both horizontally and vertically on characteristic size to improve chip performance and reliability, and
The modes such as the electrical property for influencing wafer by the utilization of the non-geometric technology such as 3D structure of modification and new material, realize silicon collection
At raising, to cater to the market demand.However, the innovation or improvement of these technologies are all based on brilliant circle drawing, manufacture.
Wafer test (Chip Probing, CP) is an important link in integrated circuit production process, the purpose is to
Bad tube core (Die) is picked out, to save useless chip package cost.CP test purpose be under reasonable cost control,
Test result is obtained with certain confidence level.CP test has become technology controlling and process, finished product yield management, product quality and reduction
One committed step of testing cost.On wafer, after semiconductor devices completes, scribing encapsulation before, can to wafer into
Row CP test, due to also unencapsulated at this time, carrying out test to the device under test (DUT) on wafer is by the probe in probe card
On the weld pad (PAD) for touching the test reserved on crystal column surface, then by test program, toward probe on load accordingly
Test electric signal is tested, and obtains some performance informations of the tube core in whole wafer, including whether there is short circuit, whether just function
Often, performance height is low, carries out screening to multiple tube cores on wafer with this and divides bin.
Whether board focusing is accurately to ensure that the important evidence of reliable test result in CP test.Once board focusing occurs
Offset, it will cause test result mistakes.It is carried out accurately however, can not focus whether to shift to board in the prior art
Detection, causes the reliability of test result to reduce.
Therefore, the reliability for how improving wafer test result, avoids the occurrence of test errors, is skill urgently to be resolved at present
Art problem.
Summary of the invention
The present invention provides a kind of crystal round test approach and wafer tester, for solving wafer test knot in the prior art
The lower problem of fruit reliability, to ensure the quality of semiconductor product.
To solve the above-mentioned problems, the present invention provides crystal round test approach, include the following steps:
One wafer is provided, there are multiple tube cores in the wafer；
It selects at least one tube core as target tube core in the edge of the wafer, and obtains the target of the target tube core
The essential information of multiple adjacent tube cores around coordinate and the target tube core；
At traveling probe to the coordinates of targets, and using the tube core at position corresponding to current probe as test dies；
Multiple adjacent tube cores around the test dies are tested using probe, obtain multiple test information；
Judge whether multiple essential informations match one by one with multiple test information, if it is not, then exact p-value machine
Focusing offset occurs for platform.
Preferably, the essential information includes location information and its institute of each adjacent tube core relative to the target tube core
Corresponding type of die.
Preferably, multiple adjacent tube cores around the coordinates of targets and the target tube core of the target tube core are obtained
The specific steps of essential information include:
Obtain be located at the target tube core upside, downside, left and right side adjacent tube core essential information.
Preferably, the edge of Yu Suoshu wafer selects at least one tube core to include: as the specific steps of target tube core
Select multiple tube cores respectively as target tube core in the edge of the wafer, and multiple target tube cores are distributed in
The opposite sides of one radial direction of wafer, and obtain respectively each target tube core coordinates of targets and the target
The essential information of multiple adjacent tube cores around tube core.
Preferably, the edge of Yu Suoshu wafer selects multiple tube cores to include: respectively as the specific steps of target tube core
Multiple target tube cores are distributed about the central symmetry of the wafer, and it is opposite to be located at each target tube core
The type of die of the adjacent tube core of two sides is different.
Preferably, the edge of Yu Suoshu wafer selects multiple tube cores to include: respectively as the specific steps of target tube core
Center asymmetric distribution of multiple target tube cores about the wafer.
To solve the above-mentioned problems, the present invention also provides a kind of wafer testers, comprising:
Selecting module, for selecting at least one tube core as target tube core from the edge of the wafer, in the wafer
With multiple tube cores, the target tube core is located at the edge of the wafer；
Memory module connects the selecting module, for obtain the target tube core coordinates of targets and the target
The essential information of multiple adjacent tube cores around tube core；
Test module connects the memory module, and the test module includes probe, for probe to be moved to the mesh
It marks at coordinate, and using the tube core at position corresponding to current probe as test dies；The test module is also used to control institute
It states probe to test multiple adjacent tube cores around the test dies, obtains multiple test information；
Comparison module connects the test module, the memory module, for judge multiple essential informations with it is multiple
Whether the test information matches one by one, if it is not, then focusing offset occurs for exact p-value board.
Preferably, the essential information includes location information and its institute of each adjacent tube core relative to the target tube core
Corresponding type of die.
Preferably, the memory module, which is used to obtain, is located at the target tube core upside, downside, left and right side
The essential information of adjacent tube core.
Preferably, the selecting module is used to selecting multiple tube cores respectively as target tube core from the edge of the wafer,
And multiple target tube cores are distributed in the opposite sides of one radial direction of wafer, and obtain each target tube respectively
The essential information of multiple adjacent tube cores around the coordinates of targets of core and the target tube core.
Crystal round test approach and wafer tester provided by the invention, by selecting at least one at the edge of wafer in advance
A tube core obtains the coordinates of targets of the target tube core and multiple adjacent around the target tube core as target tube core
The essential information of tube core, after probe is then moved to position corresponding with the coordinates of targets again, at the coordinates of targets
Corresponding tube core is test dies, is judged around test information and the target tube core of multiple adjacent tube cores around test dies
Whether the essential information of multiple adjacent tube cores corresponds matching, if it is not, then illustrating that board focusing shifts, in wafer figure
It shifts between coordinate position and the physical location of wafer, such as the practical position deviation theory in board of wafer presets position
It sets；If so, illustrating that board focusing is accurate, such as the practical position in board of wafer is identical as theoretical predeterminated position.In this way,
It can quickly determine whether wafer test board occurs focusing offset, the test result for exception occur is handled in time, is mentioned
The high reliability of wafer test, it is ensured that the quality of semiconductor product.
Detailed description of the invention
Attached drawing 1 is the flow chart of crystal round test approach in the specific embodiment of the invention；
Attached drawing 2 is the location map of target tube core in the embodiment of the invention；
Attached drawing 3 is the location map of target tube core in another specific embodiment of the present invention；
Attached drawing 4A-4C is the hollow tube core of the specific embodiment of the invention respectively, does not complete tube core and the knot of tube core is completed
Structure schematic diagram；
Attached drawing 5 is the structural block diagram of wafer tester in the specific embodiment of the invention.
Specific embodiment
The specific embodiment of crystal round test approach provided by the invention and wafer tester is done with reference to the accompanying drawing
It is described in detail.
Present embodiment provides a kind of crystal round test approach, and attached drawing 1 is wafer in the specific embodiment of the invention
The flow chart of test method, attached drawing 2 are the location maps of target tube core in the embodiment of the invention.As shown in Figure 1, Figure 2
Shown, the crystal round test approach that present embodiment provides includes the following steps:
Step S11 provides a wafer 20, has multiple tube cores 21 in the wafer 20.
The edge of step S12, Yu Suoshu wafer 20 selects at least one tube core 21 as target tube core, and obtains the mesh
Mark the coordinates of targets of tube core and the essential information of multiple adjacent tube cores around the target tube core.
Preferably, the essential information includes location information and its institute of each adjacent tube core relative to the target tube core
Corresponding type of die.Wherein, the type of die includes blank pipe core, does not complete tube core and tube core is completed.
Attached drawing 4A-4C is the hollow tube core of the specific embodiment of the invention respectively, does not complete tube core and the knot of tube core is completed
Structure schematic diagram.Specifically, the wafer 20 has the multiple tube cores 21 arranged with array manner.Wherein, the standard tube core class
Type includes blank pipe core 40, does not complete tube core 41 or tube core 42 is completed.Tube core 42 is completed described in present embodiment
Refer to, complete device architecture and the tube core with corresponding function has been formed in tube core, as shown in Figure 4 C；It is described not complete
Refer at tube core 41, is only formed with part of devices structure, the tube core without corresponding function in tube core, as shown in Figure 4 B；Institute
It states blank pipe core 40 to refer to, does not have the tube core of any device architecture in tube core, as shown in Figure 4 A.The wafer 20 includes device
Region and peripheral region, the tube core 42 that is completed are distributed in the device area；The blank pipe core 40 is distributed in the periphery
Region；The unfinished tube core 41, which is distributed in from the device area, extends to the peripheral region, i.e., the described unfinished tube core
41 parts are distributed in the device area, are partially distributed in the peripheral region.
In order to reduce detection, improve testing efficiency, the edge of Yu Suoshu wafer 20 select at least one tube core as
The specific steps of target tube core are as follows: the edge of 20 device area of Yu Suoshu wafer selects at least one that tube core 42 is completed as mesh
Mark tube core.This is because being located at being completed for device area edge at least has different adjacent of two types around tube core 42
Tube core for example, at least has one and tube core 42 and a unfinished tube core 41 or blank pipe core 40 is completed.
Step S13, at traveling probe to the coordinates of targets, and using the tube core at position corresponding to current probe as surveying
Test tube core.
Specifically, the probe is to be tested according to probe wafer figure the tube core on the wafer 20.Manipulator
Arm controls the probe and is moved at the coordinates of targets in the probe wafer figure.It does not shift in board focusing
When, the position coordinates of multiple tube cores correspond on the multiple position coordinates and the wafer 20 in the probe wafer figure, because
This, when the probe is moved at the coordinates of targets according to the probe wafer figure, at position corresponding to current probe
Tube core is the target tube core, i.e., the described test dies are the target tube core.When board focusing shifts,
The position coordinates of multiple position coordinates and multiple tube cores on the wafer 20 in the probe wafer figure no longer correspond,
But accordingly shift, therefore, when the probe is moved at the coordinates of targets according to the probe wafer figure, currently
Tube core at position corresponding to probe is not then the target tube core, i.e., the described test dies are not the target tube cores.
Step S14 is tested using probe pair and multiple adjacent tube cores around the test dies, obtains multiple surveys
Try information.
It specifically, can be multiple adjacent around the test dies to being located at using the method for four probe method measuring resistance
Tube core is tested, to obtain multiple test information.
Step S15, judges whether multiple essential informations match one by one with multiple test information, if it is not, then really
Recognize tester table and focusing offset occurs.
Present embodiment is by the test to adjacent tube core around, to judge whether current test dies are target tube
Core, and then whether exact p-value board occurs focusing offset.Specifically, when a test information and multiple basic letters
When breath matches one by one, then illustrate multiple adjacent tube cores around the test dies and multiple phases around the target tube core
Adjacent tube core corresponds, so can be confirmed the test dies be the target tube core (the i.e. described test dies with it is described
Target tube core is same tube core), finally obtain the conclusion that focusing offset does not occur for the board；When multiple test information not
When can match one by one with multiple essential informations, then illustrate the multiple adjacent tube cores and the target around the test dies
Multiple adjacent tube cores around tube core cannot correspond, and then it is the target tube core that the test dies, which can be confirmed, not
(the i.e. described test dies and the target tube core are not same tube core) finally obtains the knot that focusing offset occurs for the board
By.
Present embodiment can complete probe test in the wafer 20 and then focusing whether occurs partially to board
Shift-in row detection.When focusing offset occurs for testing result confirmation board, then staff is reminded in a manner of alarm etc., in order to
Abnormal conditions are handled in time.
In X/Y plane as shown in Figure 1, the adjacent tube core around the target tube core includes and the target tube core phase
It is adjacent and be located at the target tube core upside, downside, left side, right side, upper left side, upper right side, lower left side and lower right side this in total 8
The tube core of a position.In order to simplify testing procedure, it is preferred that obtain the target tube core coordinates of targets and the target tube
The specific steps of the essential information of multiple adjacent tube cores around core include:
Obtain be located at the target tube core upside, downside, left and right side adjacent tube core essential information.
Specifically, after selecting the target tube core, the basic letter of the adjacent tube core of the target tube core surrounding is obtained
Breath.After the probe is moved at the coordinates of targets, by centered on the test dies, to upside, downside, left side
It moves a unit quantity respectively with right side and obtains the type information of each corresponding position tube core by test, institute can be obtained
State test information.The test information also includes each adjacent tube core relative to the position of the test dies and its corresponding
Type of die.
Preferably, the edge of Yu Suoshu wafer 20 selects at least one tube core 21 as the specific steps packet of target tube core
It includes:
Select multiple tube cores respectively as target tube core in the edge of the wafer 20, and multiple target tube cores are distributed
In the opposite sides of 20 1 radial direction of wafer, and the coordinates of targets of each target tube core and described is obtained respectively
The essential information of multiple adjacent tube cores around target tube core.
Wherein, the particular number of the target tube core, those skilled in the art can select according to actual needs.It is logical
The opposite sides that multiple target tube cores are distributed in 20 1 radial direction of wafer is crossed, convenient for board focusing offset
Direction is confirmed.
Preferably, the edge of Yu Suoshu wafer 20 selects multiple tube cores to include: respectively as the specific steps of target tube core
Multiple target tube cores are distributed about the central symmetry of the wafer, and it is opposite to be located at each target tube core
The type of die of the adjacent tube core of two sides is different.
It is with the two shown in Fig. 2 target tube cores (i.e. first object tube core 211 and the second target tube core 212) below
Example is illustrated, correspondingly, probe needs the phase tested around first test dies corresponding with the first object tube core 211
Adjacent tube core information around adjacent tube core information and second test dies corresponding with the second target tube core 212.Table 1
It is the adjacent tube core essential information around first object tube core 211 and the second target tube core 212.When positioned at first testing tube
Adjacent tube core around core is basic with the adjacent tube core around first object tube core in table 1 on relative position and type of die
The information matches and adjacent tube core being located at around second test dies is on relative position and type of die and in table 1
Adjacent tube core essential information matching around second target tube core then confirms that focusing offset does not occur for the board.Conversely, working as institute
It is that tube core is completed or is located at described second to survey that probe in detecting, which is stated, to the adjacent tube core being located on the left of first test dies
Adjacent tube core on the right side of test tube core is then to confirm that focusing offset along the x axis occurs for the board when tube core is completed；Work as institute
It is to be completed under tube core or the second test dies that probe in detecting, which is stated, to the adjacent tube core being located on the upside of first test dies
The adjacent tube core of side is then to confirm that focusing offset along the y axis occurs for the board when tube core is completed.
Adjacent tube core essential information around 1 two target tube cores of table
In other specific embodiments, the edge of Yu Suoshu wafer selects multiple tube cores respectively as the tool of target tube core
Body step includes:
Center asymmetric distribution of multiple target tube cores about the wafer.
Attached drawing 3 is the location map of target tube core in another specific embodiment of the present invention.Below with shown in Fig. 3 four
A the target tube core (i.e. third target tube core 301, the 4th target tube core 302, the 5th target tube core 303 and the 6th target tube
Core 304) for be illustrated, correspondingly, probe needs to test corresponding with the third target tube core 301 third test dies
Around adjacent tube core information, the adjacent tube core information around the 4th test dies corresponding with the 4th target tube core 302,
Adjacent tube core information around the 5th test dies corresponding with the 5th target tube core 303 and with the 6th target
Adjacent tube core information around corresponding 6th test dies of tube core 304.Specifically, the third target tube core 301, described
4th target tube core 302, the 5th target tube core 303 and the 6th target tube core 304 are located at 20 device of wafer
Left side edge, lower edge, right side edge and the upper edge in part region.Table 2 is third target tube core 301, the 4th target tube
Adjacent tube core essential information around core 302, the 5th target tube core 303 and the 6th target tube core 304.By comparing each test
Whether the test information of adjacent tube core matches with the essential information in table 2 around tube core, that is, can determine whether tester table occurs
Focusing offset.In addition, by reasonably select target tube core position and quantity, additionally it is possible to determine focusing offset direction and partially
Shifting amount is adjusted convenient for transmission position of the later stage work personnel to mechanical arm.
Adjacent tube core essential information around 2 four target tube cores of table
Moreover, present embodiment additionally provides a kind of wafer tester, and attached drawing 5 is specific implementation of the present invention
The control method of the structural block diagram of wafer tester in mode, the wafer tester that present embodiment provides can join
As shown in Fig. 1-Fig. 3, Fig. 4 A- Fig. 4 C.As shown in Fig. 1-Fig. 3, Fig. 4 A- Fig. 4 C and Fig. 5, the wafer of present embodiment offer
Test device includes:
Selecting module 50, it is described for selecting at least one tube core 21 as target tube core from the edge of the wafer 20
There are multiple tube cores 21, the target tube core is located at the edge of the wafer 20 in wafer 20；
Memory module 51 connects the selecting module 50, for obtaining the coordinates of targets of the target tube core and described
The essential information of multiple adjacent tube cores around target tube core；
Test module 52 connects the memory module 51, and the test module 52 includes probe, for probe to be moved to
At the coordinates of targets, and using the tube core at position corresponding to current probe as test dies；The test module 52 is also used
It is tested in controlling the probe pair with multiple adjacent tube cores around the test dies, obtains multiple test information；
Comparison module 53 connects the test module 52, the memory module 51, for judging multiple essential informations
Whether matched one by one with multiple test information, if it is not, then focusing offset occurs for exact p-value board.
Preferably, the essential information includes location information and its institute of each adjacent tube core relative to the target tube core
Corresponding type of die.
Preferably, the memory module 51 is located at the target tube core upside, downside, left and right side for obtaining
Adjacent tube core essential information.
Preferably, the selecting module 50 is used to select multiple tube cores respectively as target tube from the edge of the wafer
Core, and multiple target tube cores are distributed in the opposite sides of one radial direction of wafer, and obtain each mesh respectively
Mark the coordinates of targets of tube core and the essential information of multiple adjacent tube cores around the target tube core.
The crystal round test approach and wafer tester that present embodiment provides, by being selected in advance at the edge of wafer
At least one tube core is selected as target tube core, and around the coordinates of targets and the target tube core of the acquisition target tube core
The essential information of multiple adjacent tube cores, after probe is then moved to position corresponding with the coordinates of targets again, with the mesh
Marking corresponding tube core at coordinate is test dies, judges the test information and target tube of multiple adjacent tube cores around test dies
Whether the essential information of multiple adjacent tube cores around core corresponds matching, if it is not, then illustrate that board focusing shifts, it is brilliant
It coordinate position in circle diagram and shifts between the physical location of wafer, such as reason is deviateed in the practical position in board of wafer
By predeterminated position；If so, illustrating that board focusing is accurate, such as the practical position in board of wafer and theoretical predeterminated position phase
Together.In this way, can quickly determine whether wafer test board occurs focusing offset, the test result for exception occur is carried out in time
Processing, improves the reliability of wafer test, it is ensured that the quality of semiconductor product.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (10)
1. a kind of crystal round test approach, which comprises the steps of:
One wafer is provided, there are multiple tube cores in the wafer；
It selects at least one tube core as target tube core in the edge of the wafer, and obtains the coordinates of targets of the target tube core
And the essential information of multiple adjacent tube cores around the target tube core；
At traveling probe to the coordinates of targets, and using the tube core at position corresponding to current probe as test dies；
Multiple adjacent tube cores around the test dies are tested using probe, obtain multiple test information；
Judge whether multiple essential informations match one by one with multiple test information, if it is not, then exact p-value board is sent out
Raw focusing offset.
2. crystal round test approach according to claim 1, which is characterized in that the essential information includes each adjacent tube core
Location information and its corresponding type of die relative to the target tube core.
3. crystal round test approach according to claim 2, which is characterized in that obtain the coordinates of targets of the target tube core with
And the specific steps of the essential information of multiple adjacent tube cores around the target tube core include:
Obtain be located at the target tube core upside, downside, left and right side adjacent tube core essential information.
4. crystal round test approach according to claim 3, which is characterized in that the edge of Yu Suoshu wafer selects at least one
Tube core includes: as the specific steps of target tube core
Select multiple tube cores respectively as target tube core in the edge of the wafer, and multiple target tube cores be distributed in it is described
The opposite sides of one radial direction of wafer, and the coordinates of targets and the target tube core of each target tube core are obtained respectively
The essential information of multiple adjacent tube cores of surrounding.
5. crystal round test approach according to claim 4, which is characterized in that the edge of Yu Suoshu wafer selects multiple tube cores
Specific steps respectively as target tube core include:
Multiple target tube cores are distributed about the central symmetry of the wafer, and are located at each target tube core opposite sides
Adjacent tube core type of die it is different.
6. crystal round test approach according to claim 4, which is characterized in that the edge of Yu Suoshu wafer selects multiple tube cores
Specific steps respectively as target tube core include:
Center asymmetric distribution of multiple target tube cores about the wafer.
7. a kind of wafer tester characterized by comprising
Selecting module has in the wafer for selecting at least one tube core as target tube core from the edge of the wafer
Multiple tube cores, the target tube core are located at the edge of the wafer；
Memory module connects the selecting module, for obtaining the coordinates of targets and the target tube core of the target tube core
The essential information of multiple adjacent tube cores of surrounding；
Test module connects the memory module, and the test module includes probe, sits for probe to be moved to the target
At mark, and using the tube core at position corresponding to current probe as test dies；The test module is also used to control the spy
It is tested for multiple adjacent tube cores around the test dies, obtains multiple test information；
Comparison module connects the test module, the memory module, for judge multiple essential informations with it is multiple described
Whether test information matches one by one, if it is not, then focusing offset occurs for exact p-value board.
8. wafer tester according to claim 7, which is characterized in that the essential information includes each adjacent tube core
Location information and its corresponding type of die relative to the target tube core.
9. wafer tester according to claim 8, which is characterized in that the memory module is located at for obtaining
The target tube core upside, downside, left and right side adjacent tube core essential information.
10. wafer tester according to claim 9, which is characterized in that the selecting module is used for from the wafer
Edge select multiple tube cores respectively as target tube core, and multiple target tube cores are distributed in one radial direction of wafer
Opposite sides, and obtain multiple adjacent tubes around the coordinates of targets and the target tube core of each target tube core respectively
The essential information of core.
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| CN111123072A (en) * | 2019-12-26 | 2020-05-08 | 武汉邮电科学研究院有限公司 | Hybrid probe card applied to wafer-level online test of silicon-based optoelectronic chip |
| CN112666448A (en) * | 2020-12-18 | 2021-04-16 | 江苏艾科半导体有限公司 | DELP series probe station driving configuration method in chip CP test |
| CN113030701A (en) * | 2021-03-09 | 2021-06-25 | 上海华虹宏力半导体制造有限公司 | Method for measuring power bearing capacity of radio frequency device |
| CN113130342A (en) * | 2021-04-15 | 2021-07-16 | 筏渡(上海)科技有限公司 | Method and device for marking wafer low-reliability failed tube core |
| CN113270342A (en) * | 2021-04-20 | 2021-08-17 | 深圳米飞泰克科技有限公司 | Wafer test dislocation monitoring method, device, equipment and storage medium |
| CN113782470A (en) * | 2021-09-10 | 2021-12-10 | 长鑫存储技术有限公司 | Method and device for adjusting wafer transfer position and semiconductor equipment |
| CN116705670A (en) * | 2023-08-07 | 2023-09-05 | 拉普拉斯新能源科技股份有限公司 | Grabbing method and device for height Wen Zhou |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811298A (en) * | 2012-11-15 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for test alignment chip |
| CN104422864A (en) * | 2013-08-21 | 2015-03-18 | 上海华虹宏力半导体制造有限公司 | Method for confirming position alignment in wafer test |
| CN108919084A (en) * | 2018-06-28 | 2018-11-30 | 上海华力微电子有限公司 | A kind of joint test method of multi-project wafer |
-
2019
- 2019-06-05 CN CN201910486619.0A patent/CN110164789A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811298A (en) * | 2012-11-15 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for test alignment chip |
| CN104422864A (en) * | 2013-08-21 | 2015-03-18 | 上海华虹宏力半导体制造有限公司 | Method for confirming position alignment in wafer test |
| CN108919084A (en) * | 2018-06-28 | 2018-11-30 | 上海华力微电子有限公司 | A kind of joint test method of multi-project wafer |
Cited By (10)
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| CN111123072A (en) * | 2019-12-26 | 2020-05-08 | 武汉邮电科学研究院有限公司 | Hybrid probe card applied to wafer-level online test of silicon-based optoelectronic chip |
| CN112666448A (en) * | 2020-12-18 | 2021-04-16 | 江苏艾科半导体有限公司 | DELP series probe station driving configuration method in chip CP test |
| CN113030701A (en) * | 2021-03-09 | 2021-06-25 | 上海华虹宏力半导体制造有限公司 | Method for measuring power bearing capacity of radio frequency device |
| CN113130342A (en) * | 2021-04-15 | 2021-07-16 | 筏渡(上海)科技有限公司 | Method and device for marking wafer low-reliability failed tube core |
| CN113270342A (en) * | 2021-04-20 | 2021-08-17 | 深圳米飞泰克科技有限公司 | Wafer test dislocation monitoring method, device, equipment and storage medium |
| CN113782470A (en) * | 2021-09-10 | 2021-12-10 | 长鑫存储技术有限公司 | Method and device for adjusting wafer transfer position and semiconductor equipment |
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| CN116705670A (en) * | 2023-08-07 | 2023-09-05 | 拉普拉斯新能源科技股份有限公司 | Grabbing method and device for height Wen Zhou |
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