CN103811298A - Manufacturing method for test alignment chip - Google Patents

Manufacturing method for test alignment chip Download PDF

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Publication number
CN103811298A
CN103811298A CN201210460903.9A CN201210460903A CN103811298A CN 103811298 A CN103811298 A CN 103811298A CN 201210460903 A CN201210460903 A CN 201210460903A CN 103811298 A CN103811298 A CN 103811298A
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chip
region
test
manufacturing
chips
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CN201210460903.9A
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CN103811298B (en
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洪雪辉
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

The invention discloses a manufacturing method for a test alignment chip. The manufacturing method is characterized by comprising a first step of exposing all areas in a silicon wafer during graph definition at an initial stage of a process; a second step of selecting a small area M to perform secondary exposure at the complete shot position of the silicon wafer when alignment chip manufacturing is needed due to the fact that the chip size is too small, failing all the chips or some chips in the area M, and forming an invalid chip array to be used for test alignment; and a third step of judging whether test results undergo leftward, rightward, upward and downward offset relative to actual chip results on the wafer according to whether valid chips are contained in chips around the invalid chip in the area M. Compared with a conventional method for manufacturing the invalid chip in a no-exposure mode, the manufacturing method for a test alignment chip has the advantages that the influenced area is little, the judging accuracy is high, and the number change flexibility of the invalid chips is high.

Description

The manufacture method that uses chip is aimed in test
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, particularly relate to a kind of test and aim at the manufacture method that uses chip.
Background technology
In semiconductor rear section testing electrical property, packaging and testing process, when hour (common monolateral size is less than 2 millimeters) of chip size, can be due to the position deviation of aiming at, cause the station location marker mistake of actual non-defective unit/defective products on silicon chip, thereby cause qualified/defective decision error of final product.
Common way is in FEOL, the each imperfect exposure range in two ends of selecting silicon chip diametric(al) to distribute, the mode of not exposing, chip in the not exposure range of specifying is made to the chip of inefficacy, thereby by the fixed position chip failing of knowing in advance, whether be effective chip in conjunction with adjacent ranks again, as the decision method of position alignment.Concrete manufacture method is as follows:
Step 1, at the technique initial stage when graphical definition, the All Ranges (SHOT) in silicon chip all exposes, as shown in Figure 1a, wherein Shot is the scope of the disposable exposure of photoetching in chip manufacturing process.
Step 2, when this silicon chip because chip size when too small, need to aim at chip manufacturing, for this type of silicon chip, in the time that chip manufacturing proceeds to last one deck metal level time, by exposure software set, the imperfect SHOT of silicon chip periphery is defined as to the region of not exposing, as shown in SHOTA, SHOTB in Fig. 1 b.
Step 3, according to whether containing effective chip in SHOTA, SHOTB periphery chip, judge test result whether with silicon chip on actual chips result be offset.
Wherein determine whether that the method being subjected to displacement is: owing to having known that in advance in Shot A and Shot B, (A-I) chip is chip failing, detect in test result and effectively whether to contain effective chip in Shot A/B periphery chip by associated program, judge test result whether with silicon chip on actual chips result be offset, the wherein size of a chip of Regional Representative at A-I place.
For SHOT A, the effective number > 0 of X, not skew left, the effective number > 0 of Y, does not offset downward, as Fig. 2 a.For SHOTB, the effective number > 0 of X, not skew to the right, the effective number > 0 of Y, not upwards skew, as Fig. 2 b.
As mentioned above, utilize traditional test to aim at chip manufacture method, if simultaneously upper and lower to what test, left and right four direction carries out pre-check, need to two imperfect SHOT be at least set in diametric(al) does not expose, with 29000 of chip count, 1 millimeter × 1 millimeter of chip size, 20 × 20 millimeters of SHOT sizes are example, as shown in Figure 3, in SHOTA, remove edge 3mm inactive area, utilize mathematics geometrical relationship, can be in the hope of the area of described delta-shaped region, thereby show that the method affects 40 more than chip, in like manner, in SHOTB, remove edge 3mm inactive area, affect 40 more than chip.Two, edge SHOT affects altogether and is greater than 80 effective chips, and the ratio of impact is greater than 0.3%.Chip failing quantity is many, large on the actual yield impact of silicon chip, and the accuracy rate of judging is not high.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of test and aims at the manufacture method that uses chip, can significantly reduce the quantity of chip failing, improves the actual yield of silicon chip.
For solving the problems of the technologies described above, a kind of test provided by the invention aimed at the manufacture method that uses chip, it is characterized in that, comprising:
Step 1, at the technique initial stage when graphical definition, the All Ranges in silicon chip all exposes;
Step 2, when this silicon chip because chip size when too small, need to aim at chip manufacturing time, for this type of silicon chip, on the position of the inner complete shot of silicon chip, select a little region M to carry out re-expose, make all or part of chip failure in the M of region, form the chip array of an inefficacy, aim at and use as test;
Step 3, according to whether containing effective chip in the chip failing periphery chip in the M of region, judge test result whether with silicon chip on actual chips result there is left and right, upper and lower skew.
Further, described in step 2, make the whole chip failures in the M of region, be specially the mode being directly offset by pressure litho pattern in the M of region is offset, make graphics overlay in this exposure range, affect its electric parameters, thereby finally cause chip failure in the M of region.
Further, described in step 2, make the segment chip in the M of region lose efficacy, be specially by be of a size of standard with single-chip on mask plate, make the exposure range that specific attribute is " printing opacity ", in exposure process, this transparent figure is exposed on the chip in the M of region, making does not have figure in the exposure range of whole " printing opacity ", thereby makes transmission region chip failure.
Further, the judgement of described step 3 is specially: when the chip failing periphery chip in described region M is when Effective number of chips order is greater than 0 in a direction therein, in described direction, do not have skew, no person is offset.
The manufacture method that uses chip is aimed in test of the present invention, the method influence area that the not Exposure mode using with respect to routine is made chip failing is few, determination rate of accuracy is high, and the flexibility of chip failing number of variations is high, production method is simple, influence area is easily controlled, high reliability variable, that use as aligning chip is placed in chip failing position.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 a is known silicon wafer exposure area schematic;
Fig. 1 b is that chip manufacturing schematic diagram is aimed in known test;
Fig. 2 a is SHOTA offset detection schematic diagram;
Fig. 2 b is SHOTB offset detection schematic diagram;
Fig. 3 is SHOTA partial enlarged drawing;
Fig. 4 is that re-expose mode of the present invention is made test aligning chip schematic diagram;
Fig. 5 a is that image shift re-expose of the present invention is made test aligning chip schematic diagram;
Fig. 5 b is that mask plate of the present invention appends figure re-expose schematic diagram;
Fig. 6 is offset detection schematic diagram of the present invention.
Embodiment
For your auditor can be had a better understanding and awareness object of the present invention, feature and effect, the present invention program is described in detail as follows below in conjunction with accompanying drawing:
The present invention tests and aims at the manufacture method that uses chip, comprising:
Step 1, at the technique initial stage when graphical definition, All Ranges (SHOT) portion in silicon chip exposes, as shown in Figure 1a, wherein Shot is the scope of the disposable exposure of photoetching in chip manufacturing process.
Step 2, when this silicon chip because chip size when too small, need to aim at chip manufacturing, for this type of silicon chip, on the position of the inner complete shot of silicon chip, select a little region M to carry out re-expose, make all or part of chip failure in the M of region, form the chip array of an inefficacy, aim at and use as test, as shown in Figure 4.
Step 3, according to whether containing effective chip in the chip failing periphery chip in the M of region, judge test result whether with silicon chip on actual chips result there is left and right, upper and lower skew.
On the fixed position of Wafer, there is a fixing chip failing distribution array, can aim at inspection to the upper and lower, left and right four direction portion of silicon chip.The method influence area that the not Exposure mode that the method is used with respect to routine is made chip failing is few, and determination rate of accuracy is high.
Wherein, saidly in step 2 on the position of the inner complete shot of silicon chip, selects a little region M to carry out re-expose, make the chip failure in the M of region, the chip array of an inefficacy of formation, can have two kinds of embodiments, is described as follows:
1, the mode being directly offset by pressure is offset litho pattern in the M of region, makes graphics overlay in this exposure range, affects its electric parameters, thereby finally causes chip failure in the M of region, as Fig. 5 a.
2, by be of a size of standard with single-chip on mask plate, make the exposure range that specific attribute is " printing opacity ", in exposure process, this transparent figure is exposed on the chip in the M of region, making does not have figure in the exposure range of whole " printing opacity ", thereby makes transmission region chip failure, the method can further reduce the chip-count of impact, as Fig. 5 b, wherein, a region is light tight region, b is transmission region, and the effective chip within the scope of the method a can be not influenced.
The present invention judge test result whether with silicon chip on actual chips result generation offset method, as shown in Figure 6, wherein predict the chip failure of A-G, the wherein size of a chip of Regional Representative at A-G place, checks whether the chip of X/Y/S/Z lost efficacy to determine whether left and right, upper and lower skew, wherein, effective number of the chip of X/Y/S/Z is greater than 0, the party, upwards this is not offset, otherwise is offset, and has improved the accuracy of skew judgement.
The inventive method is with 29000 of chip count, 1 millimeter × 1 millimeter of chip size, 20 × 20 millimeters of SHOT sizes are example, the number of the effective chip of use of region M is 3 × 3 chip-count, i.e. 9 effective chips, in the time using the second embodiment, chip-count can be reduced to 7 or still less, the ratio of impact is less than 0.03%.Greatly reduce the number of test alignment failure chip.
By specific embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims (4)

1. test and aim at a manufacture method that uses chip, it is characterized in that, comprising:
Step 1, at the technique initial stage when graphical definition, the All Ranges portion in silicon chip exposes;
Step 2, when this silicon chip because chip size when too small, need to aim at chip manufacturing time, for this type of silicon chip, on the position of the inner complete shot of silicon chip, select a little region M to carry out re-expose, make all or part of chip failure in the M of region, form the chip array of an inefficacy, aim at and use as test;
Step 3, according to whether containing effective chip in the chip failing periphery chip in the M of region, judge test result whether with silicon chip on actual chips result there is left and right, upper and lower skew.
2. the manufacture method that uses chip is aimed in test as claimed in claim 1, it is characterized in that, described in step 2, make the whole chip failures in the M of region, being specially the mode being directly offset by pressure is offset litho pattern in the M of region, make graphics overlay in this exposure range, affect its electric parameters, thereby finally cause chip failure in the M of region.
3. the manufacture method that uses chip is aimed in test as claimed in claim 1, it is characterized in that, described in step 2, make the segment chip in the M of region lose efficacy, be specially by be of a size of standard with single-chip on mask plate, make the exposure range that specific attribute is printing opacity, in exposure process, this transparent figure is exposed on the chip in the M of region, making does not have figure in the exposure range of whole printing opacity, thereby makes transmission region chip failure.
4. the manufacture method that uses chip is aimed in test as claimed in claim 1, it is characterized in that, the judgement of described step 3 is specially: when the chip failing periphery chip in described region M is when Effective number of chips order is greater than 0 in a direction therein, in described direction, do not have skew, no person is offset.
CN201210460903.9A 2012-11-15 2012-11-15 Test alignment uses the preparation method of chip Active CN103811298B (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106571164A (en) * 2015-10-12 2017-04-19 爱思开海力士有限公司 Semiconductor device
CN109389598A (en) * 2018-10-25 2019-02-26 上海哥瑞利软件有限公司 A kind of continuous chip failing quantity statistics algorithm of efficient wafer
CN109957503A (en) * 2017-12-14 2019-07-02 长光华大基因测序设备（长春）有限公司 A kind of processing chip and its application for high-throughput gene sequencing equipment
CN110164789A (en) * 2019-06-05 2019-08-23 德淮半导体有限公司 Crystal round test approach and wafer tester
CN111146106A (en) * 2019-12-30 2020-05-12 上海华岭集成电路技术股份有限公司 Method for rapidly screening failure risk of chip
CN113625149A (en) * 2020-05-07 2021-11-09 美商矽成积体电路股份有限公司 Abnormal chip detection method and abnormal chip detection system

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1209643A (en) * 1997-08-04 1999-03-03 日本电气株式会社 Alignment method
CN1492285A (en) * 2002-10-24 2004-04-28 友达光电股份有限公司 Optical mask with alignment measurnig mark and its detecting method
JP2007103851A (en) * 2005-10-07 2007-04-19 Nec Electronics Corp Method of manufacturing semiconductor device and semiconductor wafer
CN101183119A (en) * 2006-11-13 2008-05-21 采钰科技股份有限公司 Manufacturing method of wafer level testing circuit board and structure thereof
US20090000995A1 (en) * 2007-06-29 2009-01-01 Hirokazu Yanai Good chip classifying method on wafer, and chip quality judging method, marking mechanism, and manufacturing method of semiconductor device using the good chip classifying method
JP2010056222A (en) * 2008-08-27 2010-03-11 Renesas Technology Corp Method of testing semiconductor chip and semiconductor wafer, and method of manufacturing semiconductor device
CN101750900A (en) * 2008-12-16 2010-06-23 上海华虹Nec电子有限公司 Method for determining photoetching procedure causing low yield rate in the unit of exposure area
CN101345220B (en) * 2004-11-11 2011-07-13 雅马哈株式会社 Semiconductor device, semiconductor wafer, chip size package, and methods of manufacturing and inspection therefor

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1209643A (en) * 1997-08-04 1999-03-03 日本电气株式会社 Alignment method
CN1492285A (en) * 2002-10-24 2004-04-28 友达光电股份有限公司 Optical mask with alignment measurnig mark and its detecting method
CN101345220B (en) * 2004-11-11 2011-07-13 雅马哈株式会社 Semiconductor device, semiconductor wafer, chip size package, and methods of manufacturing and inspection therefor
JP2007103851A (en) * 2005-10-07 2007-04-19 Nec Electronics Corp Method of manufacturing semiconductor device and semiconductor wafer
CN101183119A (en) * 2006-11-13 2008-05-21 采钰科技股份有限公司 Manufacturing method of wafer level testing circuit board and structure thereof
US20090000995A1 (en) * 2007-06-29 2009-01-01 Hirokazu Yanai Good chip classifying method on wafer, and chip quality judging method, marking mechanism, and manufacturing method of semiconductor device using the good chip classifying method
JP2010056222A (en) * 2008-08-27 2010-03-11 Renesas Technology Corp Method of testing semiconductor chip and semiconductor wafer, and method of manufacturing semiconductor device
CN101750900A (en) * 2008-12-16 2010-06-23 上海华虹Nec电子有限公司 Method for determining photoetching procedure causing low yield rate in the unit of exposure area

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106571164A (en) * 2015-10-12 2017-04-19 爱思开海力士有限公司 Semiconductor device
CN109957503A (en) * 2017-12-14 2019-07-02 长光华大基因测序设备（长春）有限公司 A kind of processing chip and its application for high-throughput gene sequencing equipment
CN109957503B (en) * 2017-12-14 2022-05-31 长春长光华大智造测序设备有限公司 Process chip for high-throughput gene sequencing equipment and application thereof
CN109389598A (en) * 2018-10-25 2019-02-26 上海哥瑞利软件有限公司 A kind of continuous chip failing quantity statistics algorithm of efficient wafer
CN109389598B (en) * 2018-10-25 2021-09-17 上海哥瑞利软件股份有限公司 Efficient statistical algorithm for number of chips with continuous failure of wafer
CN110164789A (en) * 2019-06-05 2019-08-23 德淮半导体有限公司 Crystal round test approach and wafer tester
CN111146106A (en) * 2019-12-30 2020-05-12 上海华岭集成电路技术股份有限公司 Method for rapidly screening failure risk of chip
CN113625149A (en) * 2020-05-07 2021-11-09 美商矽成积体电路股份有限公司 Abnormal chip detection method and abnormal chip detection system

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