CN109389598A - A kind of continuous chip failing quantity statistics algorithm of efficient wafer - Google Patents
A kind of continuous chip failing quantity statistics algorithm of efficient wafer Download PDFInfo
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- CN109389598A CN109389598A CN201811252916.0A CN201811252916A CN109389598A CN 109389598 A CN109389598 A CN 109389598A CN 201811252916 A CN201811252916 A CN 201811252916A CN 109389598 A CN109389598 A CN 109389598A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/0002—Inspection of images, e.g. flaw detection
- G06T7/0004—Industrial image inspection
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/10—Segmentation; Edge detection
- G06T7/13—Edge detection
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/30—Subject of image; Context of image processing
- G06T2207/30108—Industrial image inspection
- G06T2207/30141—Printed circuit board [PCB]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/30—Subject of image; Context of image processing
- G06T2207/30168—Image quality inspection
Abstract
The present invention provides a kind of continuous chip failing quantity statistics algorithm of efficient wafer, it include: step 1, initialize all coordinates, two, obtain the matrix A for being initialized as full 0, three, after testing a chip, matrix A corresponding position is arranged to 0 or 1, 1 indicates failure, if it is 8 chips around 1 operation this chip, four, one: 8 chip of situation is not in continuous chip failing queue, then the quantity of continuous chip failing is N+1 at this time, situation two: there is M a in continuous chip failing queue Q1 in chip, have N number of in Q2, then from Q1, a chip is respectively taken out in Q2 is denoted as Die1, Die2, then the quantity of continuous chip failing is V (Die1)+V (Die2)+1, situation three: M isolated, it is N number of in queue Q1, it is continuous at this time to lose The quantity for imitating chip is M+V (Die1)+1.The present invention can effectively improve monitoring and operating efficiency, improve the convenience of monitoring.
Description
Technical field
The present invention relates to a kind of efficient continuous chip failing quantity statistics algorithms of wafer, belong to chip field.
Background technique
In semiconductor CP test, with probe card to wafer test, probe is engaged test, on the one hand can be stayed on wafer
Knit stitch trace, one side probe card itself also have consume, no matter so considered from product quality, or from cost angle, it is all uncommon
Prestige is timely found the problem during the test, timely interrupt test, corrects problem, rather than is divided again after the completion of waiting test
Analysis.
Existing CP test equipment has continuous chip failing beyond setting maximum value warning function, but it can only detect spy
This mobile continuous a kind of situation of needle, and it is continuous to detect the chip failing of physics on wafer.Test equipment detects continuously
Chip failing exceeds maximum setting value alarm, counts again after alarm, but actually having kind of situation is the core tested after alarm
What piece still failed, that this failure quantity beyond maximum set value can not come out, in addition the report of test equipment
Police cannot store, it has not been convenient to the subsequent investigation of engineer and problem analysis.
Summary of the invention
The purpose of the present invention is to provide a kind of efficient continuous chip failing quantity statistics algorithms of wafer.
Present invention employs following technical solutions:
A kind of continuous chip failing quantity statistics algorithm of efficient wafer characterized by comprising
Step 1: initializing all coordinates according to the chip status figure of wafer, and this default value indicates OK with 0.
Step 2: 0,1 matrix of 1 distribution shifts squarely, 0 polishing of edge obtains an initialization by circular 0
For the matrix A of full 0,
Step 3: after test equipment tests a chip, according to coordinate by matrix A corresponding position be arranged to 0 or
1,1 indicate failure, if it is 1 carry out operation, 8 chips of the operation centered on currently testing chip,
Step 4: being divided into three kinds of situations:
Situation one: if 8 chips not in the continuous chip failing queue of caching, and have N number of 1, then continuous at this time
The quantity of chip failing is N+1, while 9 Gong Gezhong are originally that 1 chip is all arranged to N+1, and by N+1 chip
Coordinate and value are pressed into the same continuous chip failing queue,
Situation two: if there are M in 8 chips in continuous chip failing queue Q1, there is N number of (M in continuous queue Q2
+ N≤8), then
A chip is taken out from queue Q1, Q2 respectively, is denoted as Die1, Die2 respectively, then continuous chip failing at this time
Quantity be V (Die1)+V (Die2)+1, while Q1, all chips in Q2 queue are all arranged to V (Die1)+V
(Die2)+1, and by Q1, the coordinate and value of Q2 and current chip, which merge, is pressed into the same continuous chip failing queue,
M is isolated point in three: 8 chips of situation, N number of in queue Q1, then combines situation 1, the algorithm of situation 2,
The quantity of continuous chip failing is M+V (Die1)+1 at this time, while all chips in Q1 queue are all arranged to M+V
(Die1)+1, and will be in M+1 chip indentation queue Q1.
Advantageous effect of the invention
The continuous chip failing quantity statistics algorithm of efficient wafer of the invention provides the condition of monitoring in existing system
Under, by this remodeling method, the efficiency of monitoring and operation can be effectively improved, improves the convenience of monitoring.
1. algorithm can detect chip up and down and upper left, upper right, lower-left, the continuous mistake in eight directions of bottom right
Effect.
2. can detect that continuous edge fails, in this way the mistake of energy timely correction Map Shift.
3. the continuous coordinate of chip failing can be stored, convenient intuitive the problem of reappearing wafer region.
4. can count all continuous, rather than just continuous in setting maximum range.
5. algorithm is not influenced by probe actual test track.
6. in real time, calculation amount is few, effectively.
Detailed description of the invention
Fig. 1 is the schematic diagram that conventional method is able to detect that continuous chip failing；
Fig. 2 is the schematic diagram that method of the invention is able to detect that continuous chip failing；
Fig. 3 is algorithm flow chart of the invention；
Fig. 4 is the schematic diagram of situation one in method of the invention；
Fig. 5 is another schematic diagram of situation one in method of the invention；
Fig. 6 is the schematic diagram of situation two in method of the invention；
Fig. 7 is another schematic diagram of situation two in method of the invention；
Fig. 8 is the schematic diagram of situation three in method of the invention；
Fig. 9 is another schematic diagram of situation three in method of the invention.
Specific embodiment
Illustrate a specific embodiment of the invention below in conjunction with attached drawing.
The continuous chip failing quantity statistics algorithm of efficient wafer of the invention, as shown in figure 3, including the following steps:
Step 1: initialize all coordinate according to the chip status figure (Goldmap) of wafer, and with 0 this default
Value indicates OK；
Step 2: 0,1 matrix of 1 distribution shifts squarely, 0 polishing of edge is obtained here at the beginning of one by circular 0
Beginning turns to the matrix (A) of full 0；
Step 3: matrix A corresponding position is arranged to 0 or 1 according to coordinate after test equipment tests a chip
(1 indicates failure).Operation is carried out if it is 1, operation is 8 chips centered on currently testing chip.
Step 4: being respectively comprising three kinds of situations:
Situation one, it is continuous at this time if 8 chips not in the continuous chip failing queue of caching and have N number of one
The quantity of chip failing is N+1, while 9 Gong Gezhong are originally that 1 chip is all arranged to N+1, and by N+1 chip
Coordinate and value are pressed into the same continuous chip failing queue.
Situation two has N number of in continuous chip failing team if having M in 8 chips in continuous chip failing queue Q1
It arranges in Q2 (M+N≤8), then:
A chip (Die1, Die2) is taken out from queue Q1, Q2 respectively, then the quantity of continuous chip failing at this time is
V(Die1)+V(Die2)+1.Simultaneously Q1, all chips in Q2 queue are all arranged to V (Die1)+V (Die2)+1, and
By Q1, the coordinate and value of Q2 and current chip, which merge, is pressed into the same continuous chip failing queue.
Situation three, M are isolated points in 8 chips, N number of in queue Q1, then combine situation 1, the algorithm of situation 2,
The quantity of continuous chip failing is M+V (Die1)+1 at this time.All chips in Q1 queue are all arranged to M+V simultaneously
(Die1)+1, and will be in M+1 chip indentation queue Q1.
Algorithm diagram, for Fig. 4 into Fig. 9, the position with white box indicates the chip that current test is completed.
Situation one is as shown in Figure 4 and Figure 5, without continuous Die, only 2 isolated Die around current Die.So N+
1=2+1=3；
As shown in Figure 6 and Figure 7, the Die around current Die is continuous to situation two, and 2 Die are in the continuous team of Q1
In column, so V (Die1)+V (Die2)+1=3+0+1=4；
Situation three as shown in Figure 8 and Figure 9, there are two chip failing around current chip, one of them be it is isolated, in addition
One in continuous queue Q1, so M+V (Die1)+1=1+4+1=6.
As shown in Figure 1, being the continuous chip failing that can be identified using existing test equipment in white box.
As shown in Fig. 2, being the continuous chip failing that can be identified using method of the invention in white box.
Wherein, white square indicates chip failing in Fig. 1 and Fig. 2.
It can be seen that method of the invention can identify more and larger range of continuous chip failing.
Claims (1)
1. a kind of continuous chip failing quantity statistics algorithm of efficient wafer characterized by comprising
Step 1: all coordinates are initialized according to the chip status figure of wafer, and this default value indicates OK with 0,
Step 2: 0,1 matrix of 1 distribution shifts squarely, 0 polishing of edge obtains one and is initialized as full 0 by circular 0
Matrix A,
Step 3: matrix A corresponding position is arranged to 0 or 1,1 table according to coordinate after test equipment tests a chip
Show failure, carries out operation if it is 1,8 chips of the operation centered on currently testing chip,
Step 4: being divided into three kinds of situations:
Situation one: if 8 chips not in the continuous chip failing queue of caching, and have N number of 1, then continuous failure at this time
The quantity of chip is N+1, while 9 Gong Gezhong are originally that 1 chip is all arranged to N+1, and by the coordinate of N+1 chip
It is pressed into the same continuous chip failing queue with value,
Situation two: if there are M in 8 chips in continuous chip failing queue Q1, have N number of in continuous chip failing queue Q2
In, M+N≤8, then
A chip is taken out from queue Q1, Q2 respectively, is denoted as Die1, Die2 respectively, then the number of continuous chip failing at this time
Amount is V (Die1)+V (Die2)+1, while Q1, and all chips in Q2 queue are all arranged to V (Die1)+V (Die2)+1,
And by Q1, the coordinate and value of Q2 and current chip, which merge, is pressed into the same continuous chip failing queue,
M is isolated point in three: 8 chips of situation, N number of in queue Q1, then combines situation 1, the algorithm of situation 2, at this time
The quantity of continuous chip failing is M+V (Die1)+1, at the same by all chips in Q1 queue be all arranged to M+V (Die1)+
1, and will be in M+1 chip indentation queue Q1.
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| CN201811252916.0A CN109389598B (en) | 2018-10-25 | 2018-10-25 | Efficient statistical algorithm for number of chips with continuous failure of wafer |
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| CN201811252916.0A CN109389598B (en) | 2018-10-25 | 2018-10-25 | Efficient statistical algorithm for number of chips with continuous failure of wafer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111146106A (en) * | 2019-12-30 | 2020-05-12 | 上海华岭集成电路技术股份有限公司 | Method for rapidly screening failure risk of chip |
| CN111308318A (en) * | 2019-12-30 | 2020-06-19 | 上海华岭集成电路技术股份有限公司 | Semiconductor chip test data processing method |
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| JPH0980122A (en) * | 1995-09-11 | 1997-03-28 | Advantest Corp | Failure analysis memory device of semiconductor testing device |
| US20050102591A1 (en) * | 2003-11-07 | 2005-05-12 | Hiroshi Matsushita | Failure detection system, failure detection method, and computer program product |
| CN1953102A (en) * | 2005-10-21 | 2007-04-25 | 国际商业机器公司 | Test data reporting and analyzing using data array and related data analysis |
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| CN203434131U (en) * | 2013-07-29 | 2014-02-12 | 中芯国际集成电路制造(北京)有限公司 | Chip positioning module |
| CN103811298A (en) * | 2012-11-15 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for test alignment chip |
| CN108519550A (en) * | 2018-03-28 | 2018-09-11 | 上海华岭集成电路技术股份有限公司 | IC wafers test optimization method |
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2018
- 2018-10-25 CN CN201811252916.0A patent/CN109389598B/en active Active
Patent Citations (7)
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|---|---|---|---|---|
| JPH0980122A (en) * | 1995-09-11 | 1997-03-28 | Advantest Corp | Failure analysis memory device of semiconductor testing device |
| US20050102591A1 (en) * | 2003-11-07 | 2005-05-12 | Hiroshi Matsushita | Failure detection system, failure detection method, and computer program product |
| CN1953102A (en) * | 2005-10-21 | 2007-04-25 | 国际商业机器公司 | Test data reporting and analyzing using data array and related data analysis |
| CN101290901A (en) * | 2007-04-17 | 2008-10-22 | 中芯国际集成电路制造(上海)有限公司 | Wafer quality analysis method and device |
| CN103811298A (en) * | 2012-11-15 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for test alignment chip |
| CN203434131U (en) * | 2013-07-29 | 2014-02-12 | 中芯国际集成电路制造(北京)有限公司 | Chip positioning module |
| CN108519550A (en) * | 2018-03-28 | 2018-09-11 | 上海华岭集成电路技术股份有限公司 | IC wafers test optimization method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111146106A (en) * | 2019-12-30 | 2020-05-12 | 上海华岭集成电路技术股份有限公司 | Method for rapidly screening failure risk of chip |
| CN111308318A (en) * | 2019-12-30 | 2020-06-19 | 上海华岭集成电路技术股份有限公司 | Semiconductor chip test data processing method |
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