JPH0980122A - Failure analysis memory device of semiconductor testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device for speedily counting the number of faulty bits in a failure analysis memory by paying special attention to the fact that the frequency of failure is extremely lower than a total memory capacity. SOLUTION: In addition to a memory A76 for storing the failure information of a total address space, a failure storage means memory B77 is provided for dividing the total address space of MUT for each address block unit in parallel and for performing OR addition of the failure information in the address and storing the information. A failure counting means is used to count the number of failures in the address space of the memory A76 corresponding to the address block when failure data exist by successively reading data in the memory B77 by providing an address selection means for laying out the failure storage means to the address of a specific address block unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory test apparatus for fail-counting the number of defective bits in a failure analysis memory in a short time.

[0002]

2. Description of the Related Art In testing and evaluating a semiconductor memory, it is important to have information on how many defective parts are present in a memory under test (hereinafter referred to as MUT). For example, in a wafer test, each chip on a wafer is tested, and the number of defective bits determines the subsequent processing. That is, if the number of defects is too large, the repair process cannot repair the MUT, so that the MUT is determined to be defective. If the number of defects is within a certain range, the repair bit may be repaired. .

In the MUT test, a write / read test of the entire address space is performed, and the result is stored and saved in a memory location for failure analysis corresponding to the MUT address. After that, fail counting is performed, and the number of defective bits in this defective analysis memory is counted to obtain the number of defective bits.
That is, it is necessary to read data in all address areas and count defective bits with a counter. Therefore, as the address area increases, the required counting time increases proportionally.

FIG. 10 shows a circuit configuration of a conventional failure analysis memory section related to the present invention. The configuration is the controller 72
, An address pointer 74, MUX1 and MUX2,
It is composed of a memory A76 and a fail counter 78.

The MUX 1 is a selector for selecting an address signal from the pattern generator 90 or an address signal from the address pointer 74. The address signal from the pattern generator 90 is selected during the MUT test, and the address signal from the address pointer 74 is selected during the analysis. These addresses generally have two dimensions of X and Y or three dimensions of X, Y and Z and each have several bits (for example, X0 to X7, Y0 to Y7, Z0 to Z7). MU
X2 is a selector that selects the address allocation to be applied so that the memory A76 has the same address space as the MUT that is the device under test. For example, when the MUT has an address bit number of 8 bits (address is 0 to 2
55), X0-3 and Y0-3 are allocated as in the example shown in the address allocation of the memory A76 in FIG.

The memory A76 is a memory having a capacity equal to or larger than that of the MUT and stores fail information of test results. The address pointer 74 supplies an address to the memory A76, and generates an address for fail counting by the fail counter 78, and the CPU 8
0 is for writing / reading memory data, and can generate an address having the same number of bits as the address generated by the pattern generator 90 (for example, X0 to X0).
X7, Y0 to Y7, Z0 to Z7). The controller 72 is
Controls the order of address generation during fail counting. If the data read from the memory A76 is "1", the fail counter 78 counts up and counts the number of fails.

FIG. 2 shows an example of fail storage when the number of address bits of the MUT is 8 bits. In this figure, the X address is 4 bits and the Y address is 4 bits. The fail counting procedure in this case operates like the flowchart shown in FIG. An example of the X, Y address generation order at this time is shown in the XY address generation order diagram of FIG. First, both X and Y addresses are set to "0". Next, X
Adds 1 to the address. When the X address reaches the last "F", the Y address is incremented by 1, and at the same time, the X address is returned to "0". This is repeated until both the X and Y addresses reach the final "F".

[0008]

As described above, the number of fails in the memory A76 must be read by the fail counter 78 to read all the data in all the address areas of the memory A76. There is a drawback that the fail counting time is proportional to the above, and in a recent large capacity memory, this fail counting takes a lot of time, which has become a problem of a device test throughput lowering factor. Therefore, the problem to be solved by the present invention is to focus on the fact that the number of fail occurrences is significantly smaller than the total memory capacity, and to count the number of defective bits in the failure analysis memory in a short time. The purpose is to realize a counting device.

[0009]

In order to solve the above-mentioned problems, in the configuration of the present invention, during the MUT test, the entire address space of the MUT is addressed in parallel with the memory A76 storing the fail information of all the addresses of the MUT. Fail storage means (memory B77) for compressing the fail information for each partition unit, that is, OR-adding the fail in the partition and storing it is provided, and receives the address signals smaller than the number of address signals given to the memory A76, and stores the fail Means (Memory B7
7) is provided with an address selection means (MUX3) which is arbitrarily assigned and supplied as an address signal for determining an address division unit, and a memory B which is a fail storage means.
There is a configuration means for providing fail counting means for sequentially reading 77 and scanning the address space of the memory A76 corresponding to this address partition when fail data for each address partition is present and counting the fail number. As a result, a defective bit number counting device capable of counting the defective bit number of the defect analysis memory A76 in a short time is realized.

During the MUT test, the memory A76 for storing the fail information of all addresses of the MUT is parallel to the memory A76.
A fail storage means memory B77 for compressing fail information in the entire address space of the UT for each address partition unit, that is, ORing the failures in the partition and storing the fail information is provided, and the memory A7 is provided.
An address signal less than the number of address signals given to 6 is received and supplied to the fail storage means (memory B77) as an address signal for determining an address partition unit,
When the memory B77, which is the fail storage means, is sequentially read and there is fail data in address block units,
There is a configuration means for providing a fail counting means for scanning the address space of the memory A76 corresponding to this address section and counting the number of failures.

The fail counting means receives compressed fail information from the memory B77, which is the fail storing means, at the time of fail counting, and if there is no fail, jumps within the address partition unit to perform the fail operation. The controller 7 is a counting control means that shortens the counting time of
The fail count added to 2 is realized.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to examples.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, the entire address space is divided into sections,
A fail storage memory B is additionally provided to compress and store the presence / absence of a fail for each partition. When counting fail,
Check for the presence of compression fail information for each partition,
First, when there is no fail, the address is skipped over to check the next partition unit, and when there is a second fail, the address space area corresponding to this partition is scanned and accessed to count the number of fails. As a means. That is, this is a means for reducing the counting time in units of address blocks in which no failure occurs.

FIG. 1 shows the configuration of the failure analysis memory unit of the present invention. The configuration is such that a MUX 3, a memory B77, and a path from the memory B77 to the controller 72 are added to the conventional configuration.

In addition to the conventional fail counting means, the controller 72 has a function of receiving fail information from the memory B77 at the time of fail counting and jumping to the address of the next partition unit when there is no fail. are doing.

The MUX 3 is a selector which receives the address signal from the MUX 1 and selects a size of a desired block address, that is, an address signal to be divided into address block units and supplies it to the memory B 77. In the example of the address allocation shown in FIG. 4, 8-bit address signals (Y3 to Y
0, X3 to X0) and a 4-bit address signal (Y3, Y2, X3, X2) is selected.

The memory B77 uses the entire address space as a memory for storing the presence / absence of a failure in the address area for each partition unit, and fetches MUT defect information by address compression (OR addition). Therefore, this memory capacity may be smaller than the memory A76.

FIG. 3 shows an example of address compression storage in the memory B77. In this example, the memory B77 compresses the address space of the memory A76 to 1/16. That is, the fail information of the block address area for 16 addresses of the memory A76 is OR-added and stored in one address of the memory B77. That is, if there is a failure even at one place in the shaded portion of the memory A76 in FIG. 3, "1" is written in the shaded portion of the memory B77. As a result, whether or not there is a failure even once in the compressed address space, which is a partition unit, is stored. That is, at the time of the MUT test, the fail information after OR-adding the previously stored data and the current fail data is stored and saved.

FIG. 4 shows the state of fail storage in the memory A76 and the added memory B77 in the case where the number of address bits of the MUT is 8 bits in comparison with FIG. 2 described in the prior art. The address allocation shown in this figure indicates addresses at the time of MUT test. On the other hand, the address allocation shown in FIG. 9 indicates addresses at the time of fail counting. FIG. 6 is a flowchart of the fail counting procedure, and FIG. 8 shows the address generation order at this time.

Next, the fail counting procedure will be described with reference to FIGS. 6 and 9. Set the address counter to (X, Y,
Z) = (0,0,0) is initialized and the fail counter 78 is cleared. First, the fail data at the address "0" of the memory B77 stored in the fail compression storage is read. Since the fail data of this address is "0",
The fail count is not performed, and the controller 72 increments the Z address by +1 in order to perform the address skipping operation, and again reads the fail data at the next address "1" of the memory B77. Since the fail data of the address "1" is "1", the number of fails in the address of the memory A corresponding to this section is counted. That is, the controller 72 sequentially changes the address (X, Y) from (0,0) to (3,3) to read the fail data in the memory A76, and the fail counter 78 for the number of times of "1" is incremented by +1. While counting. After counting this section, the address (X,
Y) is returned to (0,0), the Z address is incremented by 1, the fail data at the next address "1" on the memory B77 side is read again, the same operation is repeated, and the Z address is the last "F". Until it becomes.

According to this method, the memory A76 is divided into several blocks, and if there is a fail in the block address area, the memory space in the fail block is scanned to perform fail counting, and If there is no fail in the block, the block is skipped, so there is no need to scan the memory space in the pass block (block without fail). As described above, it is possible to omit the unnecessary scan of the memory space by using the memory B77, and the fail count time can be shortened in proportion to the omission of the scan.

In the fail distribution example of FIG. 4, the memory B77
Of these 16 blocks, 6 blocks are examples of fail blocks. Since only this block needs to be scanned to perform fail counting, the time can be shortened to 6/16 in this case. Further, even if the memory capacity is increased, the scan is performed in fail block units, so that the counting time does not increase in proportion to the memory capacity. In the actual memory test, the number of defective bits is less than the extent that the defect can be relieved.
The ratio of fail blocks to all blocks is very small. From this fact, 1 /
It can be reduced to counting times of a few to a few hundreds.

(Application example) In the above description of the embodiment, the memory B77 is divided into 16 blocks in which the same address is compressed in the X direction and the Y direction, but this block division is arbitrary by the MUX 3. Since the addresses can be assigned, the compression ratio in the XY directions can be changed, or the addresses can be compressed only in one direction. As a result, according to the tendency of the fail distribution of the MUT and the row / column chip structure of the MUT internal circuit, even if the address to be applied to the memory B77 is selected so as to divide the block so that the fail count becomes more efficient. good.

In the above description of the embodiment, the MUX3 is used as an example of the address compression means for arbitrarily allocating an address to be given to the memory B77.
3 may be omitted, and a fixed address signal in which a part of the address signal from the MUX1 or MUX2 (for example, several bits of the lower address signal) is simply deleted may be directly connected to the memory B77. .

[0025]

Since the present invention is configured as described above, it has the following effects. The memory B77 has a memory configuration in which the entire address space is divided into addresses for each partition unit, and stores a fail in this address partition by OR-adding it during a memory test. As a result, there is an operation of making the fail presence / absence information in this address division unit. Memory B7 during fail counting
The fail presence / absence information of 7 is sequentially read, and if there is fail data, the memory A corresponding to this address section
It is a fail counting means for counting the number of fail data in the address space on the 76 side. That is, at the time of fail counting,
If this fail data is read and the data in this partition is not fail, it is not necessary to access the address space in this partition, and the effect of shortening the access time for this is obtained, and the fail count time is significantly increased. Can be realized, fail counting can be performed in a short time even with a large capacity memory device, a decrease in throughput of the MUT test can be prevented, and throughput can be improved. The MUX 3 selects an address to be applied to the memory B77 and gives an address signal for a desired partition unit to divide and allocate the address space into the desired partition unit.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a failure analysis memory unit according to the present invention.

FIG. 2 shows that the MUT has 8 address bits (X0 to X0).
3, Y0 to 3) are address allocation and fail storage state diagrams.

FIG. 3 shows 16 address spaces of a memory A76 of the present invention.
FIG. 27 is a fail storage state diagram of the memory B77 when the data is compressed to one-half.

FIG. 4 is a diagram showing a memory A76 and a memory B7 corresponding to the memory A76 when the MUT has 8 address bits;
7 is a diagram showing a fail storage state in FIG.

FIG. 5 is a flowchart illustrating a conventional fail counting procedure.

FIG. 6 is a flowchart illustrating a fail counting procedure according to the present invention.

FIG. 7 is a diagram showing a conventional XY address generation sequence.

FIG. 8 is a diagram showing an XYZ address generation sequence of the present invention.

FIG. 9 is a diagram showing address allocation at the time of fail counting according to the present invention.

FIG. 10 is a circuit configuration diagram of a conventional failure analysis memory unit.

[Explanation of symbols]

 72 Controller 74 Address Pointer 76 Memory A 77 Memory B 78 Fail Counter 80 CPU 90 Pattern Generator

Claims (3)

[Claims] 1. A memory A for storing fail information of all addresses of a MUT in counting the number of fails of a memory under test (MUT).
In parallel with this, a fail storage means for compressing and storing fail information in the entire address space of the MUT for each address partition unit is provided, and an address signal less than the number of address signals given to the memory A is received, and is sent to the fail storage means. Address selection means MUX (3) is provided as an address signal for allocation, and the fail storage means is sequentially read out, and if there is fail data in address block units, the address of the memory A corresponding to this address block A failure analysis memory device for a semiconductor testing device, characterized by comprising a fail counting means for scanning a space to count the number of failures. 2. A memory A for storing fail information of all addresses of the MUT in fail counting of a memory under test.
In parallel with this, a fail storage means for compressing and storing fail information in the entire address space of the MUT for each address partition unit is provided, and an address signal less than the number of address signals given to the memory A is received, and is sent to the fail storage means. If the fail storage means is sequentially read out and there is fail data in address block units, a fail counting means for scanning the address space of the memory A corresponding to this address block to count the number of fails is provided. A failure analysis memory device for a semiconductor testing device, which is provided with the above. 3. The fail counting means receives compressed fail information from the fail storing means at the time of fail counting, and if there is no fail, jumps within the address partition unit to shorten the fail counting time. 3. The failure analysis memory device for a semiconductor testing device according to claim 1, wherein the counting control means is provided in the controller (72).