CN105808795A - FPGA chip global placement optimization method based on temporal constraint - Google Patents

Abstract

The invention relates to an FPGA chip global placement optimization method based on temporal constraint. The FPGA chip global placement optimization method comprises that according to the input/output IO placement netlist after logic synthesis, the initial line length of all paths in the global placement is obtained; based on the temporal constraint condition input by the user, the time margin slack of all paths is determined through static timing analysis (STA); according to the time margin, a key path is determined in all paths; according to the time margin of the key path, the net weight is updated; based on the updated net weight, the global placement is dynamically adjusted, the line length after the path is optimized is obtained; and according to the optimized line length, the global placement is optimized.

Description

Fpga chip global wiring optimization method based on temporal constraint

Technical field

The present invention relates to placement-and-routing's technical field of field programmable gate array (FieldProgrammableGateArray, FPGA) chip, particularly a kind of fpga chip global wiring optimization method based on temporal constraint.

Background technology

FPGA is the logical device being made up of many logical blocks, has abundant hardware resource, powerful parallel processing capability and flexible reconfigurable ability, obtains increasing extensive use in a lot of field such as data process, communication, network.

When doing logic synthesis and placement-and-routing to FPGA, it is necessary to set the constraint of sequential in the tool.Generally, in FPGA design instrument, all FPGA includes 4 kinds of paths: from input port to depositor, from depositor to depositor, from depositor to output, from the pure combination logic being input to output.Generally, user needs these several paths are retrained respectively, can obtain optimized result thereby through design tool.

How by design tool, according to the temporal constraint that user sets, obtain optimized layout result, be fpga chip global wiring optimization method problem to be solved provided by the invention.

Summary of the invention

The invention provides a kind of fpga chip global wiring optimization method based on temporal constraint, it is possible to based on the requirements of timing constraints of user, the global wiring of user's design is optimized so that the layout result of user's design disclosure satisfy that the requirement of temporal constraint.

Embodiments provide a kind of fpga chip global wiring optimization method based on temporal constraint, including:

According to the netlist of input and output IO layout after logic synthesis, obtain the initial line length of All Paths in global wiring；

Based on the Timing Constraints of user's input, determined the time margin slack in all paths by static timing analysis STA；

According to described time margin, in all paths, determine critical path；

Time margin according to described critical path, updates gauze weight；

Based on the gauze weight after updating, dynamically adjust global wiring, obtain the line length after path optimization；

Global wiring optimization is carried out according to the line length after optimizing.

Preferably, described according to described time margin, in all paths, determine that critical path specifically includes:

When static timing analysis determines the described time margin of first path less than predetermined threshold value, it is determined that described first path is critical path.

It is further preferred that described predetermined threshold value is not less than 0.

Preferably, the described time margin according to described critical path, update gauze weight particularly as follows:

The size of the time margin according to described critical path, updates gauze weight；

Wherein, the time margin of described critical path is more little, and the gauze weight after renewal is more high.

Preferably, after carrying out global wiring optimization according to the line length after optimizing, described method also includes:

Record the number of times carrying out global wiring optimization according to the line length after optimizing；

Judge described to carry out the optimization the number of times whether number of times of global wiring optimization reaches to preset according to the line length after optimizing；

Without reaching, then continue the Timing Constraints based on user's input, determine the time margin slack in all paths in the global wiring after optimization by static timing analysis STA；

According to described time margin, in all paths, determine critical path；

Time margin according to described critical path, updates gauze weight；

Based on the gauze weight after updating, dynamically adjust global wiring, obtain the line length after path optimization；

Global wiring optimization is again carried out according to the line length after optimizing.

Preferably, after carrying out global wiring optimization according to the line length after optimizing, described method also includes:

Based on the Timing Constraints of user's input, determine the time margin slack in all paths in the global wiring after optimization by static timing analysis STA；

According to described time margin, determine whether to there is also critical path in all paths；

If there is also critical path, then the time margin according to described critical path, update gauze weight；

Based on the gauze weight after updating, dynamically adjust global wiring, obtain the line length after path optimization；

Global wiring optimization is again carried out according to the line length after optimizing.

Preferably, after described static timing analysis, described method also includes:

Generation static timing analysis is reported, described Timing Constraints is adjusted according to described static timing analysis report in order to described user.

The fpga chip global wiring optimization method based on temporal constraint that the embodiment of the present invention provides, the time margin in all paths is determined by static timing analysis, and then determine critical path in all paths, by updating the gauze weight of critical path, dynamically adjust global wiring so that the layout result of user's design disclosure satisfy that the requirement of temporal constraint.Finally realize FPGA layout optimization, and then improve and final be routed to power.

Accompanying drawing explanation

The fpga chip global wiring optimization method based on temporal constraint that Fig. 1 provides for the embodiment of the present invention；

The schematic diagram of a kind of fpga chip Clock Net that Fig. 2 provides for the embodiment of the present invention；

In a kind of fpga chip that Fig. 3 provides for inventive embodiments, the sequential in path is with the change curve of user's temporal constraint.

Detailed description of the invention

Below by drawings and Examples, technical scheme is described in further detail.

The fpga chip global wiring optimization method flow chart based on temporal constraint that Fig. 1 provides for the embodiment of the present invention, as it can be seen, the method comprises the steps:

Step 110, the netlist according to input and output after logic synthesis (IO) layout, obtain the initial line length of All Paths in global wiring；

Concrete, utilize synthesis tool that the design of user is inputted and carry out logic synthesis (logicsynthesis), by logic synthesis, the hardware description language (VHDL or verilog) that user designs input is transformed into the other circuit connection netlist of logic gate level.

According to netlist, it is laid out, obtains an initial global wiring, wherein also include the initial length in each Clock Net path.When initial layout, the weight of each Clock Net is all defaulted as 1.After global wiring, look-up table and depositor between the logical block (LogicElement, LE) within fpga chip, within logical block allow for there is overlap.

Step 120, based on the Timing Constraints of user's input, determines the time margin (slack) in all paths by static timing analysis (STA)；

Concrete, static timing analysis is a kind of important logic verification method, by postpone comprehensive of path computing and compare the delay relative to predefined clock, its object is to find out hiding sequence problem, according to Time-Series analysis result optimizing logic or constraints, so that design reaches sequential Guan Bi.

The temporal constraint of the present embodiment refers to constraintss such as specifying the frequency/period of signal, dutycycle, time delay in static timing analysis tool.

After static timing analysis, static timing analysis report can be exported, including the slack in all paths；Wherein, in static timing analysis report, positive slack represents that the sequential in path meets constraint requirements, and negative slack represents that the sequential in path is unsatisfactory for constraint requirements.

Consider the inexactness of global wiring stage sequential, set a predetermined threshold value more than 0 in the present embodiment.When slack is more than predetermined threshold value, represent that the sequential in this path meets constraint requirements；When slack is less than predetermined threshold value, represent that the sequential in this path is unsatisfactory for constraint requirements.

In one example, the representative value of predetermined threshold value can be 1000ps.

Step 130, according to described time margin, determines critical path in all paths；

Concrete, by slack less than predetermined threshold value, namely sequential is unsatisfactory for the path of constraint requirements, it is determined that for critical path.

Step 140, the time margin according to described critical path, update gauze weight；

Concrete, in static timing analysis is reported, each critical path has the parameter of corresponding time margin, the gauze weight of critical path is improved, and time margin is more little, and the increase ratio of gauze weight is more big.

Step 150, based on the gauze weight after updating, dynamically adjusts global wiring, obtains the line length after path optimization；

Concrete, determine the order of optimization process according to the weight of every gauze in the gauze of described fpga chip, the gauze that weight is big is preferentially optimized process, obtains the line length of the gauze of the fpga chip after optimization process.

Because the weight of ordinary clock gauze has adjusted in abovementioned steps, having higher weight than data gauze, therefore when optimization process, ordinary clock gauze is preferentially optimized process, obtains the line length of the ordinary clock gauze after optimization process.

In order to ensure not increase wiring congestion optimizing after line length, therefore it is required that for each Clock Net before optimization after length change not can exceed that certain scope.

The concrete processing method of path optimization can adopt the computational methods of Matrix Solving, specifically can illustrate in following detailed example, repeat no more herein.

Step 160, carries out global wiring optimization according to the line length after optimizing.

Said process can be the process of a continuous iteration, and each layout iteration timing optimization updates weight once.

Further, iterative process can be limited by setting iterations: such as, after carrying out global wiring optimization according to the line length after optimizing every time, and the number of times of record optimization layout, it is judged that whether this number of times reaches the optimization number of times preset.Without reaching the optimization number of times preset, then the basis of global wiring after optimization repeats the step of above-mentioned steps 120-step 160, until it reaches till default optimization number of times.The global wiring optimizing number of times acquisition being up to preset is as final layout result.

Further, iterative process can also is that and is set as that All Paths all meets till Timing Constraints, and this process includes:

Based on the Timing Constraints of user's input, determine the time margin slack in all paths in the global wiring after optimization by static timing analysis STA；

According to described time margin, determine whether to there is also critical path in all paths；

If there is also critical path, then the time margin according to described critical path, update gauze weight；

Based on the gauze weight after updating, dynamically adjust global wiring, obtain the line length after path optimization；

Global wiring optimization is again carried out according to the line length after optimizing.

Additionally, the static timing analysis report generated after static timing analysis, it is available for user and according to static timing analysis report, Timing Constraints is adjusted.

When user changes the constraints of static timing constraint, the weighted value of corresponding gauze also adjusts therewith accordingly so that the optimization of global wiring also adjusts therewith, thus quickly responding and meeting user's timing requirements.

The fpga chip global wiring optimization method based on temporal constraint that the embodiment of the present invention provides, the time margin in all paths is determined by static timing analysis, and then determine critical path in all paths, by updating the gauze weight of critical path, dynamically adjust global wiring so that the layout result of user's design disclosure satisfy that the requirement of temporal constraint.Finally realize FPGA layout optimization, and then improve and final be routed to power.

Below with concrete example, the method that the above embodiment of the present invention is provided is described in detail.

As in figure 2 it is shown, in this example, to have two ports, the structure of two unit and three Clock Nets is that example illustrates to the schematic diagram of a kind of fpga chip Clock Net.Wherein unit 1 is depositor 1, and unit 2 is depositor 2.Three Clock Net respectively port 1 to depositors 1, depositor 1 to depositor 2 and these three Clock Nets 1,2,3 of depositor 2 to port 2；The length of its correspondence is (x1-x0) respectively, (x2-x1), (x3-x2).Wherein x0 is the coordinate position of port 1, and x1 is the unit 1 i.e. coordinate position of depositor 1, and x2 is the unit 2 i.e. coordinate position of depositor 2, and x3 is the coordinate position of port 2.

In this example, the weight of initial each Clock Net is all 1；Two ports coordinate position x0=100, x3=200, it is assumed that port 1, depositor 1, depositor 2, port 2 are all in same level position, and namely y-coordinate position does not change.

According to polynomial matrix solution formula:

$\min \mathrm{\φ}=\underset{n\∈N}{\mathrm{\Σ}}{L}_n{W}_n=\underset{n\∈N}{\mathrm{\Σ}}{W}_n({(x_i-x_j)}^2+{(y_i-y_j)}^2)$ (formula 1)

$\frac{\∂\mathrm{\φ}}{\∂x_i}=0,\frac{\∂\mathrm{\φ}}{\∂y_i}=0;$ (formula 2,3)

φ is secondary line length weighting, and n is the radical of gauze, and N is positive integer, and L is the length of single line net, and W is gauze weight, (x_i, y_i), (x_j, y_j) coordinate of respectively two end points of single line net.

Data according to this example are calculated:

MinCost'=(x₁-100)²+(x₁-x₂)²+(x₂-200)²(formula 4)

$\frac{\∂}{\∂x_1}\mathrm{Cost}=2\×(x_1-x_2)+2\×(x_1-100),\frac{\∂}{\∂x_2}\mathrm{Cost}=2\×(x_1-x_2)+2\×(x_1-100)$ (formula 5,6)

Matrix Solving is carried out: AX+B=0 (formula 7) according to above formula

Wherein A is matrix, and B is vector.

$\left[\begin{array}{cc}2& -1\\ -1& 2\end{array}\right]\left[\begin{array}{c}{x}_1\\ x_2\end{array}\right]+\left[\begin{array}{c}-100\\ -200\end{array}\right]=0$ (formula 8)

Obtain x₁=400/3, x₂=500/3, unit is nanometer.

It is to say, before layout optimization, the line length between the position of the initial position distance depositor 1 of depositor 2 is x₂-x₁=33.33nm.

According to the method that the above embodiment of the present invention provides, it is assumed that Clock Net 2 is critical path, and its slack is less than predetermined threshold value, it is necessary to carry out weight renewal and make layout optimization, so that the slack of this critical path meets timing requirements.Therefore the weight of the Clock Net between depositor 1 to depositor 2 is risen to original 1.2 times, Clock Net is optimized.

MinCost'=(x₁'-100)²+1.2×(x₁'-x₂')²+(x₂'-200)²(formula 9)

$\frac{\∂}{\∂{x_1}^{\′}}\mathrm{Cost}=2.4\×({x_1}^{\′}-{x_2}^{\′})+2\×({x_1}^{\′}-100)$ (formula 10)

$\frac{\∂}{\∂{x_2}^{\′}}\mathrm{Cost}=2.4\×({x_1}^{\′}-{x_2}^{\′})+2\×({x_2}^{\′}-100)$ (formula 11)

Matrix Solving is carried out: AX+B=0 (formula 7) according to above formula

Wherein A is matrix, and B is vector.

$\left[\begin{array}{cc}2.4& -1\\ -1& 2.4\end{array}\right]\left[\begin{array}{c}{x_1}^{\′}\\ {x_2}^{\′}\end{array}\right]+\left[\begin{array}{c}-100\\ -200\end{array}\right]=0$ (formula 12)

Obtain x₁ ^‘=875/8, x₂ ^’=1125/8, unit is nanometer.

It is to say, after layout optimization, the line length between the position of the positional distance depositor 2 of depositor 2 is x₂ ^‘-x₁ ^’=31.25nm.

It follows that after the optimization, near 2.08nm before the position ratio optimization of the positional distance depositor 1 of depositor 2, the delay on this path can reduce accordingly, and namely this critical path obtains optimization.

In table 1 below, give according to user's temporal constraint be laid out optimize after static timing analysis report.

Sequence number	User temporal constraint sdc (MHZ)	Static timing analysis result cstimer (MHZ)
			1	200.0	51.4
2	166.7	57
			3	142.9	51.4
4	125.0	61.9
			5	111.1	69.3
6	100.0	61.7
			7	90.9	67.9
8	83.3	65.5
			9	76.9	62.3
10	71.4	68.6
			11	66.7	67.9
12	62.5	64.5
			13	58.8	61.1
14	55.6	60.8
			15	52.6	53
16	50.0	49.8
			17	47.6	53.5
18	45.5	53.5
			19	43.5	53.4
20	41.7	50.8
			21	40.0	51.7
22	38.5	42.4
			23	37.0	42.4
24	35.7	42.4
			25	34.5	42.4

Table 1

User's temporal constraint in table 1, is to the constraint added by a certain path, it can be seen that sequence number be added by 1 to 10 constraints under, optimize in any case, all cannot meet user's design requirement.User is now needed to change Timing Constraints.

Being under multiple user's Timing Constraints of 25 to 11 by sequence number, it can be seen that apply method provided by the invention, after optimizing layout, the timing optimization degree in this path is fixed according to the constraints of user.When the constraints of user is comparatively loose, the degree of optimization in this path is relatively low, and in such as the 20th group of data, user is constrained to 4.17MHZ, and after optimization, this path can reach 50.8MHZ；And when the constraints of user is comparatively strict, the degree of optimization in path is just of a relatively high, and in such as the 12nd group of data, user is constrained to 62.5MHZ, after optimization, this path is up to 64.5MHZ.

Corresponding curve chart is as shown in Figure 3.It can be seen that in figure in arrow instruction interval, the sequential of layout after optimization, is constantly change along with the constraint of user, and the layout after namely optimizing dynamically adjusts according to temporal constraint, and its result is able to meet the requirement of temporal constraint.

Professional should further appreciate that, the unit of each example described in conjunction with the embodiments described herein and algorithm steps, can with electronic hardware, computer software or the two be implemented in combination in, in order to clearly demonstrate the interchangeability of hardware and software, generally describe composition and the step of each example in the above description according to function.These functions perform with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.Professional and technical personnel specifically can should be used for using different methods to realize described function to each, but this realization is it is not considered that beyond the scope of this invention.

The method described in conjunction with the embodiments described herein or the step of algorithm can use the software module that hardware, processor perform, or the combination of the two is implemented.Software module can be placed in any other form of storage medium known in random access memory (RAM), internal memory, read only memory (ROM), electrically programmable ROM, electrically erasable ROM, depositor, hard disk, moveable magnetic disc, CD-ROM or technical field.

Above-described detailed description of the invention; the purpose of the present invention, technical scheme and beneficial effect have been further described; it is it should be understood that; the foregoing is only the specific embodiment of the present invention; the protection domain being not intended to limit the present invention; all within the spirit and principles in the present invention, any amendment of making, equivalent replacement, improvement etc., should be included within protection scope of the present invention.

Claims (7)

1. the optimization method based on the fpga chip global wiring of temporal constraint, it is characterised in that described method includes:

According to the netlist of input and output IO layout after logic synthesis, obtain the initial line length of All Paths in global wiring；

Based on the Timing Constraints of user's input, determined the time margin slack in all paths by static timing analysis STA；

According to described time margin, in all paths, determine critical path；

Time margin according to described critical path, updates gauze weight；

Based on the gauze weight after updating, dynamically adjust global wiring, obtain the line length after path optimization；

Global wiring optimization is carried out according to the line length after optimizing.

2. method according to claim 1, it is characterised in that described according to described time margin, determines that critical path specifically includes in all paths:

When static timing analysis determines the described time margin of first path less than predetermined threshold value, it is determined that described first path is critical path.

3. method according to claim 2, it is characterised in that described predetermined threshold value is not less than 0.

4. method according to claim 1, it is characterised in that the described time margin according to described critical path, update gauze weight particularly as follows:

The size of the time margin according to described critical path, updates gauze weight；

Wherein, the time margin of described critical path is more little, and the gauze weight after renewal is more high.

5. method according to claim 1, it is characterised in that after carrying out global wiring optimization according to the line length after optimizing, described method also includes:

Record the number of times carrying out global wiring optimization according to the line length after optimizing；

Judge described to carry out the optimization the number of times whether number of times of global wiring optimization reaches to preset according to the line length after optimizing；

Without reaching, then continue the Timing Constraints based on user's input, determine the time margin slack in all paths in the global wiring after optimization by static timing analysis STA；

According to described time margin, in all paths, determine critical path；

Time margin according to described critical path, updates gauze weight；

Based on the gauze weight after updating, dynamically adjust global wiring, obtain the line length after path optimization；

Global wiring optimization is again carried out according to the line length after optimizing.

6. method according to claim 1, it is characterised in that after carrying out global wiring optimization according to the line length after optimizing, described method also includes:

Based on the Timing Constraints of user's input, determine the time margin slack in all paths in the global wiring after optimization by static timing analysis STA；

According to described time margin, determine whether to there is also critical path in all paths；

If there is also critical path, then the time margin according to described critical path, update gauze weight；

Based on the gauze weight after updating, dynamically adjust global wiring, obtain the line length after path optimization；

Global wiring optimization is again carried out according to the line length after optimizing.

7. method according to claim 1, it is characterised in that after described static timing analysis, described method also includes:

Generation static timing analysis is reported, described Timing Constraints is adjusted according to described static timing analysis report in order to described user.