CN109558345B - Memory selection method and device - Google Patents
Memory selection method and device Download PDFInfo
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- CN109558345B CN109558345B CN201710889278.2A CN201710889278A CN109558345B CN 109558345 B CN109558345 B CN 109558345B CN 201710889278 A CN201710889278 A CN 201710889278A CN 109558345 B CN109558345 B CN 109558345B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1657—Access to multiple memories
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides a memory selection method and a memory selection device. The method comprises the following steps: generating a plurality of different memory types according to timing requirements; selecting one type of memory to optimize time sequence and power consumption; reporting a ratio of timing margins and external low speed standard cells on the memory read path after optimization; and selecting to back to another memory type according to the time sequence surplus on the memory reading path and the proportion of the external low-speed standard cells until the memory type reaches the optimal memory time sequence and power. The invention can reduce the comprehensive iterative process and improve the chip development efficiency.
Description
Technical Field
The present invention relates to the field of integrated circuit design technologies, and in particular, to a memory selection method and apparatus.
Background
With the development of handheld devices towards high performance and high storage, the proportion of memories integrated in communication chips is higher and higher, and especially, the occupation proportion of memories in some Digital Signal Processing (DSP) modules is as high as more than 90%, and the timing and power (power) of the memories have a crucial influence on the performance of the whole chip.
At present, when designing a memory of a chip, considering timing and power of selecting standard cells, there are usually standard cells with different speeds and different power consumption performances, and the standard cells can be selected according to the timing on the current path. And in the selection of the memory, an extra margin of 10% -20% is uniformly added according to the working frequency of the memory, namely the time left for a memory external unit (cell) except the access/write time of the memory in the working period of the memory, and the margin is generated and directly integrated in an RTL (Register Transfer Level). Due to different access and write paths of different memories, the memories generated in a unified way have insufficient time sequence of some memories, and some memories consume excessive power.
In order to solve the above problems, currently, when selecting a memory, a memory and a related wrapper are first generated according to a chip manual and integrated into an RTL for integration according to a fixed margin, if a timing can be satisfied, the integration is completed, and if the timing has a slack, the memory needs to be regenerated and then integrated until the timing of the memory reaches an optimum.
By adopting the method, the memory needs to be regenerated and then integrated when the time sequence of the memory is not optimal, so that the iterative process is longer, and the development efficiency of the chip is reduced.
Disclosure of Invention
The memory selection method and the memory selection device provided by the invention can reduce the comprehensive iterative process and improve the chip development efficiency.
In a first aspect, the present invention provides a memory selection method, including:
generating a plurality of different memory types according to timing requirements;
selecting one type of memory to optimize time sequence and power consumption;
reporting a ratio of timing margins and external low speed standard cells on the memory read path after optimization;
and selecting to back to another memory type according to the time sequence surplus on the memory reading path and the proportion of the external low-speed standard cells until the memory type reaches the optimal memory time sequence and power.
Optionally, the selecting one of the memory types for timing and power consumption optimization includes: selecting a memory type with optimal time sequence to optimize the time sequence and the power consumption;
the selecting to fall back to another memory type includes: a memory type is selected that rolls back to a less well-timed sequence.
Optionally, the selecting one of the memory types for timing and power consumption optimization includes: selecting the memory type with the worst time sequence to optimize the time sequence and the power consumption;
the selecting to fall back to another memory type includes: the memory type is selected to be rolled back to a better timing.
Optionally, the selecting one of the memory types for timing and power consumption optimization includes: one memory type is selected for register transmission level RTL integration and built-in self-test insertion, and layout and optimization are carried out after relevant constraints are set.
Optionally, the external low speed standard cell is a high threshold voltage standard cell or a standard threshold voltage standard cell.
In a second aspect, the present invention provides a memory selection device, comprising:
the generating unit is used for generating a plurality of different memory types according to the time sequence requirement;
the optimization unit is used for selecting one memory type to optimize time sequence and power consumption;
a reporting unit, configured to report a timing surplus and a ratio of external low-speed standard cells on the memory read path after optimization;
and the rollback unit is used for selecting to rollback to another memory type according to the time sequence surplus on the memory reading path and the proportion of the external low-speed standard unit until the memory type reaches the optimal memory time sequence and power.
Optionally, the optimization unit is configured to select a memory type with an optimal timing sequence to perform timing sequence and power consumption optimization;
the rollback unit is used for selecting memory types which are rolled back to be poor in time sequence.
Optionally, the optimization unit is configured to select a memory type with the worst timing to perform timing and power consumption optimization;
the rollback unit is used for selecting a memory type with better rollback time sequence.
Optionally, the optimization unit is configured to select one of the memory types for register transfer level RTL integration and built-in self-test insertion, and perform layout and optimization after setting the relevant constraints.
Optionally, the external low speed standard cell is a high threshold voltage standard cell or a standard threshold voltage standard cell.
According to the memory selection method and the memory selection device, firstly, a plurality of different memory types are generated according to the time sequence requirement, one memory type is selected for time sequence and power consumption optimization, and according to the reported time sequence surplus on the memory reading path after optimization and the proportion of external low-speed standard units, the memory type is selected to be returned to the other memory type until the memory type achieves the optimal memory time sequence and power. Compared with the prior art, the invention generates a plurality of memories with different performances in advance before the integration, and can reduce the integration iteration process when the memory rolls back, thereby simplifying the chip development process and improving the chip development efficiency.
Drawings
FIG. 1 is a flow chart of a memory selection method according to an embodiment of the invention;
fig. 2 is a schematic structural diagram of a memory selection device according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a memory selection method, as shown in fig. 1, the method includes:
and S11, generating a plurality of different memory types according to the timing requirements.
And S12, selecting one memory type to optimize time sequence and power consumption.
Specifically, the memory type with the optimal timing sequence may be selected for timing sequence and power consumption optimization, or the memory type with the worst timing sequence may be selected for timing sequence and power consumption optimization.
And S13, reporting the timing surplus and the proportion of the external low-speed standard cells on the memory reading path after optimization.
Wherein the external low-speed standard cell is a high threshold voltage standard cell or a standard threshold voltage standard cell.
And S14, selecting to roll back to another memory type according to the timing surplus on the memory reading path and the proportion of the external low-speed standard cells until the memory type reaches the optimal memory timing and power.
Specifically, when the memory type with the optimal timing sequence is selected for timing sequence and power consumption optimization in step S12, the memory type with the poor timing sequence is selected; when the memory type with the worst timing is selected for timing and power consumption optimization in step S12, the memory type with the best timing is selected.
According to the memory selection method provided by the embodiment of the invention, firstly, a plurality of different memory types are generated according to the time sequence requirement, one memory type is selected for time sequence and power consumption optimization, and the memory type is selected to be backed to another memory type according to the reported time sequence surplus on the reading path of the memory and the proportion of the external low-speed standard unit after optimization until the memory type reaches the optimal memory time sequence and power. Compared with the prior art, the invention generates a plurality of memories with different performances in advance before the integration, and can reduce the integration iteration process when the memory rolls back, thereby simplifying the chip development process and improving the chip development efficiency.
The following describes a memory selection method provided by an embodiment of the present invention in detail.
Before selecting the memory, the memory with different timing margins and the related wrapper are generated according to a chip manual, and then the memory is automatically rolled back to the proper memory type according to the result of checking the timing in the process of selecting the memory to realize the optimization of the timing and the power.
S21, generating memory cells with different timing margins and powers during memory generation, which may be classified into different levels according to design requirements, for example: 5%, 10%, 5%, 20%, memory cells with different margins need to keep the interfaces (number and name of pins) consistent.
The Memory unit includes various RAMs (Random Access memories) and ROMs (Read-Only memories) integrated in a chip or a module.
S22, first select the memory cell with the best timing (i.e., the memory cell with the most surplus) for RTL integration and BIST (Built-in Self Test) insertion (insertion).
And S23, setting relevant constraints (constraints) and then performing layout (mapping) and optimization.
S24, checking the timing of the optimized netlist, reporting margin surplus on a reading path of the memory and the proportion of HVT (high threshold voltage) or SVT (standard threshold voltage) standard cells (i.e. cells with slower speed in the library) used.
And S25, according to the reported result, backing back the memory by taking the margin surplus and the proportion of the HVT standard unit as indexes, for example:
rollback to 5% memory when margin surplus > 20% and HVT standard cell < 10%;
rollback to 5% memory when margin surplus > 15% and HVT standard cell > 10%;
rollback to 5% memory when margin surplus > 10% and HVT standard cell > 20%;
rollback to 10% memory when margin surplus > 10% and HVT standard cell < 20%;
rollback to 10% memory when margin surplus > 5% and HVT standard cell > 20%;
rollback to 15% memory when margin surplus > 5% and HVT standard cell < 20%;
the current memory type is maintained when margin surplus < 5% and HVT standard cell < 20%.
S26, rolling back the memory type and then optimizing again, because only the checking of the relevant time sequence of the memory is involved, the optimization is fast, the time sequence is checked again after the optimization, if the margin is left, the step S25 can be repeatedly executed, and finally the optimal memory time sequence and power can be obtained.
Alternatively, different types of memory cells can be generated according to the power consumption or the area of the memory, and memory rollback according to the combination of the power consumption or the area is realized in the synthesis process.
An embodiment of the present invention further provides a memory selection apparatus, as shown in fig. 2, the apparatus includes:
a generating unit 11 for generating a plurality of different memory types according to timing requirements;
the optimization unit 12 is used for selecting one of the memory types to optimize time sequence and power consumption;
a reporting unit 13, configured to report a timing margin on the memory read path after optimization and a ratio of external low-speed standard cells;
and a rollback unit 14, configured to select to rollback to another memory type according to the timing surplus on the memory read path and a ratio of external low-speed standard cells, where the optimizing unit 12 and the reporting unit 13 repeatedly perform corresponding operations for the another memory type after rollback until the memory type reaches an optimal memory timing and power.
Optionally, the optimizing unit 12 is configured to select a memory type with an optimal timing sequence to perform timing sequence and power consumption optimization;
the rollback unit 14 is configured to select a memory type that rolls back to a worse timing.
Optionally, the optimizing unit 12 is configured to select a memory type with the worst timing to perform timing and power consumption optimization;
the rollback unit 14 is configured to select a memory type that rolls back to a better timing.
Optionally, the optimization unit 12 is configured to select one of the memory types for register transfer level RTL integration and built-in self-test insertion, and perform layout and optimization after setting relevant constraints.
Optionally, the external low speed standard cell is a high threshold voltage standard cell or a standard threshold voltage standard cell.
According to the memory selection device provided by the embodiment of the invention, firstly, a plurality of different memory types are generated according to the time sequence requirement, one memory type is selected for time sequence and power consumption optimization, and the memory type is selected to be backed to another memory type according to the reported time sequence surplus on the memory reading path after optimization and the proportion of the external low-speed standard unit until the memory type reaches the optimal memory time sequence and power. Compared with the prior art, the invention generates a plurality of memories with different performances in advance before the integration, and can reduce the integration iteration process when the memory rolls back, thereby simplifying the chip development process and improving the chip development efficiency.
The apparatus of this embodiment may be configured to implement the technical solutions of the above method embodiments, and the implementation principles and technical effects are similar, which are not described herein again.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. A memory selection method, comprising:
generating a plurality of different memory types according to timing requirements;
selecting one type of memory to optimize time sequence and power consumption;
reporting a ratio of a timing margin on the memory read path to an external low speed standard cell after optimization, the external low speed standard cell being a high threshold voltage standard cell or a standard threshold voltage standard cell;
and according to the timing surplus on the memory reading path and the proportion of the external low-speed standard cells, selecting to back to another memory type until the memory type has the optimal memory timing and power.
2. The method of claim 1, wherein selecting one of the memory types for timing and power optimization comprises: selecting a memory type with optimal time sequence to optimize the time sequence and the power consumption;
the selecting to fall back to another memory type includes: a memory type is selected that rolls back to less sequential, where less sequential surplus indicates less sequential.
3. The method of claim 1, wherein selecting one of the memory types for timing and power optimization comprises: selecting the memory type with the worst time sequence to optimize the time sequence and the power consumption;
the selecting to fall back to another memory type includes: selecting a memory type that rolls back to better timing, wherein more timing surplus indicates better timing.
4. The method of any of claims 1 to 3, wherein selecting one of the memory types for timing and power optimization comprises: one memory type is selected for register transmission level RTL integration and built-in self-test insertion, and layout and optimization are carried out after relevant constraints are set.
5. A memory selection device, comprising:
the generating unit is used for generating a plurality of different memory types according to the time sequence requirement;
the optimization unit is used for selecting one memory type to optimize time sequence and power consumption;
the reporting unit is used for reporting the proportion of the time sequence surplus and the external low-speed standard cells on the memory read path after optimization, wherein the external low-speed standard cells are high-threshold voltage standard cells or standard-threshold voltage standard cells;
and the rollback unit is used for selecting rollback to another memory type according to the time sequence surplus on the memory reading path and the proportion of the external low-speed standard unit until the memory type has the optimal memory time sequence and power.
6. The apparatus of claim 5, wherein the optimization unit is configured to select a memory type with optimal timing for timing and power consumption optimization;
the rollback unit is used for selecting a memory type which backs to a poor timing sequence, wherein the less surplus of the timing sequence represents the poor timing sequence.
7. The apparatus of claim 5, wherein the optimization unit is configured to select a memory type with a worst timing for timing and power consumption optimization;
the rollback unit is used for selecting a memory type which backs to a better time sequence, wherein the more surplus time sequences represent the better time sequence.
8. The apparatus of any one of claims 5 to 7, wherein the optimization unit is configured to select one of the memory types for register transfer level RTL integration and built-in self-test insertion, and perform layout and optimization after setting relevant constraints.
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| CN113311997B (en) * | 2021-05-28 | 2024-03-08 | 上海阵量智能科技有限公司 | Memory selection method, device, computer equipment and storage medium |
| CN115796116B (en) * | 2023-01-30 | 2023-09-22 | 飞腾信息技术有限公司 | Integrated circuit optimization method and device, storage medium and electronic equipment |
| CN116090382B (en) * | 2023-03-28 | 2023-06-23 | 深圳鸿芯微纳技术有限公司 | Time sequence report generation method and device |
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