CN109558345A - Memory selection method and device - Google Patents
Memory selection method and device Download PDFInfo
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- CN109558345A CN109558345A CN201710889278.2A CN201710889278A CN109558345A CN 109558345 A CN109558345 A CN 109558345A CN 201710889278 A CN201710889278 A CN 201710889278A CN 109558345 A CN109558345 A CN 109558345A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1657—Access to multiple memories
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The present invention provides a kind of memory selection method and device.The described method includes: generating a variety of different type of memory according to timing requirements；It chooses one of type of memory and carries out timing and optimised power consumption；The ratio of time sequence allowance surplus and external low speed standard block after report optimization on the memory read path；According to the ratio of time sequence allowance surplus and external low speed standard block on the memory read path, selection retracts to another type of memory, until memory timing and power that type of memory is optimal.The present invention can reduce comprehensive iterative process, improve chip development efficiency.
Description
Technical field
The present invention relates to IC design technical field more particularly to a kind of memory selection method and devices.
Background technique
As handheld device develops to the high storage trend of high-performance, the memory specific gravity integrated in communication chip is increasingly
Height, memory occupies ratio especially in some DSP (Digital Signal Processing, Digital Signal Processing) module
Example up to 90% or more, the timing (timing) and power (power) of memory play the performance of entire chip most important
Influence.
Currently, in the memory of design chips, there is considering for timing and power to the selection of standard block, it will usually
There is the standard block of friction speed different power consumption performance, can be selected according to the timing on current path.And in memory
It is to unify to add additional 10%~20% margin (surplus) again according to memory operation frequencies, i.e., in memory work in selection
Make period removing memory itself access (access)/write-in (write) time and leaves memory external unit (cell) in addition
Time, generate and to be directly integrated in RTL (Register Transfer Level, Method at Register Transfer Level) inner.Since difference is deposited
The access of reservoir and write paths are different, and the timing that will appear some memories according to the unified memory generated is insufficient, and
Power consumption is excessive again for some memories.
To solve the above-mentioned problems, currently, when carrying out memory selection, first according to chip handbook according to fixed surplus
Memory and correlation wrapper (circular) are generated, is integrated in RTL and is integrated, is so integrated if timing can satisfy
It completes, if timing has slack (surplus), it is necessary to regenerate memory and be integrated again, until memory timing reaches
Until optimal.
Using the above method, due to need to regenerate when memory timing is not optimal memory carry out again it is comprehensive
It closes, iterative process is longer, reduces the development efficiency of chip.
Summary of the invention
Memory selection method provided by the invention and device can reduce comprehensive iterative process, improve chip development
Efficiency.
In a first aspect, the present invention provides a kind of memory selection method, comprising:
A variety of different type of memory are generated according to timing requirements；
It chooses one of type of memory and carries out timing and optimised power consumption；
The ratio of time sequence allowance surplus and external low speed standard block after report optimization on the memory read path
Example；
According to the ratio of time sequence allowance surplus and external low speed standard block on the memory read path, select back
Another type of memory is retreated to, until memory timing and power that type of memory is optimal.
Optionally, one of type of memory of the selection carries out timing and optimised power consumption includes: that selection timing is optimal
Type of memory carry out timing and optimised power consumption；
It includes: the selection rollback type of memory poor to timing that the selection, which retracts to another type of memory,.
Optionally, one of type of memory of the selection carries out timing and optimised power consumption includes: that selection timing is worst
Type of memory carry out timing and optimised power consumption；
It includes: that selection retracts to the preferable type of memory of timing that the selection, which retracts to another type of memory,.
Optionally, one of type of memory of the selection carries out timing and optimised power consumption includes: to choose one of which
Type of memory progress Method at Register Transfer Level RTL is integrated and built-in self-test is inserted into, and cloth is carried out after setting related constraint
Office and optimization.
Optionally, the external low speed standard block is high threshold voltage standard block or standard threshold voltage standard list
Member.
Second aspect, the present invention provide a kind of memory selection device, comprising:
Generation unit, for generating a variety of different type of memory according to timing requirements；
Optimize unit, carries out timing and optimised power consumption for choosing one of type of memory；
Reporting unit, for reporting time sequence allowance surplus and external low speed after optimization on the memory read path
The ratio of standard block；
Rollback unit, for according on the memory read path time sequence allowance surplus and external low speed standard block
Ratio, selection retracts to another type of memory, until memory timing and power that type of memory is optimal.
Optionally, the optimization unit carries out timing and optimised power consumption for choosing the optimal type of memory of timing；
The rollback unit, for selecting the type of memory poor to timing that retract.
Optionally, the optimization unit carries out timing and optimised power consumption for choosing the worst type of memory of timing；
The rollback unit retracts for selecting to the preferable type of memory of timing.
Optionally, the optimization unit, it is integrated for choosing one of type of memory progress Method at Register Transfer Level RTL
It is inserted into built-in self-test, and is laid out and optimizes after setting related constraint.
Optionally, the external low speed standard block is high threshold voltage standard block or standard threshold voltage standard list
Member.
Memory selection method provided in an embodiment of the present invention and device are generated according to timing requirements a variety of different first
Type of memory chooses one of type of memory and carries out timing and optimised power consumption, is deposited according to described after the optimization of report
The ratio of time sequence allowance surplus and external low speed standard block on reservoir read path, selection retract to another memory class
Type, until memory timing and power that type of memory is optimal.Compared with prior art, the present invention is carrying out integrating it
Before the memories of a variety of different performances is generated in advance, comprehensive iterative process can be reduced when memory retracts, to simplify
Chip development process improves chip development efficiency.
Detailed description of the invention
Fig. 1 is the flow chart of memory selection method provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram for the memory selection device that one embodiment of the invention provides.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only
It is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill
Personnel's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of memory selection method, as shown in Figure 1, which comprises
S11, a variety of different type of memory are generated according to timing requirements.
S12, one of type of memory progress timing and optimised power consumption are chosen.
Specifically, the optimal type of memory of timing can be chosen and carry out timing and optimised power consumption, or choose timing most
The type of memory of difference carries out timing and optimised power consumption.
Time sequence allowance surplus and external low speed standard block after S13, report optimization on the memory read path
Ratio.
Wherein, the external low speed standard block is high threshold voltage standard block or standard threshold voltage standard list
Member.
S14, according to the ratio of time sequence allowance surplus and external low speed standard block on the memory read path, choosing
Rollback is selected to another type of memory, until memory timing and power that type of memory is optimal.
Specifically, it when step S12, which chooses the optimal type of memory of timing, carries out timing and optimised power consumption, selects here
Retract the type of memory poor to timing；When step S12 chooses, the worst type of memory of timing carries out timing and power consumption is excellent
When change, selection retracts to the preferable type of memory of timing here.
Memory selection method provided in an embodiment of the present invention generates a variety of different memories according to timing requirements first
Type chooses one of type of memory and carries out timing and optimised power consumption, read according to memory described after the optimization of report
Take the ratio of time sequence allowance surplus on path and external low speed standard block, selection retracts to another type of memory, directly
The memory timing and power being optimal to type of memory.Compared with prior art, present invention thing before integrating
The memory of a variety of different performances is first generated, comprehensive iterative process can be reduced when memory retracts, thus facilitating chip
Development process improves chip development efficiency.
Memory selection method provided in an embodiment of the present invention is described in detail below.
Before selecting memory, the memory and correlation with different timing surpluses are generated according to chip handbook
Wrapper (circular) is then suitably deposited according to the result of inspection timing to be automatically retracted back into during reselection memory
The optimization of timing and power is realized in reservoir type.
S21, when memory generates, generate the memory cell with different timing surpluses and power, can be according to setting
Meter needs a point different brackets, such as: 5% surplus, 10% surplus, 5% surplus, 20% surplus, the memory cell of different surpluses
Need to keep interface (quantity of pin with title) consistent.
Wherein, the memory cell includes various RAM (the Random Access for being integrated in chip or inside modules
Memory, random access memory) and ROM (Read-Only Memory, read-only memory).
S22, choose first best (namely there are the surplus most) memory cell of timing carry out RTL it is integrated and
BIST (Built-in Self Test, built-in self-test) is inserted into (insertion).
S23, (mapping) is laid out after setting related constraint (constraints) and is optimized.
S24, it checks the netlist that has optimized timing, surplus surplus on reporting memory read path and is used
The ratio of HVT (high threshold voltage) or SVT (standard threshold voltage) standard block (i.e. slow unit in library).
S25, according to report as a result, being returned using the ratio of surplus surplus and HVT standard block as index to memory
It moves back, such as:
When surplus surplus>20% and HVT standard block<10% when, retract to 5% memory；
When surplus surplus > 15% and HVT standard block > 10% when, retract to 5% memory；
When surplus surplus > 10% and HVT standard block > 20% when, retract to 5% memory；
When surplus surplus>10% and HVT standard block<20% when, retract to 10% memory；
When surplus surplus > 5% and HVT standard block > 20% when, retract to 10% memory；
When surplus surplus>5% and HVT standard block<20% when, retract to 15% memory；
When surplus surplus < 5% and HVT standard block < 20% when, keep current storage type.
A suboptimization is carried out again after S26, rollback type of memory, due to pertaining only to the inspection of memory correlation timing,
Such optimization is quickly, timing to be reexamined after optimization, may finally if step S25 can be repeated by also having a margin
Obtain optimal memory timing and power.
Alternatively it is also possible to generate different types of memory cell according to the power consumption of memory or area, then exist
It realizes and is combined according to power consumption or area to carry out memory rollback in combined process.
The embodiment of the present invention also provides a kind of memory selection device, as shown in Fig. 2, described device includes:
Generation unit 11, for generating a variety of different type of memory according to timing requirements；
Optimize unit 12, carries out timing and optimised power consumption for choosing one of type of memory；
Reporting unit 13, for reporting that time sequence allowance surplus after optimization on the memory read path and outside are low
The ratio of fast standard block；
Rollback unit 14, for according on the memory read path time sequence allowance surplus and external low speed standard list
The ratio of member, selection retract to another type of memory, and the optimization unit 12 and the reporting unit 13 are directed to after retracting
The another kind type of memory repeat corresponding operating, until the memory timing that is optimal of type of memory and function
Rate.
Optionally, the optimization unit 12 carries out timing and optimised power consumption for choosing the optimal type of memory of timing；
The rollback unit 14, for selecting the type of memory poor to timing that retract.
Optionally, the optimization unit 12 carries out timing and optimised power consumption for choosing the worst type of memory of timing；
The rollback unit 14 retracts for selecting to the preferable type of memory of timing.
Optionally, the optimization unit 12 carries out Method at Register Transfer Level RTL collection for choosing one of type of memory
It is inserted at built-in self-test, and is laid out and optimizes after setting related constraint.
Optionally, the external low speed standard block is high threshold voltage standard block or standard threshold voltage standard list
Member.
Memory selection device provided in an embodiment of the present invention generates a variety of different memories according to timing requirements first
Type chooses one of type of memory and carries out timing and optimised power consumption, read according to memory described after the optimization of report
Take the ratio of time sequence allowance surplus on path and external low speed standard block, selection retracts to another type of memory, directly
The memory timing and power being optimal to type of memory.Compared with prior art, present invention thing before integrating
The memory of a variety of different performances is first generated, comprehensive iterative process can be reduced when memory retracts, thus facilitating chip
Development process improves chip development efficiency.
The device of the present embodiment can be used for executing the technical solution of above method embodiment, realization principle and technology
Effect is similar, and details are not described herein again.
Those of ordinary skill in the art will appreciate that realizing all or part of the process in above-described embodiment method, being can be with
Relevant hardware is instructed to complete by computer program, the program can be stored in a computer-readable storage medium
In, the program is when being executed, it may include such as the process of the embodiment of above-mentioned each method.Wherein, the storage medium can be magnetic
Dish, CD, read-only memory (Read-Only memory, ROM) or random access memory (Random Access storage
Device, RAM) etc..
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by those familiar with the art, all answers
It is included within the scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.
Claims (10)
1. a kind of memory selection method characterized by comprising
A variety of different type of memory are generated according to timing requirements；
It chooses one of type of memory and carries out timing and optimised power consumption；
The ratio of time sequence allowance surplus and external low speed standard block after report optimization on the memory read path；
According to the ratio of time sequence allowance surplus and external low speed standard block on the memory read path, selection retracts extremely
Another type of memory, until memory timing and power that type of memory is optimal.
2. the method according to claim 1, wherein the selection one of which type of memory carry out timing and
Optimised power consumption includes: to choose the optimal type of memory of timing to carry out timing and optimised power consumption；
It includes: the selection rollback type of memory poor to timing that the selection, which retracts to another type of memory,.
3. the method according to claim 1, wherein the selection one of which type of memory carry out timing and
Optimised power consumption includes: to choose the worst type of memory of timing to carry out timing and optimised power consumption；
It includes: that selection retracts to the preferable type of memory of timing that the selection, which retracts to another type of memory,.
4. according to the method in any one of claims 1 to 3, which is characterized in that one of memory class of the selection
Type carries out timing and optimised power consumption includes: one of type of memory progress Method at Register Transfer Level RTL of selection integrated and built-in
Self-test insertion, and be laid out and optimize after setting related constraint.
5. according to the method in any one of claims 1 to 3, which is characterized in that the external low speed standard block is height
Threshold voltage standard unit or standard threshold voltage standard block.
6. a kind of memory selection device characterized by comprising
Generation unit, for generating a variety of different type of memory according to timing requirements；
Optimize unit, carries out timing and optimised power consumption for choosing one of type of memory；
Reporting unit, for reporting time sequence allowance surplus and external low speed standard after optimization on the memory read path
The ratio of unit；
Rollback unit, for the ratio according to time sequence allowance surplus and external low speed standard block on the memory read path
Example, selection retract to another type of memory, until memory timing and power that type of memory is optimal.
7. device according to claim 6, which is characterized in that the optimization unit, for choosing the optimal storage of timing
Device type carries out timing and optimised power consumption；
The rollback unit, for selecting the type of memory poor to timing that retract.
8. device according to claim 6, which is characterized in that the optimization unit, for choosing the worst storage of timing
Device type carries out timing and optimised power consumption；
The rollback unit retracts for selecting to the preferable type of memory of timing.
9. the device according to any one of claim 6 to 8, which is characterized in that the optimization unit, for choosing wherein
A kind of type of memory progress Method at Register Transfer Level RTL is integrated and built-in self-test is inserted into, and laggard setting related constraint
Row layout and optimization.
10. the device according to any one of claim 6 to 8, which is characterized in that the external low speed standard block is height
Threshold voltage standard unit or standard threshold voltage standard block.
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| CN113311997A (en) * | 2021-05-28 | 2021-08-27 | 上海阵量智能科技有限公司 | Memory selection method and device, computer equipment and storage medium |
| CN115796116A (en) * | 2023-01-30 | 2023-03-14 | 飞腾信息技术有限公司 | Integrated circuit optimization method and device, storage medium and electronic equipment |
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