CN104679529A - Layout method of FPGA (Field Programmable Gate Array) chip clock net - Google Patents

Layout method of FPGA (Field Programmable Gate Array) chip clock net Download PDF

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Publication number
CN104679529A
CN104679529A CN201310608638.9A CN201310608638A CN104679529A CN 104679529 A CN104679529 A CN 104679529A CN 201310608638 A CN201310608638 A CN 201310608638A CN 104679529 A CN104679529 A CN 104679529A
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gauze
described
clock
net
weight
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CN201310608638.9A
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CN104679529B (en
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吴鑫
虞健
蒋中华
刘明
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京微雅格(北京)科技有限公司
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Abstract

The invention relates to a layout method of an FPGA (Field Programmable Gate Array) chip clock net. The method comprises the following steps: determining a low-skew net and a common clock net in a net of the FPGA chip, wherein the net of the FPGA chip comprises a data net and a clock net, and the clock net comprises the low-skew net and the common clock net; inquiring whether a unit corresponding to a destination end of the common clock net is a register unit or not; when the unit corresponding to the destination end of the common clock net is the register unit, increasing the weight of the common clock net; according to the weight, carrying out optimization processing on the net of the FPGA chip, and obtaining the length of the net, which is subjected to the optimization processing, of the FPGA chip; and according to the length of the optimization processing common clock net, carrying out layout processing on the register unit corresponding to the destination end of the common clock net.

Description

The layout method of fpga chip Clock Net

Technical field

The present invention relates to placement-and-routing's technical field, the particularly layout method of fpga chip Clock Net of field programmable gate array (Field Programmable Gate Array, FPGA) chip.

Background technology

FPGA is the logical device be made up of many logical blocks, wherein logical block comprises door, look-up table and trigger, it has enriches hardware resource, powerful parallel processing capability and flexible reconfigurable ability, obtains increasing widespread use in a lot of field such as data processing, communication, network.

In the hardware structure of FPGA, clock sources is limited and have certain region limits.For have more independent clock control signal register design for, just they must be distributed in the middle of different processor local bus (PLB) during detailed placement, and the clock control signal restricted number met further in clock zone, meets various hardware constraints.If total arrangement's stage does not consider various clock signal optimization, can make in total arrangement's result, the register distribution relative loose of clock signal of the same race, thus increase difficulty and the complexity of detailed placement, and then increase the complexity of wiring, reduce the success ratio of wiring, even for the too much design of independently control signal, in wiring stage failure.

Summary of the invention

The object of the invention is the defect for prior art, provide a kind of layout method of fpga chip Clock Net.

Embodiments provide a kind of layout method of fpga chip Clock Net, comprising:

Low clock skew low-skew gauze and ordinary clock gauze is determined in the gauze of fpga chip; Wherein, the gauze of described fpga chip comprises data gauze and Clock Net, and described Clock Net comprises low-skew gauze and ordinary clock gauze;

Whether the unit corresponding to destination inquiring about described ordinary clock gauze is register cell;

When described ordinary clock gauze destination corresponding to unit be register cell time, increase the weight of described ordinary clock gauze;

Process is optimized, the line length of the gauze of the fpga chip after optimization process according to the gauze of described weight to described fpga chip;

According to the line length of the ordinary clock gauze after optimization process, layout processing is carried out to the register cell corresponding to the destination of described ordinary clock gauze.

Preferably, describedly in the gauze of fpga chip, determine that the method for low-skew gauze and ordinary clock gauze specifically comprises:

Obtain in the gauze of described fpga chip, the fan-out amount of every root gauze;

The n root Clock Net that fan-out amount described in described Clock Net of determining is maximum is low-skew gauze; Wherein n is the number of low-skew gauze resource in the hardware resource of described fpga chip;

Determine that other Clock Nets in described Clock Net except described low-skew gauze are ordinary clock gauze.

Preferred further, the method for the weight of the described ordinary clock gauze of described increase is specially:

According to the fan-out amount of root gauze every in the gauze of described fpga chip, determine the weight of described every root gauze;

The weight of described ordinary clock gauze is increased respectively the first quantity doubly, to make the ratio of the average weight of described whole Clock Net and the average weight of described total data gauze for preset value.

Preferred further, the method for the weight of the described ordinary clock gauze of described increase is specially:

Obtain the weight of every root Clock Net in the ordinary clock gauze of described fpga chip;

Adjust respectively the weight of described every root Clock Net, the ratio of the weight of the ordinary clock gauze before making the weight of the ordinary clock gauze after adjustment and adjusting is preset value.

Preferred further, the scope of described preset value is between 1 to 2.

Preferably, be describedly optimized process according to the gauze of described weight to described fpga chip, the line length of the ordinary clock gauze after the process that is optimized is specially:

According to the order of the weight determination optimization process of the every root gauze in the gauze of described fpga chip, the gauze large to weight is preferentially optimized process, be optimized the line length of gauze of the fpga chip after process, comprising the line length of the ordinary clock gauze after optimization process.

Described optimization process is specially:

Iterative computation is carried out to the weight of root Clock Net every in the gauze of described fpga chip, until in described Clock Net any wire net two end points between the variable quantity of semi-perimeter line length be all less than default variable quantity.

Preferably, when the non-register cell of the unit that the destination of described ordinary clock gauze is corresponding, then the weight of described ordinary clock gauze is not changed.

The layout method of the fpga chip Clock Net that the embodiment of the present invention provides, Clock Net information is collected by carrying out traversal to all registers having clock signal, determine to need optimised ordinary clock gauze, increase the weight of Clock Net, these Clock Nets are made to have higher crucial degree when line length is optimized than other gauzes, thus can be preferentially optimised when optimization process, finally reach the distribution range reducing the register that same Clock Net controls, realize FPGA layout optimization, and then reach the complexity reducing follow-up wiring, improve the final object being routed to power.

Accompanying drawing explanation

The layout method process flow diagram of the fpga chip Clock Net that Fig. 1 provides for the embodiment of the present invention;

The schematic diagram of a kind of fpga chip Clock Net that Fig. 2 provides for the embodiment of the present invention.

Embodiment

Below by drawings and Examples, technical scheme of the present invention is described in further detail.

The layout method process flow diagram of the fpga chip Clock Net that Fig. 1 provides for the embodiment of the present invention, as shown in the figure, the method comprises the steps:

Step 110, determines low clock skew low-skew gauze and ordinary clock gauze in the gauze of fpga chip; Wherein, the gauze of described fpga chip comprises data gauze and Clock Net, and described Clock Net comprises low-skew gauze and ordinary clock gauze;

Concrete, comprising:

Step 111, obtains in the gauze of described fpga chip, the fan-out amount of every root gauze;

Wherein, fan-out amount refers to the unit number of the actual driving of every root Clock Net; Described unit can be register, look-up table etc.

Step 112, the n root Clock Net that fan-out amount described in described Clock Net of determining is maximum is low-skew gauze; Wherein n is the number of low-skew gauze resource in the hardware resource of described fpga chip.

Concrete further, the hardware resource that different fpga chips has may not be identical, and wherein included low-skew Clock Net resource also may be different.Such as in a concrete example, the quantity of low-skew gauze can be two.

Step 113, determines that other Clock Nets in described Clock Net except described low-skew gauze are ordinary clock gauze.

Step 120, whether the unit corresponding to destination inquiring about described ordinary clock gauze is register cell;

Concrete, when the non-register cell of the unit that the destination of described ordinary clock gauze is corresponding, then do not change the weight of described ordinary clock gauze;

Otherwise perform, step 130, when described ordinary clock gauze destination corresponding to unit be register cell time, increase the weight of described ordinary clock gauze;

Concrete, the method increasing the weight of ordinary clock gauze is specifically as follows shown in following steps 131 to step 132.

Step 131, according to the fan-out amount of root gauze every in the gauze of described fpga chip, determines the weight of described every root gauze;

Preferably, the fan-out amount of single line net is larger, and its weight is less.

Step 132, increases by the first quantity doubly respectively by the weight of described ordinary clock gauze, to make the ratio of the average weight of described whole Clock Net and the average weight of described total data gauze for preset value.。

In addition, the method also increasing the weight of ordinary clock gauze can shown in following steps 133 to step 134.

Step 133, obtains the weight of every root Clock Net in the ordinary clock gauze of described fpga chip;

Step 134, adjusts respectively to the weight of described every root Clock Net, and the ratio of the weight of the ordinary clock gauze before making the weight of the ordinary clock gauze after adjustment and adjusting is preset value.

Increase in the method for the weight of ordinary clock gauze at above-mentioned two kinds, ranging preferably between 1 to 2 of described preset value.Preferred further, preset value equals 1.2.

Namely in the above described two methods, be all the increase in the weight of ordinary clock gauze, make it have the weight higher than data gauze.

Step 140, is optimized process according to the gauze of described weight to described fpga chip, the line length of the gauze of the fpga chip after optimization process;

Concrete, according to the order of the weight determination optimization process of the every root gauze in the gauze of described fpga chip, the gauze large to weight is preferentially optimized process, and the line length of the gauze of the fpga chip after the process that is optimized, comprising the line length of the ordinary clock gauze after optimization process.

Because the weight of ordinary clock gauze adjusts in abovementioned steps, have higher weight than data gauze, therefore when optimization process, ordinary clock gauze is preferentially optimized process, the line length of the ordinary clock gauze after the process that is optimized.

Wherein, being specifically as follows of optimization process: iterative computation is carried out to the weight of root Clock Net every in the gauze of described fpga chip, until in described Clock Net any wire net two end points between the variable quantity of semi-perimeter line length be all less than default variable quantity.

Above-mentioned semi-perimeter line length refers to: suppose that two end points of single line net are respectively the relative end points of two an of rectangle, a semi-perimeter of this rectangle, is semi-perimeter line length.

In order to ensure optimization line length after do not increase wiring congestion, therefore require for each Clock Net before optimization after length variations can not exceed certain scope.Above-mentionedly judge that the length variations of Clock Net is only a citing with semi-perimeter line length, but not limitation of the invention, after additive method can also being adopted ensure and optimizing line length, meet placement-and-routing's requirement of fpga chip.

The circular of optimization process can adopt the computing method of Matrix Solving, specifically can be described in following detailed example, repeat no more herein.

Step 150, according to the line length of the ordinary clock gauze after optimization process, carries out layout processing to the register cell corresponding to the destination of described ordinary clock gauze.

The layout method of the fpga chip Clock Net that the embodiment of the present invention provides, Clock Net information is collected by carrying out traversal to all registers having clock signal, determine to need optimised ordinary clock gauze, increase the weight of Clock Net, these Clock Nets are made to have higher crucial degree when line length is optimized than other gauzes, thus can be preferentially optimised when optimization process, finally reach the distribution range reducing the register that same Clock Net controls, realize FPGA layout optimization, and then reach the complexity reducing follow-up wiring, improve the final object being routed to power.

Below with some concrete examples, the method provided in the above embodiment of the present invention is described in further detail.

Example 1:

As shown in Figure 2, in this example, to have two ports, the structure of two unit and three Clock Nets is that example is described to a kind of schematic diagram of fpga chip Clock Net.Wherein unit 1 is look-up table (LUT), and unit 2 is register.Three Clock Nets are respectively port one to look-up table, look-up table to register and register to these three Clock Nets 1,2,3 of port 2; The length of its correspondence is respectively (x1-x0), (x2-x1), (x3-x2).Wherein x0 is the coordinate position of port one, and x1 is the unit 1 i.e. coordinate position of look-up table, and x2 is the unit 2 i.e. coordinate position of register, and x3 is the coordinate position of port 2.

In this example, the source of the clock signal of register is unit 1; The weight of initial each Clock Net is all 1; Two port coordinate position x0=100, x3=200, suppose that port one, LUT, register, port 2 are all in same level position, namely y coordinate position does not change.

According to polynomial matrix solution formula:

min φ = Σ n ∈ N L n W n = Σ n ∈ N W n ( ( x i - x j ) 2 + ( y i - y j ) 2 ) (formula 1)

∂ φ ∂ x i = 0 , ∂ φ ∂ y i = 0 ; (formula 2,3)

φ is the weighting of secondary line length, and n is the radical of gauze, and N is positive integer, and L is the length of single line net, and W is gauze weight, (x i, y i), (x j, y j) coordinate of respectively single line net two end points.

Data according to this example calculate:

Min Cost'=(x 1-100) 2+ (x 1-x 2) 2+ (x 2-200) 2(formula 4)

∂ ∂ x 1 Cost = 2 × ( x 1 - x 2 ) + 2 × ( x 1 - 100 ) , ∂ ∂ x 2 Cost = 2 × ( x 1 - x 2 ) + 2 × ( x 1 - 100 ) (formula 5,6)

Matrix Solving is carried out: AX+B=0 (formula 7) according to above formula

Wherein A is matrix, and B is vector.

2 - 1 - 1 2 x 1 x 2 + - 100 - 200 = 0 (formula 8)

Obtain x 1=400/3, x 2=500/3, unit is 100um.

That is, before layout optimization, the initial position of register apart from its signal source of clock LUT position between line length be x 2-x 1=33.33nm.

Be optimized according to the layout of method provided by the invention to Clock Net, the weight of the Clock Net between look-up table to register is risen to original 1.2 times.Clock Net is optimized.

Min Cost'=(x 1'-100) 2+ 1.2 × (x 1'-x 2') 2+ (x 2'-200) 2(formula 9)

∂ ∂ x 1 ′ Cost = 2.4 × ( x 1 ′ - x 2 ′ ) + 2 × ( x 1 ′ - 100 ) (formula 10)

∂ ∂ x 2 ′ Cost = 2.4 × ( x 1 ′ - x 2 ′ ) + 2 × ( x 1 ′ - 100 ) (formula 11)

Matrix Solving is carried out: AX+B=0 (formula 7) according to above formula

Wherein A is matrix, and B is vector.

2.4 - 1 - 1 2.4 x 1 ′ x 2 ′ + - 100 - 200 = 0 (formula 12)

Obtain x 1'=875/8, x 2'=1125/8, unit is nanometer.

That is, before layout optimization, the line length between the position of its signal source of clock of the positional distance of register LUT is x 2'-x 1'=31.25nm.

It can thus be appreciated that, after the optimization, near 2.08nm before the position ratio optimization of its signal source of clock of the positional distance of register LUT.

In addition, present invention also offers example 2-10, its concrete computation process, as shown in above-mentioned example 1, repeats no more herein.Comparing result before and after optimizing is specifically as shown in table 1.Wherein null represent cloth line iteration reach default maximum quantity still non-cloth lead to.In following each example, cloth line iteration maximum times is 60 times.

Table 1

As can be seen from the data of example 2-10 in upper table, adopt the layout method of Clock Net provided by the invention, after optimization, total line length is respectively than reducing to some extent before, that is, the register that Clock Net connects reduces respectively to some extent to the distance of signal source of clock, relatively gathers between each register that namely same Clock Net connects.Can also see that in fpga chip layout, taking of clock area is reduced to some extent simultaneously, in follow-up wiring process, gauze logical for non-cloth before also can have been led to by cloth based on the layout after optimizing, improve the success ratio of wiring.

Professional should recognize further, in conjunction with unit and the algorithm steps of each example of embodiment disclosed herein description, can realize with electronic hardware, computer software or the combination of the two, in order to the interchangeability of hardware and software is clearly described, generally describe composition and the step of each example in the above description according to function.These functions perform with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.Professional and technical personnel can use distinct methods to realize described function to each specifically should being used for, but this realization should not thought and exceeds scope of the present invention.

The software module that the method described in conjunction with embodiment disclosed herein or the step of algorithm can use hardware, processor to perform, or the combination of the two is implemented.Software module can be placed in the storage medium of other form any known in random access memory (RAM), internal memory, ROM (read-only memory) (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field.

Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only the specific embodiment of the present invention; the protection domain be not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (8)

1. a layout method for fpga chip Clock Net, is characterized in that, described method comprises:
Low clock skew low-skew gauze and ordinary clock gauze is determined in the gauze of fpga chip; Wherein, the gauze of described fpga chip comprises data gauze and Clock Net, and described Clock Net comprises low-skew gauze and ordinary clock gauze;
Whether the unit corresponding to destination inquiring about described ordinary clock gauze is register cell;
When described ordinary clock gauze destination corresponding to unit be register cell time, increase the weight of described ordinary clock gauze;
Process is optimized, the line length of the gauze of the fpga chip after optimization process according to the gauze of described weight to described fpga chip;
According to the line length of the ordinary clock gauze after optimization process, layout processing is carried out to the register cell corresponding to the destination of described ordinary clock gauze.
2. method according to claim 1, is characterized in that, describedly in the gauze of fpga chip, determines that the method for low-skew gauze and ordinary clock gauze specifically comprises:
Obtain in the gauze of described fpga chip, the fan-out amount of every root gauze;
The n root Clock Net that fan-out amount described in described Clock Net of determining is maximum is low-skew gauze; Wherein n is the number of low-skew gauze resource in the hardware resource of described fpga chip;
Determine that other Clock Nets in described Clock Net except described low-skew gauze are ordinary clock gauze.
3. method according to claim 2, is characterized in that, the method for the weight of the described ordinary clock gauze of described increase is specially:
According to the fan-out amount of root gauze every in the gauze of described fpga chip, determine the weight of described every root gauze;
The weight of described ordinary clock gauze is increased respectively the first quantity doubly, to make the ratio of the average weight of described whole Clock Net and the average weight of described total data gauze for preset value.
4. method according to claim 2, is characterized in that, the method for the weight of the described ordinary clock gauze of described increase is specially:
Obtain the weight of every root Clock Net in the ordinary clock gauze of described fpga chip;
Adjust respectively the weight of described every root Clock Net, the ratio of the weight of the ordinary clock gauze before making the weight of the ordinary clock gauze after adjustment and adjusting is preset value.
5. the method according to claim 3 or 4, is characterized in that, the scope of described preset value is between 1 to 2.
6. method according to claim 1, is characterized in that, is describedly optimized process according to the gauze of described weight to described fpga chip, and the line length of the ordinary clock gauze after the process that is optimized is specially:
According to the order of the weight determination optimization process of the every root gauze in the gauze of described fpga chip, the gauze large to weight is preferentially optimized process, be optimized the line length of gauze of the fpga chip after process, comprising the line length of the ordinary clock gauze after optimization process.
7. method according to claim 1, is characterized in that, described optimization process is specially:
Iterative computation is carried out to the weight of root Clock Net every in the gauze of described fpga chip, until in described Clock Net any wire net two end points between the variable quantity of semi-perimeter line length be all less than default variable quantity.
8. method according to claim 1, is characterized in that, when the non-register cell of the unit that the destination of described ordinary clock gauze is corresponding, does not then change the weight of described ordinary clock gauze.
CN201310608638.9A 2013-11-26 2013-11-26 The layout method of fpga chip Clock Net CN104679529B (en)

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CN106934080A (en) * 2015-12-29 2017-07-07 京微雅格(北京)科技有限公司 A kind of high-performance clock signal drives the layout method of register
CN109753721A (en) * 2018-12-29 2019-05-14 广东高云半导体科技股份有限公司 FPGA device placement-and-routing display methods, device, equipment and storage medium

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US20060090153A1 (en) * 2004-10-22 2006-04-27 Pei-Hsin Ho Method and apparatus for reducing power consumption in an integrated circuit chip
CN101187957A (en) * 2006-10-31 2008-05-28 国际商业机器公司 System and method for designing multiple latch unit layout of integrated circuit public clock domain clock aware placement
CN103136386A (en) * 2011-11-25 2013-06-05 中国科学院微电子研究所 Wiring method of field programmable gate array (FPGA) chip

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US20030106036A1 (en) * 2001-12-03 2003-06-05 Katsushi Aoki Wiring route determining apparatus, group determining apparatus, wiring route determining program storing medium and group determining program storing medium
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CN101187957A (en) * 2006-10-31 2008-05-28 国际商业机器公司 System and method for designing multiple latch unit layout of integrated circuit public clock domain clock aware placement
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