CN117807953B - Chip delay optimization method and device, computer equipment and storage medium - Google Patents
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Abstract
The invention relates to the technical field of chip design, and discloses a chip delay optimization method, a device, computer equipment and a storage medium, wherein the method comprises the following steps: obtaining a netlist obtained based on user design synthesis and a layout result obtained after layout; selecting seed nodes from the netlist; aiming at each seed node, carrying out expansion operation to obtain an expansion set of the seed node, wherein the expansion set comprises the seed node and a target node obtained through the expansion operation; re-synthesizing the nodes in the expansion set; in the case where resynthesis is effective, then a progressive layout is performed based on the alternate netlists of the expanded set generated by the resynthesis. The invention optimizes the netlist and the layout result of the chip in a global view angle, compares the netlist before optimization, and has a wider scope of application compared with a common scheme because a plurality of regional netlist changes exist in the optimized netlist. Delays that are not optimized can be largely explored after placement is acted upon.
Description
Technical Field
The present invention relates to the field of chip design technologies, and in particular, to a method and apparatus for optimizing chip delay, a computer device, and a storage medium.
Background
Critical path delay is a core indicator used to determine the performance of mapping a given user design to a field programmable gate array (Field Programmable GATE ARRAY, FPGA) chip. Mapping user designs to FPGA chips often requires the use of specialized electronic design automation (Electronic Design Automation, EDA) tools that typically contain synthesis, placement, routing, bitstream generation, etc., all of which are optimized with respect to delay information for critical paths (paths that can be simply understood as the longest delays). However, the information obtained by each link has a difference, and the interaction cost between links is relatively high, so that the optimization effect achieved by the comprehensive, layout and wiring links is limited, and the delay of the key path has a great optimization space.
Disclosure of Invention
In view of the above, the invention provides a method, a device, a computer device and a storage medium for optimizing chip delay, so as to solve the problem of limited delay optimization of an FPGA chip.
In a first aspect, the present invention provides a method for optimizing chip delay, the method comprising:
Obtaining a netlist obtained based on user design synthesis and a layout result obtained after layout;
Selecting seed nodes from the netlist;
Aiming at each seed node, carrying out expansion operation to obtain an expansion set of the seed node, wherein the expansion set comprises the seed node and a target node obtained through the expansion operation;
Re-synthesizing the nodes in the expansion set;
In the case where resynthesis is effective, then a progressive layout is performed based on the alternate netlists of the expanded set generated by the resynthesis.
In an alternative embodiment, selecting a seed node from the netlist includes:
Obtaining the margin of each input pin of each node in the netlist;
according to the margin of the input pin of the node, a seed node is selected.
In an alternative embodiment, selecting a seed node according to a margin of an input pin of the node includes:
acquiring target parameters according to the margin of each input pin of the node;
and determining whether the node is a seed node according to the size relation between the target parameter and the first preset threshold value.
In an alternative embodiment, the target parameter is derived based on the ratio of the margin of the input pins of a node to the maximum margin of all input pins of all nodes in the netlist.
In an optional embodiment, before performing the expansion operation to obtain the expansion set of the seed nodes for each seed node, the method further includes:
Obtaining the income of each seed node;
Sorting the seed nodes according to the benefits;
Performing an expansion operation on each seed node to obtain an expansion set of the seed nodes, including:
and performing expansion operation on the seed nodes according to the sequence.
In an alternative embodiment, the benefit of the seed node is calculated from the margin of the input pins of the seed node.
In an alternative embodiment, for each seed node, performing an expansion operation to obtain an expanded set of seed nodes includes:
Acquiring an input node of a seed node;
Judging whether the input node meets a preset limiting condition or not;
if yes, taking the input node as a target node to add into the expansion set;
Judging whether each input node of each target node in the expansion set meets a preset limiting condition, and adding the input nodes into the expansion set until all nodes in the input direction of the seed node are traversed or no input nodes meeting the preset limiting condition exist under the condition that the preset limiting condition is met.
In an alternative embodiment, the preset limiting conditions include a first condition, a second condition and a third condition, and any one of the second condition and the third condition is satisfied while the first condition is satisfied, that is, the preset limiting condition is satisfied;
The first condition is: the degradation binary decision diagram constructed by the extension set is smaller than the limit range;
The second condition is: all output nodes are inputs of the expansion set;
The third condition is: the difference between the margin of all input pins and the margin of the seed node is smaller than a second preset threshold.
In an alternative embodiment, the re-synthesizing the nodes in the extended set includes:
Acquiring a degradation binary decision diagram corresponding to the expansion set and a margin of the expansion set;
dividing the degraded binary decision diagram to obtain two new binary decision diagrams;
In the case that only one new binary decision diagram is capable of generating a new lookup table, determining an update margin of the extended set based on the newly generated lookup table;
judging whether the update margin meets margin constraint;
if the binary decision diagram is not satisfied, continuing to divide the other new binary decision diagram until the binary decision diagrams obtained by division can generate a new lookup table;
if yes, repartitioning the degraded binary decision diagram.
In an alternative embodiment, the margin constraint is that the update margin is less than the minimum margin of the input pins of the seed nodes in the expanded set.
In an alternative embodiment, the update margin is the difference between the minimum margin of the input pins of the newly generated node and the expected delay introduced by the introduction of a new node.
In an alternative embodiment, partitioning the degradation binary decision graph includes:
reordering all variables in the degraded binary decision diagram;
and dividing the degraded binary decision diagram after the variable reordering.
In an alternative embodiment, after progressive placement based on the alternate netlist of the resynthesized set of extensions, further comprising:
acquiring the delay of a new critical path after progressive layout;
And under the condition that the delay of the new critical path is larger than the delay of the critical path before optimization, discarding the optimization result.
In an alternative embodiment, after progressive placement based on the alternate netlist of the resynthesized set of extensions, further comprising:
judging whether the current optimization times reach preset iteration times or not;
and under the condition that the preset iteration times are not reached, re-optimizing the whole netlist based on the re-synthesis.
In a second aspect, the present invention provides a chip delay optimizing apparatus, the apparatus comprising:
The acquisition module is used for acquiring a netlist obtained after user design synthesis and a layout result obtained after layout;
a selection module for selecting seed nodes from the netlist;
the expansion module is used for carrying out expansion operation on each seed node to obtain an expansion set of the seed node, wherein the expansion set comprises the seed node and a target node obtained through the expansion operation;
the re-synthesis module is used for re-synthesizing the nodes in the expansion set;
And the layout module is used for carrying out progressive layout based on the replaced netlist of the expansion set generated by the resynthesis under the condition that the resynthesis is effective.
In a third aspect, the present invention provides a computer device comprising: the memory and the processor are in communication connection with each other, the memory stores computer instructions, and the processor executes the computer instructions, so that the chip delay optimization method of the first aspect or any implementation manner corresponding to the first aspect is executed.
In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon computer instructions for causing a computer to execute the chip delay optimization method of the first aspect or any of the embodiments corresponding thereto.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of the basic process from user design to enablement of an FPGA chip;
FIG. 2 is a flow chart of a method for optimizing chip latency according to an embodiment of the present invention;
FIG. 3 is a flow chart of another chip delay optimization method according to an embodiment of the invention;
FIG. 4 is a schematic diagram of the basic process of enabling from user design to an FPGA chip according to an embodiment of the invention;
FIG. 5 is a schematic diagram of a portion of LUT nodes in a netlist;
FIG. 6 is a schematic diagram of a binary decision diagram;
FIG. 7 is a schematic diagram of a degraded binary decision diagram of the binary decision diagram shown in FIG. 6;
FIG. 8 is a schematic flow diagram of a resynthesis according to an embodiment of the invention;
FIG. 9 is a schematic diagram of an extended set according to an embodiment of the invention;
FIG. 10a is a schematic diagram of a BDD according to an embodiment of the invention;
FIG. 10b is a schematic diagram of BDDs corresponding to the set of constraints partitioned by the BDDs of FIG. 10 a;
FIG. 10c is a schematic diagram of BDDs corresponding to free sets partitioned by the BDDs shown in FIG. 10 a;
FIG. 11 is a block diagram of a chip delay optimizing apparatus according to an embodiment of the present invention;
Fig. 12 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The enabling from user design to FPGA chip often requires integrating, placing, wiring, generating a bit stream, see in particular fig. 1. Wherein generating a bit stream can be understood simply as converting the results from the previous steps into results that enable the FPGA chip, without involving optimization operations. The synthesis stage is to convert the user design into a netlist (which can be simply understood as a circuit representation), the layout stage maps each node on the netlist obtained in the synthesis stage to a specific position of the FPGA chip, and the routing stage determines a specific connection manner between pins on the FPGA chip based on the position of the layout stage and the pin connection relationship in the netlist. The three stages all involve optimization of critical path delay, but one-way information transmission of the three stages can be seen, and the optimization means of each stage has larger limitation, so that a large optimization space exists.
Some optimization schemes aiming at FPGA chip delay in the related art are often aimed at one or two nodes on a critical path, or based on node replication or function reconstruction, and the defect of the mode is that each modification can only improve the performance of the aimed critical path, meanwhile, the view angle is only a local view angle, and a considerable part of optimization space is not explored. In addition, the delay information is not completely accurate because the optimization scheme is applied before winding, the situation that the delay is not optimized after winding possibly exists, and the result after winding is difficult to ensure because the optimization range of the method is smaller and only aims at a few key paths.
The embodiment of the invention provides a chip delay optimization method, which optimizes the netlist and the layout result of a chip from a global view angle, compares the netlist before the optimization, and has a wider scope of application compared with a common scheme because a plurality of regional netlist changes exist in the optimized netlist. Delays that are not optimized can be largely explored after placement is acted upon.
In accordance with an embodiment of the present invention, there is provided a chip delay optimization method embodiment, it being noted that the steps shown in the flowchart of the figures may be performed in a computer system, such as a set of executable computer instructions, and, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in an order other than that shown or described herein.
In this embodiment, a chip delay optimization method is provided, which may be used in a computer device, where the computer device may run an EDA tool, fig. 2 is a flowchart of a chip delay optimization method according to an embodiment of the present invention, and fig. 3 is a flowchart of another chip delay optimization method according to an embodiment of the present invention, where the flowchart includes the following steps, as shown in fig. 2 and 3:
Step S201, obtaining a netlist obtained after user design synthesis and a layout result obtained after layout.
Referring to fig. 4, the present embodiment adds a delay optimization link between the layout and wiring links, which has the advantage of obtaining more accurate delay information compared to the comprehensive link and less operation complexity and running time cost compared to the wiring link.
The input of the embodiment is a synthesized netlist and a layout result after layout, the netlist can be simply understood to be composed of combined logic nodes and sequential logic nodes, the scheme is mainly aimed at lookup table (LUT) nodes, and if all nodes are LUT nodes without special description, the layout result can be simply understood to be a mapping relation from the nodes on the netlist to corresponding positions on an FPGA chip.
Step S202, selecting seed nodes from the netlist.
In some specific embodiments, step S202 includes:
Step S2021, obtaining the margin of each input pin of each node in the netlist. Margin, can be described simply as: margin = required delay-delay, each pin has its corresponding margin, meaning the difference between the longest delay that is acceptable (required delay) and the existing delay. The margin for all pins on the critical path is 0.
In step S2022, a seed node is selected according to the margin of the input pin of the node.
In other alternative embodiments, the seed node may be selected in other ways, such as randomly, etc.
Specifically, step S2022 includes:
Step S20221, obtaining a target parameter r i according to the margin of each input pin of the node;
in step S20222, it is determined whether the node is a seed node according to the magnitude relation between the target parameter and the first preset threshold.
The target parameter is obtained based on the ratio of the margin of the input pins of the node to the maximum margin of all the input pins of all the nodes in the netlist. For example, the target parameter r i is calculated by:
Where s i is the margin of input pin i of the node and s max is the largest margin of the margins of all input pins of all nodes in the netlist.
In this embodiment, the seed node is selected by traversing all nodes in the netlist, and if any one of the input pins i exists, the target parameter r i is smaller than the first preset threshold, the node is selected as the seed node.
Step S203, for each seed node, performing an expansion operation to obtain an expansion set of the seed node, wherein the expansion set comprises the seed node and a target node obtained through the expansion operation.
In some specific embodiments, before step S203, that is, before performing the expansion operation for each seed node to obtain the expanded set of seed nodes, the method further includes:
step one, obtaining the income (gain) of each seed node;
Step two, sorting the seed nodes according to the benefits;
In step S203, for each seed node, the seed nodes are expanded sequentially.
In this embodiment, the expansion operation for the seed nodes, the resynthesis based on the expansion set and the progressive layout are performed for one seed after the execution for the other seed is completed. And after the above operation is performed on one seed node, the other seed nodes are affected. Therefore, the thought of a greedy algorithm is adopted, and seed nodes with the highest benefits, which are not affected in the sorting, are preferentially processed each time. The seed nodes with high yield can be selected preferably instead of randomly, so that the overall optimization performance is guaranteed.
The gain of the seed node is calculated according to the margin of the input pin of the seed node. The method comprises the following steps:
Gv＝(1-rmin)α(ravg-rmin)
g v is the benefit of seed node v;
α is a constant set, for example 4;
rmin＝min{ri|i∈input(v)}；
Σ i∈input(v)ri represents the sum of the target parameters of the input pins of the seed node v, sizeofinput (v) represents the number of input pins of the seed node v.
In this embodiment, the margin-based seed node selection method and the sequencing method thereof can ensure that the critical path is optimized.
In some specific embodiments, step S203, namely, performing an expansion operation for each seed node to obtain an expansion set of the seed nodes, includes:
step S2031, obtaining an input node of a seed node;
step S2032, judging whether the input node meets a preset limitation condition;
Step S2033, if yes, adding the input node as a target node into the expansion set;
if not, not adding the expansion set;
Step S2034, determining whether each input node of each target node in the extension set meets a preset constraint condition, and adding the input node to the extension set until all nodes in the input direction of the seed node are traversed or no input node meeting the preset constraint condition is present.
In this embodiment, the expansion method includes that a seed node is first used as a root node, then the seed node is traversed gradually towards the input direction, nodes meeting the requirements are added into an expansion range, and a set formed by the root node and nodes in all expansion ranges is called an expansion set of the root node. Referring to fig. 5, assume that node 0 is the root node, and in the expansion process, input nodes, namely node 1 and node 2, are considered first, and if a constraint condition (i.e., a preset) is satisfied, an expansion set is added. Assuming that node 1 is added to the extension set, it is further determined whether the input node of node 1, i.e., node 3 and node 4, satisfies the condition of adding to the extension set, and if so, adding to the extension set. The step-by-step traversal is performed according to this rule until the input or timing nodes to the entire netlist are traversed, or there are no more nodes that meet the constraint.
The preset limiting conditions comprise a first condition, a second condition and a third condition, and any one of the second condition and the third condition is met when the first condition is met, namely the preset limiting condition is met;
The first condition is: the degradation binary decision diagram constructed by the extension set is smaller than the limit range; if the node which is currently judged whether to add the extension combination is added into the extension set, the degradation binary decision diagram constructed by the extension set is smaller than the limit range;
The second condition is: all output nodes are inputs of the expansion set;
That is, if the input node of the target node in the extension set has all the output nodes that are inputs of the target node (not necessarily the same target node) in the extension set, the input node satisfies the second condition;
The third condition is: the difference between the margin of all input pins and the margin of the seed node is smaller than a second preset threshold. In other words, if the input node of the target node in the extension set has a margin of all its input pins close enough to the margin of the root node, for example, the second preset threshold may be set to 0.05ns, then the input node satisfies the third condition.
It should be noted that if there is an output of a node added to the extension set that does not point to the extension set, for example, if the extension set is node 0 and node 1 in fig. 5, and then adding node 3 to the extension set, it is found that there is an output of node 3 that points to the outside of the extension set, which means that there is an output of a node dependent node 3 outside of the other extension set, in this case, it is necessary to copy node 3.
Step S204, the nodes in the expansion set are recombined.
The re-synthesis procedure is entered after completing node expansion, and the re-synthesis method of this embodiment relies on a Binary Decision Diagram (BDD). In the process of constructing the extension set, BDDs corresponding to the extension set can be synchronously constructed. As described above, the nodes in this embodiment are LUT nodes, which are essentially a boolean function, in the form of a truth table, for example, a three-input LUT may represent any three-input boolean function in the form of an eight-bit truth table. For a simple example, a three-input boolean function is a+b+c, then its truth table is: 1000000.BDD is another representation of the function that is operationally advantageous and is selected for use in this embodiment. The form of the boolean function described above, after being represented by BDD, can be referred to fig. 6. In the figure, the solid line represents node 1, and the broken line represents node 0. It is evident, however, that the size of BDDs will increase exponentially as variables increase, however, such BDDs tend to undergo a degradation process, becoming a binary decision diagram of degradation as shown in fig. 7. It can be seen that the downgrade may downgrade a BDD (fig. 6) that would otherwise require 7 nodes to a BDD (fig. 7) that would require only 3 nodes. There is already a mature method for degradation of BDD, which is identified as degraded BDD in the subsequently mentioned BDD unless specifically stated. The size of the degraded BDD is strongly related to the function it represents and the order of input, and therefore, in order to define the size of the BDD, the definition of the size of the BDD is added in the process of constructing the expansion set.
In some embodiments, referring to fig. 8, step S204, namely, re-integrating the nodes in the extended set, includes:
step S2041, obtaining a degradation binary decision diagram corresponding to an expansion set and a margin of the expansion set;
The input of the recombination is the built BDD in the expansion process. In addition, the margin of the input pins of the expansion set can be synchronously updated in the process of gradually adding the nodes into the expansion set, the recalculated margin is called an update margin, and the calculation of the update margin is based on the fact that the whole expansion set is regarded as one node. Taking fig. 5 as an example, only the root node 0 exists in the whole extension set initially, and at this time, the whole extension set has two input pins, namely, two input pins of the node 0, and the margins of the two input pins of the node 0 are respectively the margins of the two input pins of the node 0. Node 1 is then added to the expanded set, at which point the input pins of the expanded set become the two input pins of node 1, and one input pin of node 0, see fig. 9. Since the entire extended set is treated as one node, the margin of both input pins of node 1 is updated, and the input pin margin of node 0 is unchanged. The method for calculating the update margin comprises the following steps:
s′＝s+d(a)+d(a,w)
where s' is an update margin, s is a margin of one input pin of a newly added node a, a is a node newly added to the extension set, w is a node on which the node a adds to the extension set, taking fig. 9 as an example, a is node 1, and w is node 0.d (a) is the delay of node 1 and d (a, w) is the delay of the shortest path between node 1 and node 0.
Step S2042, dividing the degraded binary decision diagram to obtain two new binary decision diagrams;
In some specific embodiments, step S2042, namely partitioning the degradation binary decision graph, includes:
step S20421, reordering all variables in the degraded binary decision diagram;
Step S20422, dividing the degraded binary decision diagram after the variable reordering.
In this embodiment, when the BDD input is taken during the recombination, all the variables in the BDD need to be reordered first, and the meaning of the ordering is to obtain the BDD that is more beneficial to the processing and obtain the better processing result. The ordering is the order in which the input variables are swapped when represented in the BDD. For example, the order of the input variables in fig. 7 is abc, and if the order is cba, the BDD obtained is the result of exchanging the positions of the node c and the node a in fig. 7. Of course, the change of the input variable sequence is not only the exchange of node positions, but also more processing is involved, and the processing can be completed by mature methods, so that the optimal variable sequence required by the scheme and the BDD after the sequence change can be obtained based on the application and the expansion of the mature methods.
Step S2043, in the case that only one new binary decision diagram can generate a new lookup table, determining an update margin of the expansion set based on the newly generated lookup table;
The re-integration requires partitioning the BDD, each of which can generate a constraint set and a free set, and reference is made specifically to fig. 10a, 10b and 10c. Fig. 10a depicts a boolean function:
after division, the variables in fig. 10b are constraint sets, and the variables in fig. 10c are free sets.
It can be seen from fig. 10b and 10c that after the BDD of fig. 10a is divided, it can be re-divided into two new BDDs, each representing a new boolean function. The two newly generated functions are respectively:
g＝(p+q+r)
each division may convert the BDD formed by the constraint set of the division into a new LUT, that is, a new LUT is formed after each division, and the margin of the expansion set calculated before in this embodiment needs to be updated.
In some embodiments, the update margin is the difference between the minimum margin of the input pins of the newly generated node and the expected delay introduced by the introduction of a new node. The calculation mode of the update margin is specifically as follows:
s′(g)＝min{s′(j)|j∈input(g)}-davg
Wherein, node g is the newly generated node, j is the input pin of node g, s' (g) is the update margin of the pin of node g as the input node connected to the expansion set, and d avg is the expected delay brought by introducing a new node. The expected delay d avg is calculated by adding the delays of all nodes except the root node and the edges in the extended set and then dividing the added delays by the number of nodes except the root node. Taking fig. 9 as an example, assuming that the extension set includes node 0, node 1, and node 2, the calculation method of d avg is as follows:
d (v 1) is the delay of node 1, d (v 2) is the delay of node 2, d (v 1, v 0) is the delay of the edge between node 1 and node 0, and d (v 2, v 0) is the delay of the edge between node 2 and node 0.
The margin of the extended set is calculated here in order to determine whether the margin of the extended set satisfies the margin constraint as follows.
Step S2044, judging whether the update margin meets margin constraint;
specifically, the margin constraint is that the update margin is less than the minimum margin of the input pins of the seed node (i.e., root node) in the expanded set.
Step S2045, if not, continuing to divide the other new binary decision diagram until the binary decision diagrams obtained by division can generate a new lookup table, namely the division is completed;
Step S2046, if yes, repartitioning the degraded binary decision diagram. That is, after dividing the BDD each time and generating a new LUT based on the constraint set obtained by the division, if there are variables (i.e., variables in the free set) that have not been mapped to the LUT in the BDD, and the margin (updated) of the extended set has satisfied the margin constraint, it may be determined that the current round of division can no longer satisfy the delay requirement, and thus restart a round of division. Of course, the new round of division results in a different division result than the current or historical division result.
If no new partitioning results are available, i.e. no other partitioning is done, or all partitioning is traversed to completion, i.e. the degraded binary decision graph is completely converted into LUT, then the optimization of the expanded set of seed nodes as root node is abandoned and the next seed node is started to be optimized.
The essential goal of the resynthesis is to gradually convert a BDD into a LUT by partitioning, while the maximum input of the LUT tends to have an upper limit, taking an upper input limit of 4 as an example. The BDD shown in fig. 10a, f needs to be implemented by six variables of p, q, r, s, t, u before division, and it is obvious that one LUT with 4 inputs cannot meet the requirement, and then the expression of the function g and the new f is extracted through division. The function g has only three variables and the new f has only 4 variables and can therefore be implemented by one LUT4, respectively. It can be seen that the partitioning and iterative partitioning process is essentially a stepwise LUT extraction process, where each partitioning can convert a BDD made up of a set of constraints of the partitioning into a LUT and reduce the variables in the remaining BDDs, ultimately converting a BDD into a series of LUTs by stepwise partitioning. Of course, there are many ways to divide BDD into LUTs, and any suitable way may be selected.
The embodiment optimizes the netlist of the extended set region based on re-synthesis, and simultaneously, the update margin of the extended set is added to limit the delay increase in the LUT generation process.
In step S205, in the case where the resynthesis is effective, a progressive layout is performed based on the replaced netlist of the expansion set generated by the resynthesis.
Progressive layout is a function provided in the EDA tool that functions in that corresponding modifications to the layout result based on the modification of the netlist generate a new layout result.
The chip delay optimization method provided by the embodiment does not act in the main link of the EDA tool before wiring after layout. Compared with a general optimization method aiming at a critical path, the method selects a delay optimization method which traverses the whole netlist from a global view to select a plurality of seed nodes to be optimized, then carries out local expansion based on the seed nodes, and carries out resynthesis on a whole expansion area based on an expansion set obtained after expansion. Compared with the netlist before optimization, the optimized netlist often has a plurality of regional netlist changes, and compared with a common scheme, the netlist has a wider application range. The embodiment can greatly reduce the failure condition of the optimization after the wiring link, can better ensure the result after the winding, and can greatly discover the delay which is not optimized after the layout is acted.
In some embodiments, after progressive placement based on the alternate netlist of the resynthesized set of extensions, further comprising:
acquiring the delay of a new critical path after progressive layout;
And under the condition that the delay of the new critical path is larger than the delay of the critical path before optimization, discarding the optimization result.
In this embodiment, a timing analysis tool in the EDA tool is called to obtain the delay of the critical path before optimization, and the timing analysis tool is called again to obtain the delay of the new critical path after the progressive layout is completed, if the delay of the new critical path is smaller than the delay of the critical path before optimization, the optimization is determined to be effective, so that the optimized netlist and layout result are reserved, otherwise, the optimization result is abandoned. The optimization processing can be ensured not to degrade the result before the wiring link, and the delay after the wiring link can be ensured not to be degraded to a great extent.
That is, the present embodiment examines the netlist and the layout before the change of the netlist and the layout is effected in each optimization iteration, and only the critical path delay obtained by the timing analysis is kept smaller than the critical path delay before the change. The method is characterized in that the time sequence analysis is carried out immediately after the optimization, and the obtained result is not poorer than that before the optimization.
In some embodiments, after progressive placement based on the alternate netlist of the resynthesized set of extensions, further comprising:
judging whether the current optimization times reach preset iteration times or not;
and under the condition that the preset iteration times are not reached, re-optimizing the whole netlist based on the re-synthesis. The entire netlist after resynthesis is referred to herein as the netlist that was last optimized to be valid and remains.
In this embodiment, after optimization of one seed node is completed, the next seed node is optimized, until the complete optimization is calculated once after all seed nodes are traversed. After completing one complete optimization, judging whether the iteration times specified by the user are reached, and if the iteration times are not reached, performing new optimization again based on the optimized netlist and the layout result, and outputting the final netlist and the layout result after the iteration times are reached.
The embodiment also provides a chip delay optimizing device, which is used for realizing the above embodiment and the preferred implementation manner, and the description is omitted. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
The present embodiment provides a chip delay optimizing apparatus, as shown in fig. 11, including:
an obtaining module 1101, configured to obtain a netlist obtained based on user design synthesis and a layout result obtained after layout;
A selection module 1102 for selecting seed nodes from the netlist;
The expansion module 1103 is configured to perform an expansion operation on each seed node to obtain an expansion set of the seed node, where the expansion set includes the seed node and a target node obtained by the expansion operation;
a re-synthesis module 1104 for re-synthesizing the nodes in the expansion set;
A layout module 1105 for performing progressive layout based on the alternate netlists of the expanded set generated by the resynthesis in the event that the resynthesis is valid.
In some alternative embodiments, the selection module 1102 includes:
the margin obtaining unit is used for obtaining the margin of each input pin of each node in the netlist;
And the seed node selection unit is used for selecting the seed node according to the margin of the input pin of the node.
In some alternative embodiments, the seed node selection unit comprises:
a target parameter obtaining subunit, configured to obtain a target parameter according to a margin of each input pin of the node;
and the seed node judging subunit is used for determining whether the node is a seed node according to the magnitude relation between the target parameter and the first preset threshold value.
In some alternative embodiments, the target parameter is derived based on the ratio of the margin of the input pins of a node to the maximum margin of all input pins of all nodes in the netlist.
In some alternative embodiments, the apparatus further comprises:
the profit obtaining module is used for obtaining the profit of each seed node;
The seed node ordering module is used for ordering the seed nodes according to benefits;
the expansion module 1103 is specifically configured to sequentially perform expansion operation on the seed nodes.
In some alternative embodiments, the benefit of the seed node is calculated from the margin of the input pins of the seed node.
In some alternative embodiments, the expansion module 1103 includes:
An input node obtaining unit for obtaining an input node of the seed node;
The first judging unit is used for judging whether the input node meets a preset limiting condition or not;
the expansion unit is used for adding the input node serving as a target node into the expansion set under the condition that the input node meets the preset limiting condition;
The second judging unit is used for judging whether each input node of each target node in the expansion set meets a preset limiting condition or not; the expansion unit is further used for adding the input node into the expansion set under the condition that the input node of the target node meets the preset limiting condition.
In some optional embodiments, the preset limiting conditions include a first condition, a second condition and a third condition, and any one of the second condition and the third condition is satisfied while the first condition is satisfied, that is, the preset limiting condition is satisfied;
The first condition is: the degradation binary decision diagram constructed by the extension set is smaller than the limit range;
The second condition is: all output nodes are inputs of the expansion set;
The third condition is: the difference between the margin of all input pins and the margin of the seed node is smaller than a second preset threshold.
In some alternative embodiments, the re-synthesis module 1104 includes:
The acquisition unit is used for acquiring a degradation binary decision graph corresponding to the expansion set and the margin of the expansion set;
the dividing unit is used for dividing the degraded binary decision diagram to obtain two new binary decision diagrams;
a margin updating unit, configured to determine an update margin of the extension set based on the newly generated lookup table in a case where only one new binary decision diagram can generate the new lookup table;
A third judging unit for judging whether the update margin satisfies the margin constraint;
The dividing unit is further used for continuously dividing the other new binary decision graph until the binary decision graph obtained by dividing can generate a new lookup table under the condition that the updating margin does not meet the margin constraint;
The dividing unit is also used for re-dividing the degradation binary decision graph under the condition that the update margin meets the margin constraint.
In some alternative embodiments, the margin constraint is that the update margin is less than the minimum margin of the input pins of the seed nodes in the expanded set.
In some alternative embodiments, the update margin is the difference between the minimum margin of the input pins of the newly generated node and the expected delay introduced by the introduction of a new node.
In some alternative embodiments, the partitioning unit includes:
The variable ordering subunit is used for reordering all variables in the degradation binary decision diagram;
And the dividing subunit is used for dividing the degraded binary decision diagram after the variable reordering.
In some alternative embodiments, the apparatus further comprises:
the delay acquisition module is used for acquiring the delay of the new key path after the progressive layout;
and the discarding module is used for discarding the optimizing result under the condition that the delay of the new critical path is larger than the delay of the critical path before the optimizing.
In some alternative embodiments, the apparatus further comprises:
The judging module is used for judging whether the current optimization times reach the preset iteration times or not;
and the iteration module is used for optimizing again based on the whole re-synthesized netlist under the condition that the preset iteration times are not reached.
Further functional descriptions of the above respective modules, units and sub-units are the same as those of the above corresponding embodiments, and are not repeated here.
The chip delay optimizing device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application SPECIFIC INTEGRATED Circuit) Circuit, a processor and a memory that execute one or more software or firmware programs, and/or other devices that can provide the above functions.
The embodiment of the invention also provides computer equipment, which is provided with the chip delay optimizing device shown in the figure 11.
Referring to fig. 12, fig. 12 is a schematic structural diagram of a computer device according to an alternative embodiment of the present invention, as shown in fig. 12, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 12.
The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.
Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform a method for implementing the embodiments described above.
The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.
The computer device further comprises input means 30 and output means 40. The processor 10, memory 20, input device 30, and output device 40 may be connected by a bus or other means, for example in fig. 12.
The input device 30 may receive input numeric or character information and generate key signal inputs related to user settings and function control of the computer apparatus, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, a pointer stick, one or more mouse buttons, a trackball, a joystick, and the like. The output means 40 may include a display device, auxiliary lighting means (e.g., LEDs), tactile feedback means (e.g., vibration motors), and the like. Such display devices include, but are not limited to, liquid crystal displays, light emitting diodes, displays and plasma displays. In some alternative implementations, the display device may be a touch screen.
The computer device also includes a communication interface for the computer device to communicate with other devices or communication networks.
The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.
Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.
Claims (11)
1. A method for optimizing chip delay, the method comprising:
Obtaining a netlist obtained based on user design synthesis and a layout result obtained after layout;
selecting seed nodes from the netlist;
performing expansion operation on each seed node to obtain an expansion set of the seed node, wherein the expansion set comprises the seed nodes and target nodes obtained through the expansion operation;
Re-synthesizing the nodes in the expansion set;
in the case that the resynthesis is effective, then performing a progressive layout based on the substitute netlist of the expanded set generated by the resynthesis;
the expanding operation is performed on each seed node to obtain an expanded set of the seed nodes, including:
acquiring an input node of the seed node;
Judging whether the input node meets a preset limiting condition or not;
if yes, the input node is taken as the target node to be added into the expansion set;
judging whether each input node of each target node in the expansion set meets the preset limiting condition, and adding the input node into the expansion set until all nodes in the input direction of the seed node are traversed or no input nodes meeting the preset limiting condition exist;
The preset limiting conditions comprise a first condition, a second condition and a third condition, and any one of the second condition and the third condition is met when the first condition is met, namely the preset limiting condition is met;
The first condition is: the degradation binary decision graph constructed by the extension set is smaller than a limited range;
The second condition is: all output nodes are inputs of the expansion set;
the third condition is: the difference value between the margin of all input pins and the margin of the seed node is smaller than a second preset threshold value;
the re-integrating the nodes in the extended set includes:
Acquiring a degradation binary decision graph corresponding to the expansion set and a margin of the expansion set;
dividing the degradation binary decision diagram to obtain two new binary decision diagrams;
In case only one of the new binary decision diagrams is able to generate a new look-up table, determining an update margin of the extended set based on the newly generated look-up table;
Judging whether the update margin meets margin constraint;
if not, continuing to divide the other new binary decision diagram until the binary decision diagrams obtained by division can generate a new lookup table;
if yes, dividing the degradation binary decision diagram again;
The margin constraint is that the update margin is less than a minimum margin of input pins of the seed node in the expanded set;
The update margin is the difference between the minimum margin of the input pins of the newly generated node and the expected delay caused by introducing a new node; the calculation mode of the expected delay is to add the delay of all nodes except the root node and the edge in the extension set and then divide the delay by the number of nodes except the root node;
the dividing the degradation binary decision diagram comprises the following steps:
reordering all variables in the degraded binary decision graph;
and dividing the degraded binary decision diagram after the variable reordering.
2. The method of claim 1, wherein the selecting a seed node from the netlist comprises:
Obtaining the margin of each input pin of each node in the netlist;
and selecting the seed node according to the margin of the input pin of the node.
3. The method of claim 2, wherein the selecting the seed node according to the margin of the input pins of the node comprises:
Acquiring target parameters according to the margin of each input pin of the node;
And determining whether the node is the seed node according to the size relation between the target parameter and a first preset threshold value.
4. A method according to claim 3, wherein the target parameter is derived based on a ratio of a margin of input pins of the node to a maximum margin of all input pins of all the nodes in the netlist.
5. The method of claim 1, wherein before performing the expanding operation to obtain the expanded set of the seed nodes for each of the seed nodes, further comprises:
obtaining the income of each seed node;
Sorting the seed nodes according to the benefits;
Performing an expansion operation on each seed node to obtain an expansion set of the seed node, including:
and carrying out the expansion operation on the seed nodes in sequence.
6. The method of claim 5, wherein the profit of the seed node is calculated from a margin of an input pin of the seed node.
7. The method of claim 1, wherein the incremental placement of the substitute netlist based on the set of extensions generated by the resynthesis further comprises:
acquiring the delay of a new critical path after progressive layout;
And discarding the optimizing result under the condition that the delay of the new critical path is larger than the delay of the critical path before the optimizing.
8. The method of claim 1 or 7, wherein the incremental layout based on the substitute netlist of the set of extensions generated by resynthesis is followed by:
judging whether the current optimization times reach preset iteration times or not;
and under the condition that the preset iteration times are not reached, re-optimizing the whole netlist based on the re-synthesis.
9. A chip delay optimizing apparatus, the apparatus comprising:
The acquisition module is used for acquiring a netlist obtained after user design synthesis and a layout result obtained after layout;
a selection module for selecting seed nodes from the netlist;
the expansion module is used for carrying out expansion operation on each seed node to obtain an expansion set of the seed node, wherein the expansion set comprises the seed nodes and target nodes obtained through the expansion operation;
the re-synthesis module is used for re-synthesizing the nodes in the expansion set;
The layout module is used for carrying out progressive layout based on the replaced netlist of the expansion set generated by the resynthesis under the condition that the resynthesis is effective;
Wherein, the expansion module includes:
an input node obtaining unit, configured to obtain an input node of the seed node;
The first judging unit is used for judging whether the input node meets a preset limiting condition or not;
the expansion unit is used for adding the input node serving as the target node into the expansion set under the condition that the input node meets a preset limiting condition;
A second judging unit, configured to judge whether each input node of each target node in the extended set meets the preset constraint condition; the expansion unit is further used for adding the input node of the target node into the expansion set under the condition that the input node meets the preset limiting condition;
The preset limiting conditions comprise a first condition, a second condition and a third condition, and any one of the second condition and the third condition is met when the first condition is met, namely the preset limiting condition is met;
The first condition is: the degradation binary decision graph constructed by the extension set is smaller than a limited range;
The second condition is: all output nodes are inputs of the expansion set;
the third condition is: the difference value between the margin of all input pins and the margin of the seed node is smaller than a second preset threshold value;
The re-synthesis module comprises:
The acquisition unit is used for acquiring a degradation binary decision graph corresponding to the expansion set and the margin of the expansion set;
the dividing unit is used for dividing the degradation binary decision graph to obtain two new binary decision graphs;
A margin updating unit, configured to determine an update margin of the extended set based on a newly generated lookup table, in a case where only one new binary decision diagram can generate the new lookup table;
a third judging unit configured to judge whether the update margin satisfies a margin constraint;
The dividing unit is further configured to continue dividing another new binary decision graph until the binary decision graphs obtained by dividing can generate a new lookup table when the update margin does not meet the margin constraint;
the dividing unit is further configured to re-divide the degradation binary decision graph when the update margin meets the margin constraint;
The margin constraint is that the update margin is less than a minimum margin of input pins of the seed node in the expanded set;
The update margin is the difference between the minimum margin of the input pins of the newly generated node and the expected delay caused by introducing a new node; the calculation mode of the expected delay is to add the delay of all nodes except the root node and the edge in the extension set and then divide the delay by the number of nodes except the root node;
The dividing unit includes:
a variable ordering subunit, configured to reorder all variables in the degraded binary decision graph;
And the dividing subunit is used for dividing the degradation binary decision diagram after the variable reordering.
10. A computer device, comprising:
A memory and a processor, the memory and the processor being communicatively connected to each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the chip delay optimization method of any one of claims 1 to 8.
11. A computer-readable storage medium having stored thereon computer instructions for causing a computer to perform the chip delay optimization method of any one of claims 1 to 8.
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