CN117350204B

CN117350204B - Target netlist generation method and device, computer equipment and readable storage medium

Info

Publication number: CN117350204B
Application number: CN202311188213.7A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Suzhou Yige Technology Co ltd
Current assignee: Suzhou Yige Technology Co ltd
Priority date: 2023-09-14
Filing date: 2023-09-14
Publication date: 2024-05-28
Anticipated expiration: 2043-09-14
Also published as: CN117350204A

Abstract

The invention relates to the technical field of integrated circuit design, and discloses a method and a device for generating a target netlist, computer equipment and a computer readable storage medium, wherein the method comprises the following steps: obtaining a gate-level netlist; wherein the gate-level netlist comprises a plurality of directed acyclic graphs, each directed acyclic graph comprising a plurality of nodes; dividing the plurality of nodes to generate a first dividing result corresponding to the nodes and a first basic attribute parameter corresponding to the first dividing result; processing the first basic attribute parameters to generate first evaluation attribute information corresponding to a first division result; processing the gate-level netlist according to the first evaluation attribute information, and determining a first target node for mapping and a second division result corresponding to the first target node; and generating a target netlist based on the first target node and the second partitioning result. The method solves the technical problem that in the prior art, a better logic mapping result cannot be ensured only by marking the nodes to select the mapping nodes.

Description

Target netlist generation method and device, computer equipment and readable storage medium

Technical Field

The present invention relates to the field of integrated circuit design technology, and in particular, to a method and apparatus for generating a target netlist, a computer device, and a computer readable storage medium.

Background

The use of field programmable gate array FPGAs requires the support of a self-contained electronic design automation tool (e.g., electronic design automation, EDA). The logic mapping is an indispensable link in the EDA tool, and the function of logic mapping implementation is often to map a gate-level netlist generated after logic synthesis into a series of basic data types (such as LUT, DFF) based on hardware abstraction as an original netlist.

In the prior art, node marking and LUT (Look-Up-Table) coverage are often adopted to realize logic mapping; in the marking stage, marking nodes one by one according to the topological sequence of PI-PO, and selecting the nodes to be mapped; in the LUT coverage stage, according to the result of the marking stage, a high degree of division is selected for the nodes to carry out LUT coverage, thereby realizing logic mapping.

However, in the prior art, a better logic mapping result cannot be ensured only by marking the nodes to select the mapping nodes.

Disclosure of Invention

In view of this, the present invention provides a method, apparatus, computer device and readable storage medium for generating a target netlist, so as to solve the technical problem that in the prior art, a better logic mapping result cannot be ensured only by marking nodes and selecting mapping nodes.

In a first aspect, the present invention provides a method for generating a target netlist, the method comprising: obtaining a gate-level netlist; wherein the gate-level netlist comprises a plurality of directed acyclic graphs, each directed acyclic graph comprising a plurality of nodes; dividing the plurality of nodes to generate a first dividing result corresponding to the nodes and a first basic attribute parameter corresponding to the first dividing result; processing the first basic attribute parameters to generate first evaluation attribute information corresponding to a first division result; processing the gate-level netlist according to the first evaluation attribute information, and determining a first target node for mapping and a second division result corresponding to the first target node; and generating a target netlist based on the first target node and the second partitioning result.

According to the method for generating the target netlist, after each node is divided, a plurality of first division results and first basic attribute parameters of the first division results are generated, then the first basic attribute parameters are processed to obtain first evaluation attribute information, the first evaluation attribute information can be used for screening the plurality of first division results, so that an optimal second division result is ensured to be obtained, and finally the second division results and the corresponding first target nodes are mapped, so that a better target netlist can be obtained.

In an alternative embodiment, after processing the gate level netlist according to the first evaluation attribute information, determining a first target node for mapping and a second partitioning result corresponding to the first target node, the method further comprises: performing iterative processing on the second division result and the first target node to generate a third division result and second basic attribute information corresponding to the third division result; processing the second basic attribute information based on the first evaluation attribute information to generate second evaluation attribute information; and processing the gate-level netlist according to the second evaluation attribute information, and determining a second target node and a fourth division result for mapping until the number of iterative execution times meets the preset number of times.

According to the generating method of the target netlist, after the second division result is determined, the second division result determined last time is utilized to conduct re-division, then a third division result is generated, the third division result is processed through second evaluation attribute information, and a fourth division result is generated; by means of continuous iterative updating, a better target netlist can be obtained more accurately.

In an alternative embodiment, the first basic attribute parameter includes a delay attribute parameter, an input node number attribute parameter, an area attribute parameter, an iteration attribute parameter, a variable attribute parameter, and a partition attribute parameter, and the first partition includes a plurality of input nodes and a root node; wherein processing the first basic attribute parameter to generate first evaluation attribute information corresponding to the first division result includes: acquiring delay attribute parameters of a plurality of input nodes; determining the minimum target delay attribute parameter in the delay attribute parameters according to the comparison result of the delay attribute parameters; determining target quantity attribute parameters of input nodes corresponding to the root nodes; determining a target area attribute parameter based on the last area attribute parameter and the output number of the root nodes corresponding to the first division result; determining a target iteration attribute parameter based on the last iteration attribute parameter and the output number; determining a first target variable attribute parameter based on the target area attribute parameter, the target iteration attribute parameter and the output number; traversing the input nodes of the root node, and determining the number of the input nodes with the output number meeting the preset output number based on the output number of the input nodes; determining a partition attribute parameter based on the number of input nodes; first evaluation attribute information is generated based on the first target variable attribute parameter, the target iteration attribute parameter, the target area attribute parameter, the target delay attribute parameter, the target number attribute parameter, and the partition attribute parameter.

According to the method for generating the target netlist, the optimal target area attribute parameters can be obtained through the obtained optimal target delay attribute parameters and the output quantity of the root nodes, so that the area optimization space of the first evaluation attribute information is improved; the optimization effect of the first evaluation attribute information on the netlist can be improved by continuously updating the target iteration attribute parameter and the first target variable attribute parameter according to the iteration times.

In an alternative embodiment, processing the first basic attribute parameter to generate first evaluation attribute information corresponding to the first division result includes: judging whether the first basic attribute parameter meets a preset condition or not; when the first basic attribute parameters meet preset conditions, the first basic attribute parameters are processed to generate first evaluation attribute information; and when the first basic attribute parameter does not meet the preset condition, discarding the first division result which does not meet the preset condition.

According to the method for generating the target netlist, after a plurality of first division results are obtained, whether the first division results meet the preset conditions or not is judged, and the first division results which do not meet the preset conditions are discarded, so that the node processing efficiency can be effectively reduced, and the generating efficiency of the target netlist is improved.

In an alternative embodiment, processing the gate level netlist according to the first evaluation attribute information, determining a first target node for mapping and a second partitioning result corresponding to the first target node, includes: acquiring the priority of the first evaluation attribute information; traversing the gate-level netlist according to the reverse topological order, sequentially comparing the first evaluation attribute information according to the order of the priorities from low to high, and determining a first division result with the highest priority; the first division result is characterized as a second division result; a plurality of first target nodes is determined based on the second partitioning result.

According to the method for generating the target netlist, the priorities of the first evaluation attribute information are compared, then the gate netlist is traversed according to the mode that the priorities are combined with the reverse topological order, so that an optimal second partitioning result can be obtained, a corresponding first target node is determined according to the second partitioning result, and finally the second partitioning result and the corresponding first target node are mapped, so that a better target netlist can be obtained.

In an optional embodiment, before performing the partitioning processing on the plurality of nodes to generate the first partitioning result corresponding to the nodes and the first basic attribute parameter corresponding to the first partitioning result, the method further includes: acquiring identification values corresponding to a plurality of input nodes in a first division result; determining a characteristic value corresponding to the identification value; judging whether the characteristic values meet preset requirements or not; and if the characteristic values meet the preset requirements, processing the first basic attribute to generate a first evaluation attribute.

According to the target netlist generation method provided by the embodiment, the rationality of some first division results can be directly judged by comparing the feature values, and if the first division results are reasonable, the first basic attributes are directly processed to generate the first evaluation attributes. Therefore, the first division result meeting the preset requirement can be preferentially screened out, so that the comparison time can be saved to a great extent.

In an optional embodiment, the partitioning processing is performed on a plurality of nodes, to generate a first partitioning result corresponding to the nodes and a first basic attribute parameter corresponding to the first partitioning result, including: performing topology sequence processing on the plurality of nodes to generate a plurality of fifth division results of the corresponding nodes; enumerating a plurality of fifth division results to generate a first division result and a first basic attribute.

According to the method for generating the target netlist, on one hand, the first division results which do not meet the preset conditions can be removed in an enumeration mode, and on the other hand, the combination of a plurality of fifth division results can be achieved in an enumeration mode, so that the accuracy of the first division results is guaranteed.

In a second aspect, the present invention provides a generating apparatus for a target netlist, where the apparatus includes a first obtaining module configured to obtain a gate level netlist; wherein the gate-level netlist comprises a plurality of directed acyclic graphs, each directed acyclic graph comprising a plurality of nodes; the first processing module is used for carrying out division processing on the plurality of nodes and generating a first division result corresponding to the nodes and a first basic attribute parameter corresponding to the first division result; the second processing module is used for processing the first basic attribute parameters and generating first evaluation attribute information corresponding to the first division result; the third processing module is used for processing the gate-level netlist according to the first evaluation attribute information and determining a first target node for mapping and a second division result corresponding to the first target node; and the generating module is used for generating a target netlist based on the first target node and the second division result.

In a third aspect, the present invention provides a computer device comprising: the memory and the processor are in communication connection, computer instructions are stored in the memory, and the processor executes the computer instructions, so that the method for generating the target netlist according to the first aspect or any implementation mode corresponding to the first aspect is executed.

In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon computer instructions for causing a computer to execute the method for generating a target netlist according to the first aspect or any of its corresponding embodiments.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow diagram of a method of generating a target netlist according to an embodiment of the invention;

FIG. 2 is a schematic diagram of the structure of a directed acyclic graph according to an embodiment of the invention;

FIG. 3 is a flow diagram of another method of generating a target netlist according to an embodiment of the invention;

FIG. 4 is a schematic diagram of another directed acyclic graph according to an embodiment of the invention;

FIG. 5 is a schematic diagram of the structure of one of the directed acyclic graphs according to an embodiment of the invention;

FIG. 6 is a flow diagram of a method of generating a further target netlist according to an embodiment of the invention;

FIG. 7 is a schematic diagram of an evaluation system according to an embodiment of the invention;

FIG. 8 is a flow chart of a method of generating yet another target netlist according to an embodiment of the invention;

FIG. 9 is an enumerated schematic diagram of a directed acyclic graph according to an embodiment of the invention;

FIG. 10 is an enumerated schematic diagram of yet another directed acyclic graph according to an embodiment of the invention;

FIG. 11 is a block diagram of a target netlist generation device according to an embodiment of the invention;

fig. 12 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The method for generating the target netlist is implemented in an FPGA (a chip with a changeable internal structure by programming); the FPGA needs to be supported by a matched EDA tool (a design mode of completing the processes such as functional design, synthesis, verification, physical design (including layout, wiring, layout, design rule checking, etc.) of a very large scale integrated circuit (VLSI) chip by using Computer Aided Design (CAD) software), and logic mapping is an essential link in the EDA tool. The function implemented in this step is often to map the gate-level netlist generated after logic synthesis into a series of netlists (i.e., target netlists) based on basic data types such as LUTs (partitions) abstracted by hardware as primary.

Based on the related technology, the logic mapping is realized by adopting node marks and LUT (Look-Up-Table) coverage; in the marking stage, marking nodes one by one according to the topological sequence of PI-PO, and selecting the nodes to be mapped; in the LUT coverage stage, according to the result of the marking stage, a high degree of division is selected for the nodes to carry out LUT coverage, thereby realizing logic mapping. But by only marking the nodes to select the mapping nodes, a better logical mapping result cannot be ensured.

In accordance with an embodiment of the present invention, there is provided a method embodiment for generating a target netlist, it being noted that the steps shown in the flowcharts of the figures may be performed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different than what is shown herein.

In this embodiment, a method for generating a target netlist is provided, which may be used in the above-mentioned central processing unit (Central Processing Unit, CPU), and fig. 1 is a flowchart of a method for generating a target netlist according to an embodiment of the present invention, as shown in fig. 1, where the flowchart includes the following steps:

Step S101, obtaining a gate-level netlist; wherein the gate-level netlist includes a plurality of directed acyclic graphs, each directed acyclic graph including a plurality of nodes.

In this embodiment, fig. 2 is a schematic structural diagram of a directed acyclic graph. Wherein, as shown in connection with FIG. 2, the gate-level netlist can include a plurality of directed acyclic graphs; in a gate-level netlist only containing basic combinational logic, all input nodes are iterated by taking any node as a root node until the input node at the top level is traversed (the node has no input node), and a sub-graph (namely a directed acyclic graph) taking one node as the root node can be obtained. Wherein node 1, node 2, node 3, node 4 and node 5 are a plurality of nodes in the directed acyclic graph.

It should be noted that the number of nodes in fig. 2 is only referred to herein, and the specific number and connection manner are not specifically limited herein, and may be implemented by those skilled in the art.

Step S102, dividing the plurality of nodes to generate a first dividing result corresponding to the nodes and a first basic attribute parameter corresponding to the first dividing result.

Referring to fig. 2, each node in fig. 2 is divided, taking node 1 as an example, CUT1 and CUT2 are both a division result (i.e., a first division result) of the subgraph shown in fig. two, and each CUT includes a corresponding first basic attribute parameter. The nodes corresponding to the CUT1 may be a node 1, a node 2, and a node 3; the nodes corresponding to CUT2 may be node 1, node 3, node 4, and node 5.

Step S103, processing the first basic attribute parameter to generate first evaluation attribute information corresponding to the first division result.

After obtaining the first basic attribute parameters corresponding to the first division result, determining first evaluation attribute information according to a plurality of target parameters in the first basic attribute parameters. Wherein the first evaluation attribute information is used to determine a second division result for mapping.

Step S104, the gate level netlist is processed according to the first evaluation attribute information, and a first target node for mapping and a second division result corresponding to the first target node are determined.

And dividing the gate-level netlist again according to the first evaluation attribute information, evaluating the gate-level netlist to determine the priority of the CUT compared with other CUTs, so as to determine an optimal second division result, and further determine a first target node corresponding to the second division result.

Step S105, generating a target netlist based on the first target node and the second partitioning result.

That is, when mapping the second division result to the prior-level netlist (i.e., the target netlist), a second division result needs to be mapped to a LUT (Look-Up Table) to complete the mapping of the target netlist.

In an optional embodiment, after step S104, the method for generating a target netlist further includes:

and carrying out iterative processing on the second division result and the first target node to generate a third division result and second basic attribute information corresponding to the third division result.

And processing the second basic attribute information based on the first evaluation attribute information to generate second evaluation attribute information.

And processing the gate-level netlist according to the second evaluation attribute information, and determining a second target node and a fourth division result for mapping until the number of iterative execution times meets the preset number of times.

According to the method for generating the target netlist, after the second division result is determined, the second division result determined last time is used for carrying out re-division, then a third division result is generated, the third division result is processed through the second evaluation attribute information, a fourth division result is generated, and then the steps from the step S101 to the step S104 are repeatedly executed.

Such as: taking nodes 0-9 in fig. 9 as an example, where there are four kinds of division results of CUT1-CUT4, the division result satisfying the first evaluation attribute may be determined from the four kinds of division results of CUT1-CUT4 through the above-described step S101-step S104, such as: CUT1 and CUT2. Then CUT1 and CUT2 are divided again to obtain a new division result until the preset times of iteration are met.

Alternatively, the preset number of times may be 5 times, 10 times, 13 times, etc., and the specific number of iterations is not specifically limited herein, and may be implemented by those skilled in the art.

According to the embodiment, the optimal dividing result can be obtained more accurately by continuously and iteratively updating the dividing result, so that the optimal target netlist can be determined more accurately. In this embodiment, a method for generating a target netlist is provided, which may be used in the above-mentioned central processing unit, and fig. 3 is a flowchart of a method for generating a target netlist according to an embodiment of the present invention, as shown in fig. 3, where the flowchart includes the following steps:

step S201, obtaining a gate-level netlist; wherein the gate-level netlist includes a plurality of directed acyclic graphs, each directed acyclic graph including a plurality of nodes. Please refer to step S101 in the embodiment shown in fig. 1 in detail, which is not described herein.

Step S202, a plurality of nodes are divided, and a first division result corresponding to the nodes and a first basic attribute parameter corresponding to the first division result are generated. Please refer to step S102 in the embodiment shown in fig. 1 in detail, which is not described herein.

Step S203, the first basic attribute parameter is processed to generate first evaluation attribute information corresponding to the first division result.

Specifically, the first basic attribute parameters comprise delay attribute parameters, input node quantity attribute parameters, area attribute parameters, iteration attribute parameters, variable attribute parameters and partition attribute parameters, and the first partition result comprises a plurality of input nodes and root nodes; wherein, the step S203 includes:

s2031, delay attribute parameters of a plurality of input nodes are acquired.

S2032, determining the minimum target delay attribute parameter in the delay attribute parameters according to the comparison result of the delay attribute parameters.

Each input node has delay attribute parameters such as: 1.2, comparing the delay parameters of the input nodes in each first division result to obtain a target delay attribute parameter with the minimum delay parameter, and then determining the first division result with the minimum target delay attribute parameter. If a CUT with the smallest delay attribute parameter is selected for each node, the smallest target delay attribute parameter that the entire netlist can achieve based on the CUT's constraints is finally obtained in one traversal.

Fig. 4 shows a schematic structural diagram of a directed acyclic graph. In connection with the determination method of the target delay attribute parameter shown in fig. 4, in order to set the delay attribute parameters of all the top-level nodes (without input nodes) to 0 first, then the delay of the child node of each node is the delay+1 of the maximum input node, and similarly, the maximum delay can be obtained after the topology sequence traverses all the nodes. It is taken as the initial value of the time constraint required time. The required time of each node is set as an initial value, and then the required time of each node is the minimum required time-1 of all the sub-nodes. Such as: if no node is input into the node 2, the delay attribute parameter of the node is set to be 0, if one input node is provided with the node 3, the delay attribute parameter of the node is set to be 1, and the node 5 corresponds to two input nodes of the node 2 and the node 3, wherein the node 3 is the maximum input node, and the delay attribute parameter of the node 5 is the delay attribute parameter of the node 3 plus 1.

S2033, determining target number attribute parameters of the input nodes corresponding to the root node.

Each root node corresponds to a plurality of input nodes, and thus, a target number attribute parameter of the input node corresponding to the root node can be determined.

S2034, determining a target area attribute parameter based on the last area attribute parameter and the output number of the root node corresponding to the first division result.

In an alternative embodiment, the determining the target area attribute parameter based on the last area attribute parameter and the output number of the root node corresponding to the first division result may be as follows:

Where i represents the input node number of the CUT, from 0 to k, the CUT has k+1 input nodes, fanout is the output number of the root node corresponding to the first division result). Observation can find that area is a target area attribute parameter, and area [ i ] is a last area attribute parameter.

S2035, determining a target iteration attribute parameter based on the last iteration attribute parameter and the output number.

In an alternative embodiment, the determination of the target iteration attribute parameter based on the last iteration attribute parameter and the output number may be as follows:

Wherein iter represents the iteration round number, estFanout [ iter ] is a target iteration attribute parameter, and alpha is a constant value.

S2036, determining a first target variable attribute parameter based on the target area attribute parameter, the target iteration attribute parameter, and the output number.

In an alternative embodiment, the determining the first target variable attribute parameter based on the target area attribute parameter, the target iteration attribute parameter, and the output number may be as follows:

Wherein A is the area, and cost is the attribute parameter of the first target variable.

S2037, traversing the input nodes of the root node, and determining the number of the input nodes with the output number meeting the preset output number based on the output number of the input nodes.

S2038, determining the partition attribute parameter based on the number of input nodes.

The partitioning attribute parameter is used to characterize the number of partitions contained in a maximum fanout cone (Maximum Fanout Free Cone, MFFC) of a CUT. Wherein the partitioning attribute parameter localArea is the number of input nodes in each maximum fanout-free cone.

Fig. 5 is a schematic diagram of a directed acyclic graph, and in conjunction with fig. 5, each CUT is ultimately mapped to a LUT node, which can be considered as a LUT node for each node in fig. 5. localArea in FIG. 5 is node 1, i.e., 9, and the entire graph is fanout-free except for node 1 (i.e., node 0, node 2-node 9). localArea for node 3 is 3 because the subgraph with node 3 as the root node is traversed upward from node 3, including node 5, node 6, node 8, node 9, node 0. Where node 5 has one fan out as node 2, fig. 5 can be seen as pointing from top to bottom to the input node to the child node, so there is no feasible path between node 2 and node 3. Similarly, node 8 has a fan-out of node 4, and there is no viable path between it and node 3. Therefore, node 3 contains only node 6, node 9, and node 0 in MFFC.

In an alternative embodiment, the step S2038 may include the following steps:

step a1, constructing a queue.

Step a2, adding a CUT to the queue.

Step a3, pop one CUT in the queue.

Step a4, traversing the input nodes corresponding to the CUT in step a 2.

Step a5, subtracting a preset value from the input node.

Step a6, judging whether the preset value is zero.

And a7, if the input node is zero, adding the input node into a queue, namely adding 1 to the number of the input nodes.

Step a8, repeatedly executing all input nodes corresponding to the CUT until the queue is empty.

In this embodiment, as shown in fig. 5, taking as an example that node 3 (each CUT is a selected partition of the netlist and then mapped into an LUT, and thus can be regarded as a node) is calculated localArea (initial value is 0), a queue is first created to push node 3 in, and then input nodes of node 3 are traversed. First, fanout of the node 5 is decremented by 1, fanout of the node 5 is changed from 2 to 1 to 0, and no operation is performed. Then fanout of node 6 is decremented by 1 and fanout of node 6 is changed from 1 to 0, thus adding node 6 to the queue, localArea +1. And finishing the input node traversal of the node 3, wherein the queue is not empty, popping the node 6 and continuing to repeat the operation, so that localArea of the node 3 is obtained.

Alternatively, the preset value may be 1.

The present embodiment can calculate the number localArea more simply.

S2039, generating first evaluation attribute information based on the first target variable attribute parameter, the target iteration attribute parameter, the target area attribute parameter, the target delay attribute parameter, the target number attribute parameter, and the division attribute parameter.

The first evaluation attribute information may be generated according to at least three of a first target variable attribute parameter, a target iteration attribute parameter, a target area attribute parameter, a target delay attribute parameter, a target number attribute parameter, and a partition attribute parameter. Such as: the first target variable attribute parameter, the target iteration attribute parameter and the target area attribute parameter can be used as a first evaluation attribute parameter; for another example: the target delay attribute parameter, the target number attribute parameter, and the division attribute parameter may be regarded as one piece of first evaluation attribute information.

In the method for generating the target netlist provided by the embodiment, from the perspective of an evaluation system, the scheme uses 4 kinds of first evaluation attribute information, namely [ delay, CUT input, area ], [ delay, area, CUT input ], cost, estFanout, delay ] and [ localArea, estFanout, delay ]; wherein the optimal delay is confirmed and the area is optimized (resource usage is reduced) by the previous two rounds of iteration, and then the area is further optimized by the evaluation attribute aiming at the area design.

In addition, by limiting the CUT set size of each node, only N nodes with optimal evaluation attributes in each node are included in the set for processing of subsequent nodes, and when the netlist division is confirmed by the reverse topological order, the CUT with optimal evaluation attributes of the node is selected if the node is traversed. Under the condition that the evaluation system is reasonable in design, the method can ensure good mapping results at the same time under the condition that the running time is shortened to a great extent.

Step S204, the gate level netlist is processed according to the first evaluation attribute information, and a first target node for mapping and a second division result corresponding to the first target node are determined. Please refer to step S104 in the embodiment shown in fig. 1 in detail, which is not described herein.

Step S205, a target netlist is generated based on the first target node and the second partitioning result. Please refer to step S105 in the embodiment shown in fig. 1 in detail, which is not described herein.

In an alternative embodiment, the step S203 may further include the following steps:

step b1, judging whether the first basic attribute parameter meets a preset condition;

step b2, when the first basic attribute parameters meet preset conditions, processing the first basic attribute parameters to generate first evaluation attribute information;

and b3, when the first basic attribute parameter does not meet the preset condition, discarding the first division result which does not meet the preset condition.

After determining the first division result, it needs to be determined whether the first basic attribute parameter corresponding to the first division result meets a preset condition, and it needs to be described that the constraint of delay and demand time may be determined, for example: if delay is greater than the required time, the first division result which does not meet the preset condition needs to be discarded, so that the processing efficiency of the nodes can be effectively reduced, and the generating efficiency of the target netlist is improved.

According to the method for generating the target netlist, after the plurality of first division results are obtained, whether the first division results meet the preset conditions or not is judged, and the first division results which do not meet the preset conditions are discarded, so that the node processing efficiency can be effectively reduced, and the generating efficiency of the target netlist is improved.

In this embodiment, a method for generating a target netlist is provided, which may be used in the above-mentioned central processing unit, and fig. 6 is a flowchart of a method for generating a target netlist according to an embodiment of the present invention, as shown in fig. 6, where the flowchart includes the following steps:

Step S301, obtaining a gate-level netlist; wherein the gate-level netlist includes a plurality of directed acyclic graphs, each directed acyclic graph including a plurality of nodes. Please refer to step S101 in the embodiment shown in fig. 1 in detail, which is not described herein.

Step S302, performing a partitioning process on the plurality of nodes, and generating a first partitioning result corresponding to the node and a first basic attribute parameter corresponding to the first partitioning result. Please refer to step S102 in the embodiment shown in fig. 1 in detail, which is not described herein.

Step S303, processing the first basic attribute parameter, and generating first evaluation attribute information corresponding to the first division result. Please refer to step S103 in the embodiment shown in fig. 1 in detail, which is not described herein.

Step S304, the gate level netlist is processed according to the first evaluation attribute information, and a first target node for mapping and a second division result corresponding to the first target node are determined.

Specifically, the step S304 may include the following steps:

in step S3041, the priority of the first evaluation attribute information is acquired.

Step S3042, traversing the gate-level netlist according to the reverse topological order, sequentially comparing the first evaluation attribute information according to the order from low priority to high priority, and determining a first division result with the highest priority; wherein the first division result is characterized as a second division result.

Step S3043, determining a plurality of first target nodes based on the second division result.

Fig. 7 shows a schematic diagram of an evaluation system. Referring to fig. 7, the evaluation system of fig. 7 is used to obtain first evaluation attribute information of a CUT. First, a series of first basic attributes are obtained in the process of generating the CUT, and may be further divided into global attributes (e.g., area attribute parameters), local attributes (e.g., the number of input nodes corresponding to the root node), and iterative attributes (e.g., iteration attribute parameters). The first evaluation attribute information may be represented by a vector, where the first level of evaluation in fig. 7 represents that the first evaluation attribute information is a one-dimensional vector, and the multiple levels of evaluation represent that the first evaluation attribute information is a multidimensional vector, and the dimensions of the vector and the meaning represented by each dimension (composition and comparison mode, such as greater or lesser preference) and the priority need to be determined by combining the considered first basic attribute parameter and the designed evaluation function (i.e. the mode of determining the first basic attribute parameter) in each iteration process. Such as: in one iteration, where it is desired to take delay as the highest priority, area as the next priority, fanout as the third priority, then for each CUT we will get a vector of [ delay, area, fanout ] as the evaluation attribute, if there is one CUT0 (its evaluation attribute [ delay0, area0, fanout0 ]) better than another CUT1 (its evaluation attribute [ delay0, area0, fanout0 ]), then delay0< delay1, or delay 0= delay1, area0< area1, or delay 0= = delay1, area 0= = area1, fanout0> fanout1.

Step S305, a target netlist is generated based on the first target node and the second partitioning result. Please refer to step S105 in the embodiment shown in fig. 1 in detail, which is not described herein.

In this embodiment, a method for generating a target netlist is provided, which may be used in the above-mentioned central processing unit, and fig. 8 is a flowchart of a method for generating a target netlist according to an embodiment of the present invention, as shown in fig. 8, where the flowchart includes the following steps:

Step S401, obtaining a gate-level netlist; wherein the gate-level netlist includes a plurality of directed acyclic graphs, each directed acyclic graph including a plurality of nodes. Please refer to step S101 in the embodiment shown in fig. 1 in detail, which is not described herein.

Step S402, dividing the plurality of nodes to generate a first dividing result corresponding to the nodes and a first basic attribute parameter corresponding to the first dividing result.

Specifically, the step S402 may include the following steps:

in step S4021, topology sequence processing is performed on the plurality of nodes, so as to generate a plurality of fifth division results of the corresponding nodes.

In step S4022, enumeration is performed on the plurality of fifth division results, and a first division result and a first basic attribute parameter are generated.

Fig. 9 and 10 show an enumeration schematic of a directed acyclic graph, please refer to fig. 9 and 10, in which a series of CUT can be enumerated for each node, the enumeration manner is to perform a combination enumeration on the CUT of its parent node, and a specific flow of the enumeration schematic may be described with reference to fig. four. When the CUT of node 1 in fig. 9 is generated, it may be obtained by performing a combinatorial enumeration through the CUT of its input node. The input nodes of node 1 are node 2 and node 3, where node 2 has two CUT (not just two of which are considered for convenience of illustration only) CUT1 and CUT2, respectively, and node 3 also has two CUT3 and CUT4, respectively. Combining the CUT of two nodes can result in [ CUT1, CUT3], [ CUT2, CUT4], [ CUT1, CUT4], [ CUT2, CUT3]. As shown in connection with fig. 10, the root nodes of all combined CUT are node 1. The combination of CUT1 and CUT3 will become CUT5, with its input nodes node 7, node 8, node 9, node 0. The combination of CUT2 and CUT4 will become CUT8, with its input nodes node 4, node 5, node 6. The combination of CUT1 and CUT4 will become CUT6, with its input nodes being node 7, node 8, node 9, node 6. The combination of CUT2 and CUT3 will become CUT7, with its input nodes node 4, node 8, node 9, node 0.

Step S403, processing the first basic attribute parameter, and generating first evaluation attribute information corresponding to the first division result. Please refer to step S103 in the embodiment shown in fig. 1 in detail, which is not described herein.

Step S404, the gate level netlist is processed according to the first evaluation attribute information, and a first target node for mapping and a second division result corresponding to the first target node are determined. Please refer to step S104 in the embodiment shown in fig. 1 in detail, which is not described herein.

Step S405, a target netlist is generated based on the first target node and the second partitioning result. Please refer to step S105 in the embodiment shown in fig. 1 in detail, which is not described herein.

In an alternative embodiment, prior to step S102, the method further comprises:

Step c1, obtaining identification values corresponding to a plurality of input nodes in the first division result.

Step c2, determining a characteristic value corresponding to the identification value.

And c3, judging whether the characteristic values meet the preset requirement.

And c4, if the plurality of characteristic values meet the preset requirements, processing the first basic attribute to generate a first evaluation attribute.

In this embodiment, the generation of the set of CUT for each node is done by enumerating the set of CUT merges for its input nodes. A CUT to incorporate a CUT set first needs to be judged as rational before being evaluated by its first evaluation attribute information. The judgment of rationality mainly comprises three points: 1. whether a CUT exists in the CUT set; 2. whether one CUT is contained by another CUT in the set or contains another CUT in the set; 3. whether the total number of inputs of a CUT satisfies less than K (K is a set value). Wherein, a CUT exists in the CUT set, namely, the CUT is the CUT, and the input node and the output node of the CUT are identical to those of the CUT existing in the set. One CUT is encompassed by another CUT in the set, i.e., the input nodes of the CUTs in the set are completely encompassed by the input nodes of the one CUT. Taking node 1 in FIG. 5 as an example, described above, generating a set of CUTs for node 1 requires combining CUTs for node 2 and node 3 by enumerating the CUTs. Node 2 has a CUT with its input nodes node 7, node 8, node 9. Node 3 has a CUT whose input node is node 5, node 6. The input nodes of the newly generated CUT called CUT1 are nodes 5, 6, 7, 8, 9. Node 3 has another CUT input node as nodes 8, 9, 6. The combination with the CUT of node 2 described above results in a new CUT called CUT2, whose input nodes are nodes 7, 8, 9, 6. From the figure, it can be seen that the partition coverage generated by CUT2 can completely contain the coverage generated by CUT1 (coverage nodes of CUT2 are nodes 1,2,3,4, 5, coverage nodes of CUT1 are nodes 1,2,3, 4). In this case we consider that the priority of CUT2 must be better than the priority of CUT 1. Whether the total number of inputs of one CUT is smaller than K or not is that the number of input nodes is smaller than K or not. However, if no prescreening is performed, each CUT needs to make a single determination of the three conditions, i.e., each input node needs to be compared one by one. Thereby consuming K2 units of time.

The present embodiment provides for the ability to directly determine the rationality of some CUT's, thereby eliminating the need for subsequent conditional determinations to compare with the input node one by one. First, in the gate level netlist, each node attaches an ID value (i.e., the identification value described above) to it, and assigns a value starting from 0. A sign (eigenvalue) of the CUT is then calculated from the ID of its input node. The calculation method is as follows:

Wherein M is a value designed based on the number of computer operation bits, sign is a characteristic value, the characteristic value can be represented by binary system, and n is an input node of the CUT. Taking CUT8 in fig. 10 as an example, input nodes of the CUT8 are node 4, node 5 and node 6, and id values are set to 4,5 and 6, respectively. Then sign of CUT8 is ((M-6) 0) 111000, M bits total. Current computers tend to be 64 bits, so M can be set to 64.

The introduction of sign allows us to get the following judgement: 1. if the sign of CUT1 and CUT2 are not the same then the two CUTs must not be the same. (that is, only if sign is the same, it is necessary to compare the two CUTs one by one, that is, whether the input nodes of CUT1 and CUT2 are identical. 2. If the sign of CUT1 is not included in CUT2 then CUT1 must not be included in CUT2 (i.e., only if the sign of CUT1 is included in the sign of CUT2 (each bit of CUT1 being 1 is also 1 in CUT2, such as 0010 is included in 0011), then it is necessary to compare nodes one by one to determine if CUT1 includes CUT 2). 3. If the sum of 1 in the sign of CUT1 and CUT2 is less than K, then the number of input nodes of the CUT generated by the merging of CUT1 and CUT2 must be less than K. Through the three screening conditions, some CUTs meeting the conditions can be screened in one calculation period, so that the comparison time can be saved to a great extent.

In an alternative embodiment, the present application provides a method for fast acquisition of LUT truth tables.

When mapping the first division result (CUT) to the prior level netlist, it is mainly necessary to map a CUT to a LUT (Look-Up Table), for which specific values of the LUT truth Table need to be known. Taking the AND logic of two inputs as an example, the inputs are a and b, the truth table is 1000, and the truth table is from right to left (the first bit of [ a and b ] from right to left is [0,0], the second bit is [0,1], the third bit is [1,0], and the fourth bit is [1,1 ]). Then a traversal simulation of all input possibilities for both inputs is required when this truth table is obtained. The number of times that two inputs need to be traversed is 4 (22), and similarly, the LUT typically has a maximum input of 6, and for each LUT6, it is necessary to simulate 64 (26) times to arrive at its truth table. In order to solve the situation, the scheme provides a method, and a truth table of one LUT can be obtained through one simulation.

Because the LUT has a limited number of inputs (typically 6 at maximum), the input condition of each node can be obtained easily through enumeration. Taking a two-input LUT as an example, inputs are a and b, the simulation needs to be traversed, namely [0,0], [0,1], [1,0], [1,1], and the input of a is 1100, and the input of b is 1010. We can directly assign a to 1100 and b to 1010 followed by bit-wise simulation to obtain a truth table. Taking a two-input AND gate as an example, 1100 and 1010 are bitwise AND operations to obtain 1000, which is the truth table of the two-input AND gate. Similarly, the initial values of the three inputs are: 11110000, 11001100, 10101010 the rest of the LUT can be analogized. And storing all input initial values in advance, finding out corresponding initial values through the input quantity of the LUT to simulate when the LUT is used, and obtaining a truth table of the LUT through one-time simulation, so that the truth table of the LUT can be obtained quickly.

Compared with a general logic mapping method, the method can ensure the optimal delay, and simultaneously realize less area occupation in a shorter running time.

In addition, the optimal delay is obtained through iterative preprocessing, and meanwhile, the number of input nodes of the CUT is controlled in a smaller range through the CUT input attribute, so that the space for optimizing the subsequent area is improved.

In addition, the CUT set size of each node is limited, only N nodes with optimal evaluation attributes in each node are included in the set for enumeration of subsequent nodes, and when the netlist division is confirmed by the reverse topological order, the CUT with optimal evaluation attributes of the node is selected if the node is traversed. Under the condition that the evaluation system is reasonable in design, the method can ensure good mapping results at the same time under the condition that the running time is shortened to a great extent.

The present embodiment also provides a device for generating a target netlist, which is used in the following, for implementing the foregoing embodiments and preferred embodiments, and is not described in detail. The term "module" may be a combination of software and/or hardware that implements the intended function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

The present embodiment provides a generating apparatus of a target netlist, as shown in fig. 11, including:

A first obtaining module 1101, configured to obtain a gate level netlist; wherein the gate-level netlist comprises a plurality of directed acyclic graphs, each directed acyclic graph comprising a plurality of nodes;

the first processing module 1102 is configured to perform a partitioning process on a plurality of nodes, and generate a first partitioning result corresponding to the nodes and a first basic attribute parameter corresponding to the first partitioning result;

A second processing module 1103, configured to process the first basic attribute parameter, and generate first evaluation attribute information corresponding to the first division result;

a third processing module 1104, configured to process the gate-level netlist according to the first evaluation attribute information, and determine a first target node for mapping and a second division result corresponding to the first target node;

a generating module 1105, configured to generate a target netlist based on the first target node and the second partitioning result.

In some optional embodiments, the apparatus further includes an iteration module configured to iteratively perform processing on the second division result and the first target node to generate a third division result and second base attribute information corresponding to the third division result: the fourth processing module is used for processing the second basic attribute information based on the first evaluation attribute information to generate second evaluation attribute information; and a fifth processing module, configured to process the gate-level netlist according to the second evaluation attribute information, and determine a second target node for mapping and a fourth division result until the number of iterative execution times satisfies a preset number of times.

In an alternative embodiment, the first basic attribute parameter includes a delay attribute parameter, an input node number attribute parameter, an area attribute parameter, an iteration attribute parameter, a variable attribute parameter, and a partition attribute parameter, and the first partition result includes a plurality of input nodes and a root node; the second processing module 1103 includes: a first acquisition unit configured to acquire delay attribute parameters of a plurality of input nodes; a first determining unit, configured to determine a minimum target delay attribute parameter from the plurality of delay attribute parameters according to a comparison result of the plurality of delay attribute parameters; the second determining unit is used for determining target quantity attribute parameters of the input nodes corresponding to the root nodes; a third determining unit, configured to determine a target area attribute parameter based on the last area attribute parameter and the output number of the root nodes corresponding to the first division result; a fourth determining unit, configured to determine a target iteration attribute parameter based on the previous iteration attribute parameter and the output number; a fifth determining unit, configured to determine a first target variable attribute parameter based on the target area attribute parameter, the target iteration attribute parameter, and the output number; a sixth determining unit, configured to traverse the input nodes of the root node, and determine, based on the output number of the input nodes, the number of input nodes whose output number meets a preset output number; a seventh determining unit configured to determine a partition attribute parameter based on the number of input nodes; the generating unit is used for generating first evaluation attribute information based on the first target variable attribute parameter, the target iteration attribute parameter, the target area attribute parameter, the target delay attribute parameter, the target quantity attribute parameter and the partition attribute parameter.

In an alternative embodiment, the second processing module 1103 includes: the judging unit is used for judging whether the first basic attribute parameter meets a preset condition or not; the first processing unit is used for processing the first basic attribute parameters when the first basic attribute parameters meet preset conditions to generate first evaluation attribute information; and the second processing unit is used for discarding the first division result which does not meet the preset condition when the first basic attribute parameter does not meet the preset condition.

In an alternative embodiment, the third processing module 1104 includes: a second acquisition unit configured to acquire a priority of the first evaluation attribute information; a seventh determining unit, configured to traverse the gate-level netlist according to the reverse topology sequence, and sequentially compare the first evaluation attribute information according to the sequence from low priority to high priority, to determine a first division result with the highest priority; wherein the first division result is characterized as a second division result; an eighth determination unit configured to determine a plurality of first target nodes based on the second division result.

In an alternative embodiment, the apparatus further comprises: the second acquisition module is used for acquiring identification values corresponding to a plurality of input nodes in the first division result; a determining module for determining a characteristic value corresponding to the identification value; the judging module is used for judging whether the characteristic values meet the preset requirement or not; and the fourth processing module is used for processing the first basic attribute to generate a first evaluation attribute if the plurality of characteristic values meet the preset requirements.

In an alternative embodiment, the first processing module 1102 includes: a ninth processing unit, configured to perform topology sequence processing on the plurality of nodes, and generate a plurality of fifth division results corresponding to the nodes; and the enumeration unit is used for enumerating the plurality of fifth division results and generating a first division result and a first basic attribute parameter.

Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.

The target netlist generation device in this embodiment is presented in the form of functional units, where the units are ASIC (Application SPECIFIC INTEGRATED Circuit) circuits, processors and memories that execute one or more software or firmware programs, and/or other devices that provide the above-described functionality.

The embodiment of the invention also provides computer equipment, which is provided with the XXX device shown in the figure 11.

Referring to fig. 12, fig. 12 is a schematic structural diagram of a computer device according to an alternative embodiment of the present invention, as shown in fig. 12, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 12.

The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.

Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform the methods shown in implementing the above embodiments.

The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.

The computer device further comprises input means 30 and output means 40. The processor 10, memory 20, input device 30, and output device 40 may be connected by a bus or other means, for example in fig. 12.

The input device 30 may receive input numeric or character information and generate key signal inputs related to user settings and function control of the computer apparatus, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, a pointer stick, one or more mouse buttons, a trackball, a joystick, and the like. The output means 40 may include a display device, auxiliary lighting means (e.g., LEDs), tactile feedback means (e.g., vibration motors), and the like. Such display devices include, but are not limited to, liquid crystal displays, light emitting diodes, displays and plasma displays. In some alternative implementations, the display device may be a touch screen.

The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.

Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.

Claims

1. A method for generating a target netlist, the method comprising:

Obtaining a gate-level netlist; wherein the gate-level netlist comprises a plurality of directed acyclic graphs, each of the directed acyclic graphs comprising a plurality of nodes;

dividing the plurality of nodes to generate a first dividing result corresponding to the nodes and a first basic attribute parameter corresponding to the first dividing result;

processing the first basic attribute parameters to generate first evaluation attribute information corresponding to the first division result;

Processing the gate-level netlist according to the first evaluation attribute information, and determining a first target node for mapping and a second division result corresponding to the first target node;

generating a target netlist based on the first target node and the second partitioning result;

The first basic attribute parameters comprise delay attribute parameters, input node quantity attribute parameters, area attribute parameters, iteration attribute parameters, variable attribute parameters and partition attribute parameters, and the first partition result comprises a plurality of input nodes and root nodes; wherein the processing the first basic attribute parameter to generate first evaluation attribute information corresponding to the first division result includes:

Obtaining delay attribute parameters of a plurality of input nodes;

Determining the minimum target delay attribute parameter in the delay attribute parameters according to the comparison result of the delay attribute parameters;

determining target quantity attribute parameters of the input nodes corresponding to the root nodes;

determining a target area attribute parameter based on the last area attribute parameter and the output number of the root node corresponding to the first division result;

Determining a target area attribute parameter based on the last area attribute parameter and the output number of the root node corresponding to the first division result, wherein the determining comprises the following steps:

wherein i represents the number of input nodes, from 0 to k, k+1 input nodes are provided, fanout is the output number of the root node corresponding to the first division result, area is a target area attribute parameter, and area [ i ] is the last area attribute parameter;

Determining a target iteration attribute parameter based on the iteration attribute parameter of the last time and the output quantity;

determining a target iteration attribute parameter based on the iteration attribute parameter of the last time and the output number, including:

wherein iter represents the iteration round number, estFanout [ iter ] is a target iteration attribute parameter, and alpha is a constant value;

Determining a first target variable attribute parameter based on the target area attribute parameter, the target iteration attribute parameter, and the output number;

Determining a first target variable attribute parameter based on the target area attribute parameter, the target iteration attribute parameter, and the output number, comprising:

Wherein A is the area, and cost is the attribute parameter of the first target variable;

Traversing the input nodes of the root node, and determining the number of input nodes, the output number of which meets the preset output number, based on the output number of the input nodes;

Determining the partition attribute parameters based on the number of the input nodes; the dividing attribute parameters are the number of input nodes in each maximum fanout cone;

Generating first evaluation attribute information based on the first target variable attribute parameter, the target iteration attribute parameter, the target area attribute parameter, the target delay attribute parameter, the target number attribute parameter, and the partition attribute parameter;

processing the gate level netlist according to the first evaluation attribute information, determining a first target node for mapping and a second partitioning result corresponding to the first target node, including:

And dividing the first target node in the gate-level netlist again according to the first evaluation attribute information, and evaluating the gate-level netlist to determine the priority of the first target node compared with other nodes so as to determine an optimal second division result, thereby determining the first target node corresponding to the second division result.

2. The method of generating a target netlist according to claim 1, wherein after the gate level netlist is processed according to the first evaluation attribute information to determine a first target node for mapping and the second partitioning result corresponding to the first target node, the method further comprises:

performing iterative processing on the second division result and the first target node to generate a third division result and second basic attribute information corresponding to the third division result;

processing the second basic attribute information based on the first evaluation attribute information to generate second evaluation attribute information;

And processing the gate-level netlist according to the second evaluation attribute information, and determining a second target node and a fourth dividing result for mapping until the number of iterative execution times meets the preset number of times.

3. The method for generating a target netlist according to claim 1, wherein the processing the first basic property parameters to generate first evaluation property information corresponding to the first partitioning result includes:

judging whether the first basic attribute parameter meets a preset condition or not;

When the first basic attribute parameters meet the preset conditions, processing the first basic attribute parameters to generate first evaluation attribute information;

and when the first basic attribute parameter does not meet the preset condition, discarding the first division result which does not meet the preset condition.

4. The method of generating a target netlist according to claim 1, wherein the processing the gate level netlist according to the first evaluation attribute information to determine a first target node for mapping and the second partitioning result corresponding to the first target node comprises:

acquiring the priority of the first evaluation attribute information;

traversing the gate-level netlist according to the reverse topological order, sequentially comparing the first evaluation attribute information according to the order of the priorities from low to high, and determining the first division result with the highest priority; wherein the first division result is characterized as the second division result;

And determining a plurality of first target nodes based on the second division result.

5. The method of generating a target netlist according to claim 1, wherein prior to performing a partitioning process on the plurality of nodes to generate a first partitioning result corresponding to the nodes and a first basic attribute parameter corresponding to the first partitioning result, the method further comprises:

acquiring identification values corresponding to a plurality of input nodes in the first division result;

Determining a characteristic value corresponding to the identification value;

judging whether the characteristic values meet preset requirements or not;

and if the characteristic values meet the preset requirement, processing the first basic attribute to generate a first evaluation attribute.

6. The method for generating a target netlist according to claim 1, wherein the partitioning the plurality of nodes to generate a first partitioning result corresponding to the nodes and a first basic attribute parameter corresponding to the first partitioning result comprises:

Performing topology sequence processing on the plurality of nodes to generate a plurality of fifth division results corresponding to the nodes;

enumerating the plurality of fifth division results to generate a first division result and the first basic attribute parameter.

7. A device for generating a target netlist, the device comprising:

The first acquisition module is used for acquiring a gate-level netlist; wherein the gate-level netlist comprises a plurality of directed acyclic graphs, each of the directed acyclic graphs comprising a plurality of nodes;

The first processing module is used for carrying out division processing on the plurality of nodes and generating a first division result corresponding to the nodes and a first basic attribute parameter corresponding to the first division result;

The second processing module is used for processing the first basic attribute parameters and generating first evaluation attribute information corresponding to the first division result;

The third processing module is used for processing the gate-level netlist according to the first evaluation attribute information and determining a first target node for mapping and a second division result corresponding to the first target node;

the generating module is used for generating a target netlist based on the first target node and the second partitioning result;

a second processing module comprising: a first acquisition unit configured to acquire delay attribute parameters of a plurality of input nodes;

A first determining unit, configured to determine a minimum target delay attribute parameter from the plurality of delay attribute parameters according to a comparison result of the plurality of delay attribute parameters;

The second determining unit is used for determining target quantity attribute parameters of the input nodes corresponding to the root nodes;

A third determining unit, configured to determine a target area attribute parameter based on the last area attribute parameter and the output number of the root nodes corresponding to the first division result;

a third determining unit configured to, based on the formula: Determining a target area attribute parameter; wherein i represents the number of input nodes, from 0 to k, k+1 input nodes are provided, fanout is the output number of the root node corresponding to the first division result, area is a target area attribute parameter, and area [ i ] is the last area attribute parameter;

A fourth determining unit, configured to determine a target iteration attribute parameter based on the previous iteration attribute parameter and the output number;

A fourth determining unit configured to, based on the formula: determining a target iteration attribute parameter; wherein iter represents the iteration round number, estFanout [ iter ] is a target iteration attribute parameter, and alpha is a constant value;

a fifth determining unit, configured to determine a first target variable attribute parameter based on the target area attribute parameter, the target iteration attribute parameter, and the output number;

A fifth determining unit configured to, based on the formula: Determining a first target variable attribute parameter; wherein A is the area, and cost is the attribute parameter of the first target variable;

A sixth determining unit, configured to traverse the input nodes of the root node, and determine, based on the output number of the input nodes, the number of input nodes whose output number meets a preset output number;

A seventh determining unit configured to determine a partition attribute parameter based on the number of input nodes; the dividing attribute parameters are the number of input nodes in each maximum fanout cone;

The generating unit is used for generating first evaluation attribute information based on the first target variable attribute parameter, the target iteration attribute parameter, the target area attribute parameter, the target delay attribute parameter, the target quantity attribute parameter and the partition attribute parameter;

And the third processing module is used for dividing the first target node in the gate-level netlist again according to the first evaluation attribute information, evaluating the gate-level netlist to determine the priority of the first target node compared with other nodes so as to determine an optimal second division result, and further determining the first target node corresponding to the second division result.

8. A computer device, comprising:

a memory and a processor, the memory and the processor being communicatively connected to each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the method of generating a target netlist according to any one of claims 1 to 6.

9. A computer-readable storage medium having stored thereon computer instructions for causing a computer to perform the method of generating a target netlist according to any of claims 1 to 6.