CN116467980B - Parameter solving method of standard unit circuit, electronic equipment and storage medium - Google Patents
Parameter solving method of standard unit circuit, electronic equipment and storage medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3315—Design verification, e.g. functional simulation or model checking using static timing analysis [STA]
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
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Abstract
The application relates to a parameter solving method of a standard unit circuit, electronic equipment and a storage medium. The method includes determining an equivalent circuit of a resistor-capacitor circuit connected to an output of a standard cell; solving the effective capacitance of the equivalent circuit based on static time sequence analysis to obtain the to-be-corrected output capacitance of the standard unit; determining a preset equivalent circuit matched with the equivalent circuit; inquiring correction parameters corresponding to the preset equivalent circuit in a correction parameter library, wherein the correction parameters are obtained according to the effective capacitance of the preset equivalent circuit determined based on static time sequence analysis and the effective capacitance of the preset equivalent circuit determined based on dynamic time sequence analysis; and correcting the output capacitance to be corrected according to the correction parameters to obtain the output capacitance of the standard unit. The scheme provided by the application corrects the standard unit output capacitance to be corrected based on the static time sequence analysis based on the correction parameters predetermined by the static time sequence analysis and the dynamic time sequence analysis, so that the solving speed and the solving precision of the standard unit output capacitance can be improved.
Description
Technical Field
The application belongs to the technical field of circuits, and particularly relates to a parameter solving method of a standard unit circuit, electronic equipment and a storage medium.
Background
With the increase of chip integration, various standard units such as inverters, and gates, etc. are increasingly used in chips.
For a standard cell, the output capacitance is a key index for determining the delay of the standard cell, and the speed and the accuracy for solving the output capacitance of the standard cell directly influence the speed and the accuracy for solving the delay of the standard cell. At present, two modes for solving the output capacitance of the standard unit are available: 1) Static time sequence analysis; 2) And (5) dynamic time sequence analysis. The accurate standard unit output capacitance can be obtained by solving based on dynamic time sequence analysis, and the process of solving the standard unit output capacitance takes longer time; the process of solving the standard cell output capacitance based on static time sequence analysis is short in time consumption, and the accuracy of the standard cell output capacitance obtained through solving is not high.
Therefore, how to improve the parameter solving speed and the solving precision of the standard unit circuit becomes a problem to be solved urgently.
Disclosure of Invention
In order to solve the technical problems, the application provides a parameter solving method of a standard unit circuit, electronic equipment and a computer storage medium, which can improve the parameter solving speed and solving precision of the standard unit circuit.
The application provides a solving method of a standard unit circuit, which comprises the following steps:
determining an equivalent circuit of a resistor-capacitor circuit connected with the output end of the standard unit based on a preset circuit model;
solving the effective capacitance of the equivalent circuit based on static time sequence analysis to obtain the output capacitance to be corrected of the standard unit;
determining a preset equivalent circuit matched with the equivalent circuit;
inquiring correction parameters corresponding to the preset equivalent circuits in a correction parameter library, wherein the correction parameter library comprises corresponding relations between a plurality of preset equivalent circuits and a plurality of correction parameters, and the correction parameters are obtained by processing a first effective capacitance of the preset equivalent circuits determined based on static time sequence analysis and a second effective capacitance of the preset equivalent circuits determined based on dynamic time sequence analysis when the preset equivalent circuits are set as the output of a standard unit;
and correcting the output capacitance to be corrected according to the correction parameters so as to obtain the output capacitance of the standard unit.
In one embodiment, the effective capacitance causes the delay produced by the standard cell to be the same as the delay produced by the equivalent circuit.
In an embodiment, the preset equivalent circuit and the equivalent circuit adopt the same preset circuit model.
In an embodiment, the solving the effective capacitance of the equivalent circuit based on static timing analysis to obtain the output capacitance to be corrected of the standard cell includes:
inquiring a nonlinear delay model library according to a first capacitance value of the equivalent circuit and the input conversion time of the standard unit, and determining the output conversion time of the standard unit, wherein the first capacitance value represents the overall capacitance of the equivalent circuit; based on the static time sequence analysis, solving the effective capacitance of the equivalent circuit according to the output conversion time of the standard unit, the resistance value of the equivalent circuit and a second capacitance value to obtain the output capacitance to be corrected of the standard unit, wherein the second capacitance value is the capacitance value of each capacitance in the equivalent circuit.
In an embodiment, the step of solving the effective capacitance of the equivalent circuit according to the output conversion time of the standard cell, the resistance value of the equivalent circuit, and the second capacitance value based on the static timing analysis to obtain the output capacitance to be corrected of the standard cell includes:
determining the effective capacitance of the equivalent circuit according to the output conversion time of the standard unit, the resistance value of the equivalent circuit and the second capacitance value; judging whether the effective capacitance converges or not; if not, returning the effective capacitor to the first capacitor value of the equivalent circuit and the input conversion time of the standard unit according to the first capacitor value of the equivalent circuit, inquiring a nonlinear delay model library, and determining the output conversion time of the standard unit; and if so, taking the effective capacitor as an output capacitor to be corrected of the standard unit.
In an embodiment, according to the output conversion time of the standard cell, the resistance value of the equivalent circuit, and the second capacitance value, the method for solving the effective capacitance of the equivalent circuit includes:
converting a time domain expression of the driving voltage of the standard unit into a frequency domain expression; determining a frequency domain expression of the driving current of the standard unit according to the frequency domain expression of the driving voltage, the resistance value of the equivalent circuit and the second capacitance value, and converting the frequency domain expression of the driving current into a time domain expression, wherein the time domain expression of the driving current is used for representing the output conversion time, the working voltage, the driving time of the standard unit, the resistance value of the equivalent circuit and the relation between the second capacitance value and the driving current; obtaining a target driving voltage selected by solving the delay of the standard unit and a target driving time corresponding to the target driving voltage; processing the time domain expression of the driving current according to the target driving time and the target driving voltage, so that the charging capacity of the driving current of the standard unit to the circuit under the target driving time is equal to the charging capacity of the effective capacitor of the equivalent circuit to the circuit under the target driving voltage; and transforming the expression obtained by processing to solve and obtain the effective capacitance of the equivalent circuit according to the output conversion time of the standard unit, the resistance value of the equivalent circuit and the second capacitance value.
In one embodiment, the step of establishing the correction parameter library includes:
constructing a preset equivalent circuit with a preset number; carrying out static time sequence analysis on each preset equivalent circuit, and determining a first effective capacitance of each preset equivalent circuit; performing the dynamic time sequence analysis on each preset equivalent circuit to determine a second effective capacitance of each preset equivalent circuit; determining the deviation between the first effective capacitance and the second effective capacitance of each preset equivalent circuit; and determining a correction parameter according to the deviation, and associating the correction parameter with a corresponding preset equivalent circuit to establish the correction parameter library.
In an embodiment, the step of performing the static timing analysis on each preset equivalent circuit to determine the first effective capacitance of each preset equivalent circuit includes:
based on the static time sequence analysis, determining a first effective capacitor of each preset equivalent circuit according to a resistance value and a capacitance value in each preset equivalent circuit and output conversion time of the standard unit corresponding to each preset equivalent circuit.
In an embodiment, determining a preset equivalent circuit matched with the equivalent circuit includes: comparing the resistance value and the capacitance value of the equivalent circuit with those of the preset equivalent circuit; and determining a preset equivalent circuit matched with the equivalent circuit according to the comparison result.
In an embodiment, after the correcting the output capacitance to be corrected according to the correction parameter to obtain the output capacitance of the standard cell, the method further includes: and inquiring a nonlinear delay model library according to the input conversion time of the standard unit and the output capacitance of the standard unit so as to solve and obtain the delay of the standard unit.
The application also provides an electronic device comprising a memory, a processor and a computer program stored in the memory and capable of running on the processor, wherein the processor executes the computer program to realize the steps of the parameter solving method of the standard cell circuit.
The application also provides a computer storage medium storing a computer program which, when executed by a processor, implements the steps of the parameter solving method of the standard cell circuit.
According to the parameter solving method, the electronic equipment and the computer storage medium of the standard unit circuit, the effective capacitance of the equivalent circuit is solved based on static time sequence analysis, the to-be-corrected output capacitance of the standard unit can be obtained quickly, the solving speed of the output capacitance of the standard unit is improved, in addition, the to-be-corrected output capacitance is corrected according to the correction parameters which are predetermined according to the solving result of the preset equivalent circuit based on the static time sequence analysis and the dynamic time sequence analysis, the accurate standard unit output capacitance can be obtained, the solving precision of the standard unit output capacitance is improved, in addition, in the process of solving the standard unit output capacitance, the dynamic time sequence analysis of the equivalent circuit is not needed, and the solving speed of the standard unit output capacitance can be further improved. Therefore, the solving speed and the solving precision of the standard unit output capacitance can be ensured at the same time.
Drawings
Fig. 1 is a flowchart of a parameter solving method of a standard cell circuit according to an embodiment of the application.
Fig. 2 is a schematic structural diagram of an equivalent circuit according to a first embodiment of the present application.
Fig. 3 is a schematic diagram of solving an effective capacitance of an equivalent circuit based on static timing analysis according to an embodiment of the present application.
Fig. 4 is a schematic diagram of an established correction parameter library according to an embodiment of the present application.
Fig. 5 is a schematic diagram of solving an effective capacitance of an equivalent circuit based on dynamic time sequence analysis according to an embodiment of the present application.
Fig. 6 is a schematic structural diagram of an electronic device according to a second embodiment of the present application.
Detailed Description
The technical scheme of the application is further elaborated below by referring to the drawings in the specification and the specific embodiments. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, "and/or" includes any and all combinations of one or more of the associated listed items.
Fig. 1 is a flowchart of a parameter solving method of a standard cell circuit according to an embodiment of the application. As shown in fig. 1, the parameter solving method of the standard cell circuit of the present application may include the following steps:
step S10: determining an equivalent circuit of a resistor-capacitor circuit connected with the output end of the standard unit based on a preset circuit model;
step S20: solving the effective capacitance of the equivalent circuit based on static time sequence analysis to obtain the to-be-corrected output capacitance of the standard unit;
step S30: determining a preset equivalent circuit matched with the equivalent circuit;
step S40: inquiring correction parameters corresponding to a preset equivalent circuit in a correction parameter library, wherein the correction parameter library comprises corresponding relations between a plurality of preset equivalent circuits and a plurality of correction parameters, and the correction parameters are obtained by processing a first effective capacitance of the preset equivalent circuit determined based on static time sequence analysis and a second effective capacitance of the preset equivalent circuit determined based on dynamic time sequence analysis when the preset equivalent circuit is set as the output of a standard unit;
step S50: and correcting the output capacitance to be corrected according to the correction parameters so as to obtain the output capacitance of the standard unit.
According to the method for solving the standard unit, the effective capacitance of the equivalent circuit is solved based on static time sequence analysis, the to-be-corrected output capacitance of the standard unit can be obtained rapidly, the solving speed of the output capacitance of the standard unit is improved, in addition, the to-be-corrected output capacitance is corrected according to the correction parameters established in advance based on the results of the static time sequence analysis and the dynamic time sequence analysis, the accurate output capacitance of the standard unit can be obtained, the solving precision of the output capacitance of the standard unit is improved, and in the process of solving the output capacitance of the standard unit, dynamic time sequence analysis of the equivalent circuit is not needed, and the solving speed of the output capacitance of the standard unit can be further improved.
Alternatively, the standard cells include inverters, and gates, etc., each corresponding to a plurality of cell circuits of different sizes and different driving capacities, and the standard cell circuit includes a standard cell and a resistor-capacitor circuit (RC circuit) connected to an output terminal of the standard cell. The preset circuit model is Pi model (Pi-model) and comprises two capacitors connected in parallel and a resistor connected in series with the two capacitors connected in parallel. Converting the resistor-capacitor circuit connected to the output of the standard cell based on pi model to obtain an equivalent circuit as shown in fig. 2, i.e. converting the resistor-capacitor circuit connected to the output of the standard cell to pi model circuit, wherein the first capacitor C 1 And a second capacitor C 2 In parallel, a resistor R is connected in series with a first capacitor C 1 And a second capacitor C 2 Between them.
In one embodiment, the solving the effective capacitance of the equivalent circuit based on the static timing analysis in the step S20 to obtain the output capacitance to be corrected of the standard cell includes:
inquiring a nonlinear delay model library according to a first capacitance value of the equivalent circuit and the input conversion time (Input Transition Time) of the standard unit, and determining the output conversion time (Output Transition Time) of the standard unit, wherein the first capacitance value represents the overall capacitance of the equivalent circuit;
based on static time sequence analysis, according to output conversion time of the standard unit, a resistance value of the equivalent circuit and a second capacitance value, solving an effective capacitance of the equivalent circuit to obtain an output capacitance to be corrected of the standard unit, wherein the second capacitance value is a capacitance value of each capacitance in the equivalent circuit.
The effective capacitance of the equivalent circuit is the correction capacitance to be output of the standard unit.
In one embodiment, based on static time sequence analysis, according to output conversion time of a standard unit, a resistance value of an equivalent circuit and a second capacitance value, solving an effective capacitance of the equivalent circuit to obtain a to-be-corrected output capacitance of the standard unit, including:
determining the effective capacitance of the equivalent circuit according to the output conversion time of the standard unit, the resistance value of the equivalent circuit and the second capacitance value;
judging whether the effective capacitance converges or not;
if the effective capacitance is not converged, the effective capacitance is used as a first capacitance value of an equivalent circuit, and the step of inquiring a nonlinear delay model library and determining the output conversion time of the standard unit is returned according to the first capacitance value of the equivalent circuit and the input conversion time of the standard unit;
and if so, taking the effective capacitance as the output capacitance to be corrected of the standard unit.
With continued reference to FIG. 2, the total capacitance C of the equivalent circuit is selected total =C 1 +C 2 As an initial first capacitance value, according to the total capacitance C total Input transition time Tr of standard cell i Querying a nonlinear delay model library to determine a first output transition time Tr of the standard cell 1 Then according to the first output conversion of the standard cellTime Tr 1 Resistor R, first capacitor C of equivalent circuit 1 Second capacitor C 2 Determining effective capacitance of equivalent circuit-C eff_s1 . Judging whether the effective capacitance converges or not, wherein the condition of the effective capacitance convergence comprises that the deviation between the effective capacitance values obtained by two adjacent calculation is in a preset range, the effective capacitance obtained by the first solving is the initial first capacitance value, and the effective capacitance obtained by the second solving is the effective capacitance C eff_s1 Thus, the initial first capacitance value and the effective capacitance C are determined eff_s1 Whether the deviation between the two capacitors is within a preset range can be judged, and whether the effective capacitance converges or not can be judged.
If the effective capacitance converges, the effective capacitance is C eff_s1 As the output capacitance to be corrected of the standard cell, if the effective capacitance is not converged, the effective capacitance is C eff_s1 As updated first capacitance value, and input transition time Tr of standard cell i Together, the nonlinear delay model library is queried again to determine the second output transition time Tr of the standard cell 2 Then according to the second output transition time Tr of the standard cell 2 Resistor R, first capacitor C of equivalent circuit 1 Second capacitor C 2 Determining effective capacitance C of equivalent circuit eff_s2 . Judging whether the effective capacitance converges or not, and calculating two C values of the effective capacitance at the moment eff_s2 And effective capacitance-C eff_s1 Whether the deviation between the two capacitors is within a preset range, if so, the effective capacitors are converged, and the effective capacitors are two C eff_s2 As the output capacitance to be corrected of the standard unit, if not, the effective capacitance is not converged, and the effective capacitance is two C eff_s2 And taking the effective capacitance as a first capacitance value of the equivalent circuit, continuing to execute the processes of searching the model library and solving the effective capacitance until the effective capacitance of the equivalent circuit converges, and taking the effective capacitance solved last time as the output capacitance to be corrected of the standard unit.
In an embodiment, according to the output conversion time of the standard unit, the resistance value of the equivalent circuit and the second capacitance value, the method for solving the effective capacitance of the equivalent circuit includes:
converting the time domain expression of the driving voltage of the standard unit into a frequency domain expression;
determining a frequency domain expression of the driving current of the standard unit according to the frequency domain expression of the driving voltage, the resistance value of the equivalent circuit and the second capacitance value, and converting the frequency domain expression of the driving current into a time domain expression, wherein the time domain expression of the driving current is used for representing the output conversion time, the working voltage, the driving time, the resistance value of the equivalent circuit and the relation between the second capacitance value and the driving current of the standard unit;
obtaining a target driving voltage selected by solving the delay of a standard unit and a target driving time corresponding to the target driving voltage;
processing the time domain expression of the driving current according to the target driving time and the target driving voltage, so that the charging electric quantity of the driving current of the standard unit to the circuit under the target driving time is equal to the charging electric quantity of the effective capacitor of the equivalent circuit to the circuit under the target driving voltage;
and transforming the expression obtained by the processing to solve and obtain the effective capacitance of the equivalent circuit according to the output conversion time of the standard unit, the resistance value of the equivalent circuit and the second capacitance value.
The delay generated by the standard unit is the same as the delay generated by the equivalent circuit, and when the charge capacity of the circuit to the drive current of the standard unit is equal to the charge capacity of the circuit to the effective capacitor of the equivalent circuit under the target drive voltage, the condition that the delay generated by the standard unit is the same as the delay generated by the equivalent circuit is satisfied. It should be appreciated that the same amount of power or the same delay may be the same or may be considered the same when within a predetermined deviation.
As shown in fig. 3 (a), when the driving voltage reachesAt the time, the driving time corresponds to +.>. According to the driving voltage and the driving timeTo obtain a time domain representation of the drive voltage of the standard cell:
wherein, the liquid crystal display device comprises a liquid crystal display device,represents the driving time of the standard cell to the equivalent circuit, < >>The driving voltage which shows the variation of the standard unit along with the driving time is the driving voltage source after the standard unit is equivalent,/or%>Representing the operating voltage of a standard cell, +.>Representation and->The driving time of the corresponding standard cell, i.e. the output transition time.
Referring to fig. 2 and (b) in fig. 3, the standard cell in fig. 2 is equivalent to a driving voltage source, so as to obtain a circuit shown in (b) in fig. 3, where circuit parameters include: driving voltage source acting on equivalent circuit and varying with output switching timeAnd a driving current I (t), a driving time-dependent current I passing through a first capacitor in the equivalent circuit 1 (t) current I as a function of drive time through a resistor and a second capacitor in the equivalent circuit 2 (t) wherein the first capacitance has a value of C 1 The value of the first capacitor is C 2 The value of the resistor is R.
According to the conversion relation between the time domain and the frequency domain, converting the circuit parameter shown in (b) in fig. 3 from the time domain to the frequency domain to obtain the circuit parameter shown in (c) in fig. 3, including: driving voltage sourceDriving voltage varying with driving frequency acting on equivalent circuitAnd a driving current I(s), a driving frequency-dependent current I passing through a first capacitor in the equivalent circuit 1 (s) a current I as a function of the driving frequency through a resistor and a second capacitor in the equivalent circuit 2 (s) wherein the value of the first capacitance is 1/C 1 s, the value of the second capacitor is 1/C 2 And s, the value of the resistor is R.
Correspondingly, converting the time domain expression of the driving voltage of the standard unit to obtain the frequency domain expression of the driving voltage of the standard unit:
wherein, the liquid crystal display device comprises a liquid crystal display device,represents the driving frequency of the standard cell to the equivalent circuit, < >>Representing the driving voltage of the standard cell as a function of the driving frequency.
According to the circuit and its circuit parameters shown in fig. 3 (c), the frequency domain expressions of the current through the first capacitor, the current through the resistor and the second capacitor, and the frequency domain expression of the driving current are determined as follows:
substituting the frequency domain expression of the driving voltage of the standard unit into the frequency domain expression I of the driving current to obtain a frequency domain expression II of the driving current as follows:
optionally, converting the frequency domain expression II of the driving current through inverse Laplace transformation to obtain a time domain expression of the driving current:
optionally, selectAs the target driving voltage for solving the delay of the standard cell, the target driving voltage can be determined from the relationship shown in FIG. 3 (a)>The target driving time corresponding to/2 is Tr/2.
As shown in (d) of fig. 3, at the target driving voltageWith/2 as the threshold point, the delay between the input voltage passing through the threshold point and the output voltage passing through the threshold point being the delay T of the standard cell d . In general, most nonlinear delay model libraries use +.>As a threshold point for calculating the standard cell delay, it is understood that the threshold point is not limited to +.>/2。
Therefore, in combination with (c), (d) and (e) in fig. 3, the effective capacitance of the equivalent circuit is satisfiedMake the markWhen the delay generated by the standard unit is the same as the delay generated by the equivalent circuit, the driving current of the standard unit charges the circuit at the target driving time Tr/2 and the effective capacitance of the equivalent circuit>At the target driving voltage->And/2, the charge quantity of the circuit is equal.
Based on the relationship of equal charge amount, according to the target driving time Tr/2 and the target driving voltageAnd/2, processing the time domain expression of the driving current to obtain the following expression:
wherein Q represents the amount of electricity. Transforming the expression obtained by processing, and solving to obtain the effective capacitance of the equivalent circuit according to the output conversion time of the standard unit, the resistance value of the equivalent circuit and the second capacitance value:
in one embodiment, the step of establishing a correction parameter library includes:
constructing a preset equivalent circuit with a preset number;
performing static time sequence analysis on each preset equivalent circuit to determine a first effective capacitance of each preset equivalent circuit;
performing dynamic time sequence analysis on each preset equivalent circuit to determine a second effective capacitance of each preset equivalent circuit;
determining the deviation between the first effective capacitance and the second effective capacitance of each preset equivalent circuit;
and determining correction parameters according to the deviation, and associating the correction parameters with corresponding preset equivalent circuits to establish a correction parameter library.
The preset equivalent circuit and the equivalent circuit adopt the same preset circuit model. Optionally, the built preset equivalent circuit covers the equivalent circuits of the RC network as possible, for example, 9 ten thousand preset equivalent circuits, where the resistance value and/or the capacitance value of any two preset equivalent circuits are different. Alternatively, a first effective capacitance C is employed eff_s And a second effective capacitance C eff_d Is indicative of the first effective capacitance C eff_s And a second effective capacitance C eff_d Is a deviation of (2). Numbering 9 ten thousand preset equivalent circuits, taking the number of the preset equivalent circuits as an abscissa and taking a first effective capacitor C eff_ s and a second effective capacitance C eff_d As ordinate, a correction parameter library as shown in fig. 4 is obtained, in which the first effective capacitance C eff_s And a second effective capacitance C eff_d The ratio of each preset equivalent circuit is taken as a correction parameter, and the number of each preset equivalent circuit uniquely corresponds to one first effective capacitor C eff_ s and a second effective capacitance C eff_d I.e. uniquely corresponds to a correction parameter.
In one embodiment, the step of performing static timing analysis on each preset equivalent circuit to determine the first effective capacitance of each preset equivalent circuit includes:
based on static time sequence analysis, determining a first effective capacitance of each preset equivalent circuit according to a resistance value and a capacitance value in each preset equivalent circuit and output conversion time of a standard unit corresponding to each preset equivalent circuit.
Specifically, the process of determining the first effective capacitance of the preset equivalent circuit based on the static timing analysis refers to the process of determining the effective capacitance of the equivalent circuit of the resistor-capacitor circuit connected to the output terminal of the standard cell based on the static timing analysis, which is not described herein.
In addition, lead toThe standard unit delay analysis of the preset equivalent circuit shown in fig. 5 (a) is performed to obtain an accurate delay calculation result, and under the same input signal driving (the input conversion time is Tr i ) Capacitance value C when the same standard cell delay is reached as in the preset equivalent circuit shown in FIG. 5 (a) eff (as shown in (b) of fig. 5), namely, the second effective capacitance of the preset equivalent circuit shown in (a) of fig. 5.
In an embodiment, the determining the preset equivalent circuit that matches the equivalent circuit in step S30 includes:
comparing the resistance value and the capacitance value of the equivalent circuit with the resistance value and the capacitance value of a preset equivalent circuit;
and determining a preset equivalent circuit matched with the equivalent circuit according to the comparison result.
Specifically, after the to-be-corrected output capacitance of the standard unit is obtained based on static time sequence analysis, the resistance value and the capacitance value of the equivalent circuit of the standard unit are compared with the resistance value and the capacitance value of a preset equivalent circuit, and the preset equivalent circuit matched with the equivalent circuit is determined. Based on the correction parameter library shown in fig. 4, corresponding correction parameters are queried according to the number of the matched preset equivalent circuit, and the output capacitance to be corrected is corrected according to the correction parameters, so that the output capacitance of the standard unit is obtained. By the method, when the output capacitance of the standard unit is solved, dynamic time sequence analysis is not needed, the solving speed is high, the correction parameters are obtained by combining the dynamic time sequence analysis in advance, and the solving precision can be ensured.
In an embodiment, after correcting the output capacitance to be corrected according to the correction parameter to obtain the output capacitance of the standard cell, the method further includes:
and according to the input conversion time of the standard unit and the output capacitance of the standard unit, inquiring a nonlinear delay model library to solve and obtain the delay of the standard unit.
According to the parameter solving method for the standard cell circuit, which is provided by the embodiment of the application, the to-be-corrected output capacitance of the standard cell can be quickly solved based on static time sequence analysis, and in addition, the to-be-corrected output capacitance is corrected according to the correction parameters which are established in advance based on the results of the static time sequence analysis and the dynamic time sequence analysis, so that the accurate standard cell output capacitance can be obtained. The method has the advantages that the accurate standard unit output capacitance obtained based on quick solving is used for inquiring the nonlinear delay model library, so that the solving speed and the solving precision of the standard unit delay can be improved, and in the process of solving the standard unit delay, dynamic time sequence analysis is not required to be carried out on an equivalent circuit, so that the solving speed of the standard unit delay can be further improved.
Fig. 6 is a schematic structural diagram of an electronic device according to a second embodiment of the present application. The electronic device of the present application includes: a processor 110, a memory 111 and a computer program 112 stored in the memory 111 and executable on the processor 110. The processor 110, when executing the computer program 112, implements the steps in the parameter solving method embodiment of the standard cell circuit described above.
Electronic devices may include, but are not limited to, processor 110, memory 111. It will be appreciated by those skilled in the art that fig. 6 is merely an example of an electronic device and is not meant to be limiting, and may include more or fewer components than shown, or may combine certain components, or different components, e.g., an electronic device may also include an input-output device, a network access device, a bus, etc.
The processor 110 may be a central processing unit (CentralProcessingUnit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-ProgrammableGateArray, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 111 may be an internal storage unit of the electronic device, such as a hard disk or a memory of the electronic device. The memory 111 may also be an external storage device of the electronic device, such as a plug-in hard disk provided on the electronic device, a smart memory card (SmartMediaCard, SMC), a security word (SecureDigital, SD) card, a flash memory card (FlashCard), or the like. Further, the memory 111 may also include both an internal storage unit and an external storage device of the electronic device. The memory 111 is used to store computer programs and other programs and data required by the electronic device. The memory 111 may also be used to temporarily store data that has been output or is to be output.
The application also provides a computer storage medium, wherein a computer program is stored on the computer storage medium, and the steps in the parameter solving method embodiment of the standard cell circuit are realized when the computer program is executed by a processor.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
In this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a list of elements is included, and may include other elements not expressly listed.
The foregoing is merely illustrative embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about variations or substitutions within the technical scope of the present application, and the application should be covered. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (10)
1. A method for solving parameters of a standard cell circuit, comprising:
determining an equivalent circuit of a resistor-capacitor circuit connected with the output end of the standard unit based on a preset circuit model;
solving the effective capacitance of the equivalent circuit based on static time sequence analysis to obtain the output capacitance to be corrected of the standard unit;
determining a preset equivalent circuit matched with the equivalent circuit;
inquiring correction parameters corresponding to the preset equivalent circuits in a correction parameter library, wherein the correction parameter library comprises corresponding relations between a plurality of preset equivalent circuits and a plurality of correction parameters, and the correction parameters are determined according to deviation between a first effective capacitance of the preset equivalent circuits determined based on static time sequence analysis and a second effective capacitance of the preset equivalent circuits determined based on dynamic time sequence analysis when the preset equivalent circuits are set to be output of standard units;
and correcting the output capacitance to be corrected according to the correction parameters so as to obtain the output capacitance of the standard unit.
2. The method of claim 1, wherein solving the effective capacitance of the equivalent circuit based on static timing analysis to obtain the to-be-corrected output capacitance of the standard cell comprises:
inquiring a nonlinear delay model library according to a first capacitance value of the equivalent circuit and the input conversion time of the standard unit, and determining the output conversion time of the standard unit, wherein the first capacitance value represents the overall capacitance of the equivalent circuit;
based on the static time sequence analysis, solving the effective capacitance of the equivalent circuit according to the output conversion time of the standard unit, the resistance value of the equivalent circuit and a second capacitance value to obtain the output capacitance to be corrected of the standard unit, wherein the second capacitance value is the capacitance value of each capacitance in the equivalent circuit.
3. The method of claim 2, wherein the step of solving the effective capacitance of the equivalent circuit based on the static timing analysis according to the output transition time of the standard cell, the resistance value of the equivalent circuit, and the second capacitance value to obtain the output capacitance to be corrected of the standard cell comprises:
determining the effective capacitance of the equivalent circuit according to the output conversion time of the standard unit, the resistance value of the equivalent circuit and the second capacitance value;
judging whether the effective capacitance converges or not;
if not, returning the effective capacitor to the first capacitor value of the equivalent circuit and the input conversion time of the standard unit according to the first capacitor value of the equivalent circuit, inquiring a nonlinear delay model library, and determining the output conversion time of the standard unit;
and if so, taking the effective capacitor as an output capacitor to be corrected of the standard unit.
4. A method according to claim 2 or 3, wherein solving the effective capacitance of the equivalent circuit based on the output transition time of the standard cell, the resistance value of the equivalent circuit, and the second capacitance value comprises:
converting a time domain expression of the driving voltage of the standard unit into a frequency domain expression;
determining a frequency domain expression of the driving current of the standard unit according to the frequency domain expression of the driving voltage, the resistance value of the equivalent circuit and the second capacitance value, and converting the frequency domain expression of the driving current into a time domain expression, wherein the time domain expression of the driving current is used for representing the output conversion time, the working voltage, the driving time of the standard unit, the resistance value of the equivalent circuit and the relation between the second capacitance value and the driving current;
obtaining a target driving voltage selected by solving the delay of the standard unit and a target driving time corresponding to the target driving voltage;
processing the time domain expression of the driving current according to the target driving time, so that the charging electric quantity of the driving current of the standard unit to the circuit under the target driving time is equal to the charging electric quantity of the effective capacitor of the equivalent circuit to the circuit under the target driving voltage;
and transforming the expression obtained by processing to solve and obtain the effective capacitance of the equivalent circuit according to the output conversion time of the standard unit, the resistance value of the equivalent circuit and the second capacitance value.
5. The method of claim 1, wherein the step of establishing the library of correction parameters comprises:
constructing a preset equivalent circuit with a preset number;
carrying out static time sequence analysis on each preset equivalent circuit, and determining a first effective capacitance of each preset equivalent circuit;
performing the dynamic time sequence analysis on each preset equivalent circuit to determine a second effective capacitance of each preset equivalent circuit;
determining the deviation between the first effective capacitance and the second effective capacitance of each preset equivalent circuit;
and determining a correction parameter according to the deviation, and associating the correction parameter with a corresponding preset equivalent circuit to establish the correction parameter library.
6. The method of claim 5, wherein the step of performing the static timing analysis on each of the predetermined equivalent circuits to determine a first effective capacitance of each of the predetermined equivalent circuits comprises:
based on the static time sequence analysis, determining a first effective capacitor of each preset equivalent circuit according to a resistance value and a capacitance value in each preset equivalent circuit and output conversion time of the standard unit corresponding to each preset equivalent circuit.
7. The method of claim 1, wherein determining a preset equivalent circuit that matches the equivalent circuit comprises:
comparing the resistance value and the capacitance value of the equivalent circuit with those of the preset equivalent circuit;
and determining a preset equivalent circuit matched with the equivalent circuit according to the comparison result.
8. The method of claim 1, wherein after correcting the output capacitance to be corrected according to the correction parameter to solve for the output capacitance of the standard cell, the method further comprises:
and inquiring a nonlinear delay model library according to the input conversion time of the standard unit and the output capacitance of the standard unit so as to solve and obtain the delay of the standard unit.
9. An electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the method according to any one of claims 1 to 8 when the computer program is executed.
10. A computer storage medium storing a computer program, which when executed by a processor performs the steps of the method according to any one of claims 1 to 8.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112100158A (en) * | 2020-09-21 | 2020-12-18 | 海光信息技术有限公司 | Standard cell library establishing method and device, electronic equipment and storage medium |
| CN113392608A (en) * | 2021-06-25 | 2021-09-14 | 成都海光集成电路设计有限公司 | Circuit generation method, circuit generation device, electronic equipment and storage medium |
| CN113466725A (en) * | 2020-03-31 | 2021-10-01 | 比亚迪股份有限公司 | Method and device for determining state of charge of battery, storage medium and electronic equipment |
| US11443089B1 (en) * | 2021-03-15 | 2022-09-13 | Amazon Technologies, Inc. | Timing verification of non-standard library blocks |
| CN115688641A (en) * | 2022-10-28 | 2023-02-03 | 南京美辰微电子有限公司 | Method and system for representing variation parameters on standard cell sheet |
| CN115964973A (en) * | 2022-12-30 | 2023-04-14 | 南京邮电大学 | Unit delay calculation method of composite current source model |
| CN116257992A (en) * | 2023-02-14 | 2023-06-13 | 三峡大学 | Fractional order switch capacitor network and efficiency evaluation method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8225248B2 (en) * | 2005-10-24 | 2012-07-17 | Cadence Design Systems, Inc. | Timing, noise, and power analysis of integrated circuits |
| WO2013018061A1 (en) * | 2011-08-03 | 2013-02-07 | Ben Gurion University Of The Negev Research And Development Authority | Device and method for dual-mode logic |
-
2023
- 2023-06-19 CN CN202310727158.8A patent/CN116467980B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113466725A (en) * | 2020-03-31 | 2021-10-01 | 比亚迪股份有限公司 | Method and device for determining state of charge of battery, storage medium and electronic equipment |
| CN112100158A (en) * | 2020-09-21 | 2020-12-18 | 海光信息技术有限公司 | Standard cell library establishing method and device, electronic equipment and storage medium |
| US11443089B1 (en) * | 2021-03-15 | 2022-09-13 | Amazon Technologies, Inc. | Timing verification of non-standard library blocks |
| CN113392608A (en) * | 2021-06-25 | 2021-09-14 | 成都海光集成电路设计有限公司 | Circuit generation method, circuit generation device, electronic equipment and storage medium |
| CN115688641A (en) * | 2022-10-28 | 2023-02-03 | 南京美辰微电子有限公司 | Method and system for representing variation parameters on standard cell sheet |
| CN115964973A (en) * | 2022-12-30 | 2023-04-14 | 南京邮电大学 | Unit delay calculation method of composite current source model |
| CN116257992A (en) * | 2023-02-14 | 2023-06-13 | 三峡大学 | Fractional order switch capacitor network and efficiency evaluation method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 基于28NM工艺ASIC芯片的静态时序分析与优化;翦彦龙;中国优秀硕士学位论文全文数据库 (信息科技辑)(第12期);I135-227 * |
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