CN113836844B

CN113836844B - Dynamic time sequence analysis method based on event propagation

Info

Publication number: CN113836844B
Application number: CN202110993095.1A
Authority: CN
Inventors: 林亦波; 张作栋; 郭资政; 王润声; 黄如
Original assignee: Peking University
Current assignee: Peking University
Priority date: 2021-08-27
Filing date: 2021-08-27
Publication date: 2023-09-22
Anticipated expiration: 2041-08-27
Also published as: CN113836844A

Abstract

The invention provides a dynamic time sequence analysis method based on event propagation, and belongs to the field of integrated circuit design automation. The dynamic time sequence analysis provided by the invention is mainly divided into: event generation at the input node, propagation of events at the internal node, reverse timing analysis and path reporting. Meanwhile, the method provided by the invention supports the acceleration of multithreading, which is distributed to different CPU cores. Therefore, the invention can accurately calculate the time sequence information, and can analyze the long-period time sequence analysis of a large-scale circuit through the internal memory recovery and the multi-core parallel mechanism.

Description

Dynamic time sequence analysis method based on event propagation

Technical Field

The invention relates to a dynamic time sequence analysis method based on event propagation (event-based), belonging to the field of integrated circuit design automation (electronic design automation).

Background

As microelectronic processes continue to scale down, various non-ideal effects such as process fluctuations (process variation) and device aging (transser) become more severe, resulting in greater and greater circuit performance fluctuations (performance variation). To ensure that a circuit will function properly in a variety of usage scenarios, designers typically use static timing analysis (static timing analysis) to estimate the worst-case performance of the circuit and design the circuit under constraints.

In order to reduce underestimation of performance, new design methods have been proposed in recent years, such as dynamic clock/voltage scaling (dynamic frequency/voltage scaling) and approximation calculation (approximate computing). Dynamic clock/voltage regulation adjusts the operating frequency or voltage according to real-time operating scenarios to achieve better performance or higher energy efficiency. Approximation calculations allow errors in the circuitry to be tolerated, taking advantage of the fault tolerance of the program or algorithm itself. These new design approaches can be free of pessimistic limitations of static analysis, but require dynamic information such as dynamic timing margin (dynamic timing slack) and slew rate (switching activity) to guide these optimization strategies.

The purpose of the dynamic timing analysis is to calculate the delay and slew rate of the circuit under the actual input vector. Conventional dynamic timing analysis methods are implemented using gate level simulations with delay de-scaling, where the delay de-scaling file is each cell delay resulting from graph-based static timing analysis. And then analyzing the time sequence and the turnover rate according to the waveform file generated by simulation. This approach has two major drawbacks: the calculation of the time sequence information is inaccurate and the simulation of a large-scale circuit with a long period is difficult to support.

The first drawback is that the delay of the delay-inverse is derived based on a graph-based static timing analysis, which uses the largest input signal transition time when calculating the output signal transition time of one multiple-input unit, i.e. the graph-based static timing analysis overestimates the output signal transition time of each multiple-input unit, while overestimating the delay of the next several stages of the signal. Therefore, the path delay obtained by static timing analysis based on the graph in the large-scale circuit is higher than the true value, and the path delay obtained by dynamic timing analysis using the delay inverse is also higher than the true value. Moreover, gate level circuit simulation is performed using erroneous delay information, and the resulting gate level flip rate may also be erroneous.

The second drawback is that conventional dynamic timing analysis methods have difficulty supporting long-period simulation of large-scale circuits. Conventional dynamic timing analysis is to analyze delay and flip information in each cycle using the generated waveforms after gate level simulation. However, the number of nodes in a large-scale circuit is very large, if the time sequence of a very long period is analyzed to obtain statistical information, the waveform file generated by gate level simulation is very large, the requirement on storage is very high, and a lot of running time is wasted on reading and writing of IO files. This greatly limits the use scenarios of conventional dynamic timing analysis.

Therefore, a dynamic time sequence analysis method which can accurately analyze time sequence information and support long-period simulation of a large-scale circuit is very important for a circuit optimization strategy under an advanced node.

Disclosure of Invention

The invention provides a dynamic time sequence analysis method based on event propagation, which can realize long-period dynamic time sequence analysis of a large-scale simulation circuit.

The dynamic analysis method based on event propagation integrates logic simulation and time sequence calculation in the same program. The method defines signal switching on an internal node in a simulation circuit as an event, the event has basic attributes of switching time (transition time) and arrival time (arrival time), step-by-step transmission of the event is obtained according to logic analysis, delay of each event transmission and signal switching time of a new event are calculated according to a standard cell library (standard cell library), and event arrival time on a final time sequence endpoint node can be accurately calculated.

The invention provides a dynamic time sequence analysis method based on event propagation, which specifically comprises the following steps: initialization of the data structure and cycle-by-cycle timing analysis, wherein the data structure initialization comprises: firstly, reading in a standard cell library and establishing a lookup table; then reading in a circuit netlist, establishing a time sequence diagram, pruning the complete time sequence diagram according to a designated time sequence endpoint, only reserving units and wires related to the time sequence endpoint, sorting the units inside by using topological sorting, setting the values of all input nodes to 0, and initializing the states of all internal nodes; the cycle-by-cycle timing analysis includes: generating an event on an input node, taking the input node as a 0 th stage on a time sequence diagram, starting to propagate the event on an internal node step by step, traversing all time sequence endpoints after all event propagation is completed, finding out the event with the maximum arrival time, wherein the corresponding delay and path are the maximum delay and the triggered longest path in the period, deleting all event information after each period is finished, and only keeping the current state of each node.

The invention can analyze the longest path triggered by the input of each period and the corresponding path delay of a circuit under the appointed input vector and working condition. The method provided by the invention supports dividing all the periods into a plurality of parts and distributing the parts to different CPU cores so as to realize the acceleration of multithreading. Therefore, the running time of the newly proposed dynamic time sequence analysis method is in a linear relation with the total cycle number, and the time sequence analysis with a long cycle can be supported.

Drawings

FIG. 1 is a flow chart of a dynamic timing analysis method based on event propagation according to the present invention.

Detailed Description

The flow of the specific embodiment provided by the invention is shown in fig. 1, and each part of the flow will be described in detail and clearly with reference to the schematic drawings. The dynamic time sequence analysis method based on event propagation is divided into two parts, wherein the first part is the initialization of a data structure, and the second part is the time sequence analysis of cycle by cycle.

Initializing a data structure: the files required for dynamic timing analysis are mainly the circuit netlist (netlist), the input vectors and the standard cell library. The data structures required are mainly timing diagrams (timing graphs) and look-up tables (LUTs) of delay and conversion times. The initialization of the data structure of the invention specifically comprises the following steps: firstly, reading in a standard cell library, and establishing a lookup table; then reading in the circuit netlist, creating a timing diagram, pruning the complete timing diagram according to the designated critical timing endpoint (critical endpoint), and only retaining the cells and wires associated with the critical timing endpoint, thereby greatly reducing the scale of the analysis. After the timing diagram is established, the cell ordering inside is graded by using topological ordering. In the case of gradation, the input of the cell of each stage is required to be smaller than the level of the cell, so that the timing can be updated stepwise. Finally, the values of all input nodes are set to 0 and the states of all internal nodes are initialized.

Cycle-by-cycle timing analysis: the cycle-by-cycle timing analysis is divided into the following sections within each cycle: events on the input nodes are generated, the input events are propagated forward on the internal nodes, reverse timing analysis and path reporting. After each period is finished, deleting all event information, and only keeping the current state of each node.

Wherein an event on the input node is generated: the input event is a change in the value on the input port, meaning that the input of the present cycle changes with the cycle, and there is a level switch, i.e., an event is generated. This event will change the state of some nodes inside, and possibly also the state of the output node. Each cycle starts and the value of each input node is compared according to the input node vector to follow the cycle, if the two are different, an input event is added to the node. The switching time of the input event is the input signal switching time defined by the user, and the arrival time of the input event is the user defined external delay plus a random number as the input uncertainty (input uncertainty).

Forward propagating input event: after all the input events are generated, the input node is used as the 0 th level on the time sequence diagram, and the events start to be propagated backward step by step. The algorithm of event propagation is divided into propagation on logic gates and propagation on connection lines.

The event propagation on the connection is relatively simple, and because there is only delay on the connection and no change of the event, the event propagation on the connection only needs to add one on-line delay. The propagation of events at the logic gates is complex, especially for multiple input logic gates, because not every input event causes a change in the output. Therefore, all input events are time ordered, then it is judged according to the time order whether the output of the unit will change at each time point, if so, it is indicated that an event will be newly generated at the output node. The arrival time and transition time of the event are then calculated based on the delay and output transition time of the cell, completing the propagation of the event on one cell. And the whole time is updated, and unreasonable events on the output node are deleted. Progressive propagation of events ends when an end of time sequence such as an input node or output port of a D flip-flop is encountered.

Reverse timing analysis and path reporting: after all the events are propagated, traversing all the time sequence endpoints to find the event with the maximum arrival time, wherein the corresponding delay and path are the maximum delay and the triggered longest path in the period.

In order to accelerate dynamic time sequence analysis under a long simulation period, the invention is distributed to different CPU cores to realize multi-thread acceleration, provides multi-core acceleration of period parallelism, and is different from parallel acceleration of other simulation software by adopting a netlist division method. Considering that dynamic time sequence analysis not only depends on the input of a period, but also depends on the state of each node of a current circuit, adjacent parts are required to be overlapped when the period is divided, for example, a circuit of a two-stage pipeline is required to perform 1000-period analysis, if the period is divided into 10 cores to be parallel, the first core simulates 0 to 100 periods, the second core simulates 99 to 200 periods, and the like. Two cycles are overlapped because the circuit requires two cycles to have each node inside in its state that would have been in at the beginning of the 101 th cycle.

The above-described embodiments are not intended to limit the present invention, and those skilled in the art may make various modifications and alterations without departing from the spirit and scope of the present invention, and the scope of the present invention is defined in the appended claims.

Claims

1. A method of dynamic timing analysis based on event propagation, comprising initialization of a data structure and cycle-by-cycle timing analysis, wherein the data structure initialization comprises: firstly, reading in a standard cell library and establishing a lookup table; then reading in a circuit netlist, establishing a time sequence diagram, pruning the complete time sequence diagram according to a designated time sequence endpoint, only reserving units and wires related to the time sequence endpoint, sorting the units inside by using topological sorting, setting the values of all input nodes to 0, and initializing the states of all internal nodes; the cycle-by-cycle timing analysis includes: generating an event on an input node, taking the input node as a 0 th stage on a time sequence diagram, starting to propagate the event on an internal node step by step, traversing all time sequence endpoints after all event propagation is completed, finding out the event with the maximum arrival time, wherein the corresponding delay and path are the maximum delay and the triggered longest path in the period, deleting all event information after each period is finished, and only keeping the current state of each node.

2. The event propagation based dynamic timing analysis method as set forth in claim 1, wherein each cycle starts by comparing the values of the input nodes according to the input node vector with the values of the input nodes of the cycle, and if the two are not identical, adding an input event to the node.

3. The event propagation based dynamic timing analysis method as set forth in claim 1, wherein the switching time of the event at the input node is a user-defined input signal switching time, and the arrival time of the input event is a user-defined external delay plus a random number as the input uncertainty.

4. The event propagation-based dynamic timing analysis method as set forth in claim 1, wherein the algorithm of the propagation of the event on the internal node is divided into the propagation on the logic gate and the propagation on the connection line.

5. The event propagation based dynamic timing analysis method as set forth in claim 4, wherein all input events are first time-ordered, then it is determined in time order whether the output of the unit will change at each time point, if so, it is indicated that an event will newly occur at the output node, and then the arrival time and transition time of the event are calculated based on the delay and output transition time of the unit, thereby completing the event propagation at one unit.

6. The event propagation based dynamic timing analysis method as set forth in claim 1, wherein all cycles are divided into a plurality of parts, adjacent cycle parts overlap, and different cycle parts are allocated to different CPU cores to implement multithreading.