CN112232006A - Standard cell library verification method and device, electronic equipment and storage medium - Google Patents
Standard cell library verification method and device, electronic equipment and storage medium Download PDFInfo
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Abstract
The application relates to a standard cell library verification method, a standard cell library verification device, electronic equipment and a storage medium, and belongs to the technical field of computers. The standard cell library verification method comprises the following steps: building a test circuit according to standard cells in a standard cell library to be verified, wherein the test circuit comprises all types of standard cells in the standard cell library to be verified, and takes a time sequence unit as input and a combined logic unit as output; generating a gate-level circuit netlist and a simulation circuit netlist according to the test circuit; performing static analysis on the gate-level circuit netlist and performing circuit simulation on the simulation circuit netlist; and verifying the quality of the standard cell library to be verified according to the static analysis result and the circuit simulation result. The time sequence information and the power consumption information of all core units in the standard unit library are verified by using the test circuits which are small in number and contain all types of standard units in the standard unit library, so that the standard unit library can be verified quickly, accurately and comprehensively.
Description
Technical Field
The application belongs to the technical field of computers, and particularly relates to a standard cell library verification method and device, electronic equipment and a storage medium.
Background
The standard cell library is used as a core element of digital circuit design, and the quality assurance of the standard cell library is one of the necessary conditions for the success of the circuit design. As the size of transistors in digital circuit designs shrink, the accuracy of the feature information in the standard cell library has an increasing impact on the digital circuit design. The accuracy of the time sequence information directly influences the static time sequence analysis and the signing and checking of the final design. The power consumption (power) value affects the power analysis and approving of the design. Therefore, the verification of the accuracy of the timing information of the standard cell library is very important.
In the conventional numerical verification of the standard cell library, a single standard cell (cell) is taken as an analysis object, and simulation verification is performed on a corresponding coordinate point in time delay of the cell. And because the number of cells (thousands to tens of thousands) in the standard cell library is large, a large amount of resources are needed for simulation, so that the simulation workload is huge and the simulation efficiency is low.
Disclosure of Invention
In view of the above, an object of the present application is to provide a method and an apparatus for verifying a standard cell library, an electronic device, and a storage medium, so as to solve the problem of low efficiency in quality verification of an existing standard cell library.
The embodiment of the application is realized as follows:
in a first aspect, an embodiment of the present application provides a standard cell library verification method, including: building a test circuit according to standard cells in a standard cell library to be verified, wherein the test circuit comprises all types of standard cells in the standard cell library to be verified, and takes a time sequence unit as input and a combined logic unit as output; generating a gate-level circuit netlist and a simulation circuit netlist according to the test circuit; performing static analysis on the gate-level circuit netlist and performing circuit simulation on the simulation circuit netlist, wherein test excitation applied when the static analysis is performed on the gate-level circuit netlist is consistent with test excitation applied when the circuit simulation is performed on the simulation circuit netlist; and verifying the quality of the standard cell library to be verified according to the static analysis result and the circuit simulation result. In the embodiment of the application, the test circuit comprising all types of standard units in the standard unit library is built, the information of all core units in the standard unit library can be verified by using the standard units with small quantity, all the standard units do not need to be analyzed, and therefore the standard unit library can be verified quickly, accurately and comprehensively.
With reference to a possible implementation manner of the embodiment of the first aspect, building a test circuit according to a standard cell in a standard cell library to be verified includes: grouping all standard units in the standard unit library to be verified, and grouping the standard units with consistent functions into a group; and respectively selecting at least one standard cell from each group of standard cells, and building the test circuit according to the standard cells. In the embodiment of the application, when the test circuit is built, all standard units are grouped according to work, the standard units with the consistent functions are divided into one group, and then at least one standard unit is selected from each group to build the test circuit, so that the building speed of the test circuit can be greatly increased.
With reference to one possible implementation manner of the embodiment of the first aspect, the test circuit includes only one complete timing path from the input to the output. In the embodiment of the application, the built test circuit only comprises a complete time sequence path from input to output so as to improve the accuracy of the verification result and reduce the mutual interference among a plurality of time sequence paths.
With reference to one possible implementation manner of the embodiment of the first aspect, the method further includes: when the test circuit is built, if a multi-input standard unit exists in the test circuit, assigning values to other input ends of the multi-input standard unit except for the input ends connected with the time sequence path. In the embodiment of the application, when the test circuit is built, if a multi-input standard unit exists in the test circuit, other input ends of the multi-input standard unit except for the input end connected with the time sequence path need to be correctly assigned, so that the correctness of the circuit function is ensured, and the reliability of the verification result is improved.
In combination with a possible implementation of the embodiment of the first aspect, the test stimulus is generated by: and generating the test excitation meeting the test requirement according to the preset minimum pulse width of the clock signal and the setup time and the hold time of the preset test excitation relative to the clock signal. In the embodiment of the application, the test excitation meeting the test requirement is generated through the minimum pulse width of the clock signal and the setup time and the hold time of the preset test excitation relative to the clock signal, so that the reliability of the verification result is enhanced.
With reference to a possible implementation manner of the embodiment of the first aspect, verifying the quality of the standard cell library to be verified according to a static analysis result and a circuit simulation result includes: comparing the timing delay in the static analysis result with the timing delay in the circuit simulation result, and comparing the power consumption in the static analysis result with the power consumption in the circuit simulation result; and if the time sequence delay in the static analysis result is consistent with the time sequence delay in the circuit simulation result and the power consumption in the static analysis result is consistent with the power consumption in the circuit simulation result, the standard cell library to be verified passes the quality verification. In the embodiment of the application, the time sequence delay in the static analysis result is compared with the time sequence delay in the circuit simulation result, and the power consumption in the static analysis result is compared with the power consumption in the circuit simulation result, so that the time sequence information and the power consumption information of all core units in the standard unit library can be verified at the same time, and the verification speed is improved.
With reference to one possible implementation manner of the embodiment of the first aspect, comparing the timing delay in the static analysis result with the timing delay in the circuit simulation result includes: comparing the timing delay of the timing unit in the static analysis result with the timing delay of the timing unit in the circuit simulation result, and comparing the output timing delay of the test circuit in the static analysis result with the output timing delay of the test circuit in the circuit simulation result. In the embodiment of the application, the time sequence delay of the time sequence unit in the static analysis result is compared with the time sequence delay of the time sequence unit in the circuit simulation result, so that whether the establishment time, the holding time and the minimum pulse width in the standard unit library are reasonable or not is verified, and meanwhile, the output time sequence delay of the test circuit in the static analysis result is compared with the output time sequence delay of the test circuit in the circuit simulation result, so that whether the time sequence information of the standard unit library is reasonable or not is verified.
In combination with one possible implementation manner of the embodiment of the first aspect, before comparing the output timing delay of the test circuit in the static analysis result with the output timing delay of the test circuit in the circuit simulation result, the method further includes: determining that the timing delay of the timing unit in the static analysis result is consistent with the timing delay of the timing unit in the circuit simulation result. In the embodiment of the present application, before comparing the output timing delay of the test circuit in the static analysis result with the output timing delay of the test circuit in the circuit simulation result, it is required to determine that the timing delay of the timing unit in the static analysis result is consistent with the timing delay of the timing unit in the circuit simulation result, and if the timing delay of the timing unit in the static analysis result is not consistent with the timing delay of the timing unit in the circuit simulation result, subsequent comparison is not required, so as to improve the verification efficiency.
In a second aspect, an embodiment of the present application further provides a standard cell library verification apparatus, including: the system comprises a building module, a generating module, an analyzing and simulating module and a verifying module; the device comprises a building module, a test module and a control module, wherein the building module is used for building a test circuit according to standard units in a standard unit library to be verified, the test circuit comprises all types of standard units in the standard unit library to be verified, a time sequence unit is used as input, and a combined logic unit is used as output; the generating module is used for generating a gate-level circuit netlist and a simulation circuit netlist according to the test circuit; the analysis simulation module is used for carrying out static analysis on the gate-level circuit netlist and carrying out circuit simulation on the simulation circuit netlist, wherein the test excitation applied when the static analysis is carried out on the gate-level circuit netlist is consistent with the test excitation applied when the circuit simulation is carried out on the simulation circuit netlist; and the verification module is used for verifying the quality of the standard cell library to be verified according to the static analysis result and the circuit simulation result.
In a third aspect, an embodiment of the present application further provides an electronic device, including: a memory and a processor, the processor coupled to the memory; the memory is used for storing programs; the processor is configured to invoke a program stored in the memory to perform the method according to the first aspect embodiment and/or any possible implementation manner of the first aspect embodiment.
In a fourth aspect, embodiments of the present application further provide a storage medium, on which a computer program is stored, where the computer program is executed by a processor to perform the method provided in the foregoing first aspect and/or any one of the possible implementation manners of the first aspect.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. The foregoing and other objects, features and advantages of the application will be apparent from the accompanying drawings. Like reference numerals refer to like parts throughout the drawings. The drawings are not intended to be to scale as practical, emphasis instead being placed upon illustrating the subject matter of the present application.
Fig. 1 shows a flowchart of a standard cell library verification method provided in an embodiment of the present application.
Fig. 2 shows a schematic diagram of a built test circuit provided in an embodiment of the present application.
FIG. 3 is a timing diagram of test stimulus and clock signals provided by an embodiment of the present application.
Fig. 4 is a flowchart illustrating a further standard cell library verification method provided in an embodiment of the present application.
Fig. 5 shows a block diagram of a standard cell library verification apparatus according to an embodiment of the present application.
Fig. 6 shows a schematic structural diagram of an electronic device provided in an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, relational terms such as "first," "second," and the like may be used solely in the description herein to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Further, the term "and/or" in the present application is only one kind of association relationship describing the associated object, and means that three kinds of relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone.
Due to the large number of cells in a standard cell library, quality assurance requires extensive quality checks and testing. In order to efficiently, quickly and comprehensively inspect the numerical information in the standard cell, the embodiment of the application provides a standard cell library verification method, which comprises the steps of analyzing the information of all standard cells in a standard cell library, screening, generating a corresponding gate-level circuit netlist (such as verilog netlist) and a corresponding simulation circuit netlist (such as spice netlist), simulating by using a static timing analysis tool and a simulation tool, verifying the Quality of the standard cell library to be verified according to a static analysis result and a circuit simulation result, and realizing Quality Assurance (Quality Assurance, QA) of data such as timing, constraint, power consumption and the like of the standard cell library, so that the numerical information in the standard cell can be efficiently, quickly and comprehensively inspected, the circuit design problem caused by the fact that the timing information of the standard cell library is not correct is reduced, and the Quality of the standard cell library is ensured. For ease of understanding, the standard cell library verification method provided in the embodiments of the present application will be described below with reference to fig. 1.
Step S101: and building a test circuit according to the standard cells in the standard cell library to be verified, wherein the test circuit comprises all types of standard cells in the standard cell library to be verified, and takes the time sequence cell as input and the combined logic cell as output.
When quality verification is required to be performed on a standard cell library to be verified, in order to efficiently, quickly and comprehensively complete verification of numerical information in standard cells, in the embodiment of the application, the standard cell library is analyzed based on functions provided by the standard cell library and time sequence arc information (timing arc) of the standard cell library, all types of standard cells are screened out, and a test circuit is built according to the standard cells, so that the built test circuit comprises all types of standard cells in the standard cell library to be verified. When the test circuit is built, the sequential unit is used as an input, the combined logic unit is used as an output, that is, the test circuit starts with the sequential unit (such as a flip-flop, a level latch, and the like), an unlimited number of logic units (such as logic units of an and gate, a not gate, an or gate, a buffer, an inverter, an adder, and the like) are connected after the output of the sequential unit, and finally the built test circuit is finished with the output of the combined logic unit, and a schematic diagram of the built test circuit is shown in fig. 2.
It should be noted that, if each standard cell is classified according to a large category, each standard cell may be classified as a sequential cell or a logical cell. If the time sequence unit is further divided, the time sequence unit can be divided into subclasses such as a trigger, a level latch and the like, and the logic unit can be further divided into subclasses such as an AND gate, an NOT gate, a NOR gate, an adder, a buffer and the like.
In order to build a test circuit more quickly, in an optional implementation manner, all standard cells in a standard cell library to be verified may be grouped, standard cells with the consistent functions are grouped into one group, then at least one standard cell is selected from each group of standard cells, and the test circuit is built according to the standard cells. When the test circuit is built, the time sequence unit is used as input, and the combined logic unit is used as output. When the test circuit is built, one standard cell can be selected from the same type of standard cell group, or a plurality of standard cells can be selected. Wherein the number of standard cells selected from the different types of standard cell groups may be different.
The test circuit only includes a complete timing path from input to output, i.e. from CLK (clock) to Q (output) of the timing unit, and then transmits downwards until the final output. To ensure the accuracy of the results, only one timing path is used by one test circuit during testing. In the process of building the test circuit, the functional correctness of the time sequence path of the standard cell needs to be ensured. For the multi-input standard unit, one input is connected with the time sequence path, and other input ends of the multi-input standard unit need to be correctly assigned with values, so that the functional correctness of the time sequence path of the standard unit is ensured. For example, the standard unit using multiple inputs in the building process includes an and gate, if two input ends of the and gate are A, B, respectively, if point a is currently used as an input path of data input, point B needs to be always set to 1, so as to ensure that data can be correctly output when being input into the and gate from point a. When assigning values to other input ends of the multi-input standard cell except the input end connected with the timing path, the values can be obtained through analysis by various methods, for example, based on accurate analysis of a timing condition when in a standard cell library to be verified, or based on analysis of a function/truth table of the multi-input standard cell, for example, if the multi-input standard cell is an and gate, the value assigned to the other input end is 1, and if the multi-input standard cell is an or gate, the value assigned to the other input end is 0.
In order to more fully verify the timing arc (timing arc) of the different inputs to outputs in a standard cell, in an alternative embodiment, multiple test circuits may be created. The types, the numbers and the positions of the standard cells included in the plurality of test circuits are the same, except that the timing paths from the input to the output are different, for example, the timing path of one test circuit is from CLK to Q1, and the timing path of another test circuit is from CLK to Q2.
Step S102: and generating a gate-level circuit netlist and a simulation circuit netlist according to the test circuit.
After the test circuit is built according to the standard cells in the standard cell library to be verified, a corresponding gate-level circuit netlist (such as verilog netlist) and a corresponding simulation circuit netlist (such as spice netlist) can be generated according to the built test circuit. The process of generating the gate-level circuit netlist and the simulation circuit netlist from the test circuit is well known to those skilled in the art and will not be described here.
Step S103: and performing static analysis on the gate-level circuit netlist and performing circuit simulation on the simulation circuit netlist.
After obtaining the gate-level circuit netlist and the simulation circuit netlist, performing static analysis on the gate-level circuit netlist to obtain a static analysis result including timing delays of connection points (net) in the timing path (such as the output end of the timing circuit, the output end of the and gate, or the output end … … of the gate and the output end of the buffer in fig. 2) and power consumption of the whole test circuit, and performing circuit simulation on the simulation circuit netlist to obtain a circuit simulation result including timing delays of the connection points (net) in the timing path and power consumption of the whole test circuit. The test excitation applied when the static analysis is carried out on the gate-level circuit netlist is consistent with the test excitation applied when the circuit simulation is carried out on the simulation circuit netlist, so that the comparison conditions of the gate-level circuit netlist and the simulation circuit netlist are completely consistent.
In the static analysis, the analysis needs to be performed by Electronic Design Automation (EDA) tools, such as Prime Time (PT) and Design Compiler (DC). When static time sequence analysis is carried out, delay of each connection point (net) in the corresponding static time sequence path can be obtained by analyzing the rise and fall situation on the time sequence path, utilizing the characteristic information in the standard cell library to be verified and in a lookup table mode. When static power consumption analysis is carried out, the power consumption consumed on the corresponding net is calculated by combining the rising and falling conditions of all the connection points (net) in time sequence analysis in a mode of searching a table in a standard unit library to be verified, and then the power consumption of the whole test circuit is calculated (for example, the total power consumption is the sum of the power consumption of all the connection points net). The specific static analysis process is well known to those skilled in the art and will not be described herein.
In circuit Simulation, Simulation may be performed by means of a Simulation tool, such as a Simulation circuit simulator (Simulation program with integrated circuit simulator).
Wherein, in static analysis and circuit simulation, test excitation is required to be applied. The test stimulus may be generated by: the test excitation meeting the test requirements is generated according to a preset minimum pulse width (min-pulse-width) of the clock signal and a preset setup time (setup) and hold time (hold) of the test excitation relative to the clock signal. When generating the test stimulus, it is necessary to set constraints, such as the input transition (input transition) between D1 and CLK and the parameter of the output load (load) of the test circuit within the allowable range of the characteristic value of the standard cell library to be verified, and then according to the set input transition (input transition) between D1 and CLK and the parameter of the output load (load), the corresponding setup, hold, min-pulse-width information can be obtained by looking up the table. Then, according to the obtained minimum pulse width of the clock signal, and the setup time and hold time, a test stimulus meeting the test requirement can be generated, so that the setup time and hold time of the generated test stimulus relative to the clock signal are consistent with the previously obtained setup and hold. FIG. 3 is a timing diagram of test stimuli, clock signals, and output signals. D1 is the test stimulus and Q1 is the output signal.
Step S104: and verifying the quality of the standard cell library to be verified according to the static analysis result and the circuit simulation result.
After the static analysis result and the circuit simulation result are obtained, the quality of the standard cell library to be verified is verified according to the static analysis result and the circuit simulation result, and whether the quality of the standard cell library to be verified is qualified or not can be quickly and accurately determined.
The verification process may be: comparing the timing delay in the static analysis result with the timing delay in the circuit simulation result, and comparing the power consumption in the static analysis result with the power consumption in the circuit simulation result. And if the time sequence delay in the static analysis result is consistent with the time sequence delay in the circuit simulation result, and the power consumption in the static analysis result is consistent with the power consumption in the circuit simulation result, the standard cell library to be verified is represented to pass quality verification. It should be noted that, in comparison, it can be considered to be consistent as long as the error of the two is within the allowable range, for example, if the error of the timing delay in the static analysis result and the timing delay in the circuit simulation result is within the allowable range, it is considered that the timing delay in the static analysis result is consistent with the timing delay in the circuit simulation result, and similarly, if the error of the power consumption in the static analysis result and the power consumption in the circuit simulation result is within the allowable range, it is considered that the power consumption in the static analysis result is consistent with the power consumption in the circuit simulation result.
The timing delay in the static analysis result and the timing delay in the circuit simulation result can be simultaneously compared, and the power consumption in the static analysis result and the power consumption in the circuit simulation result are compared; or comparing the time sequence delay in the static analysis result with the time sequence delay in the circuit simulation result, and comparing the power consumption in the static analysis result with the power consumption in the circuit simulation result when the time sequence delay in the static analysis result is consistent with the time sequence delay in the circuit simulation result; or vice versa, for example, comparing the power consumption in the static analysis result with the power consumption in the circuit simulation result, and comparing the timing delay in the static analysis result with the timing delay in the circuit simulation result when the power consumption in the static analysis result is consistent with the power consumption in the circuit simulation result.
Comparing the timing delay in the static analysis result with the timing delay in the circuit simulation result may refer to comparing the output timing delay of the test circuit in the static analysis result with the output timing delay of the test circuit in the circuit simulation result, that is, comparing the timing delays of CLK and Q1 in the static analysis result with the timing delays of CLK and Q1 in the circuit simulation result.
In an alternative embodiment, comparing the timing delay in the static analysis result with the timing delay in the circuit simulation result may be a value: comparing the timing delay of the timing unit (the timing delay of the CLK and the output signal of the output terminal Q of the timing unit) in the static analysis result with the timing delay of the timing unit (the timing delay of the CLK and the output signal of the output terminal Q of the timing unit) in the circuit simulation result, and comparing the output timing delay of the test circuit in the static analysis result with the output timing delay of the test circuit in the circuit simulation result.
Optionally, the timing delay of the timing unit in the static analysis result may be compared with the timing delay of the timing unit in the circuit simulation result, and if the error between the timing delay of the timing unit in the static analysis result and the timing delay of the timing unit in the circuit simulation result is within the allowable range, the output timing delay of the test circuit in the static analysis result may be compared with the output timing delay of the test circuit in the circuit simulation result; if the error between the timing delay of the timing unit in the static analysis result and the timing delay of the timing unit in the circuit simulation result is not within the allowable range, the verification fails (Fail), so that the verification time can be saved. The method comprises the steps of verifying whether errors of time sequence delay of a time sequence unit (the time sequence delay of a signal output by a CLK and a time sequence unit output end Q) in a static analysis result and errors of the time sequence delay of the time sequence unit (the time sequence delay of the signal output by the CLK and the time sequence unit output end Q) in a circuit simulation result are within an error allowable range, and verifying whether setup time (setup), hold time (hold) and minimum pulse width (min-pulse-width) in a standard unit library are reasonable, so that verification of delay information and power consumption is achieved, and verification of the setup, hold and min-pulse-width is achieved.
In addition, whether the output of the time sequence unit is inverted as expected in the circuit simulation result can be verified. For example, in one embodiment, the entire verification process may be: whether the output of the time sequence unit is inverted according to expectation or not, if the output of the time sequence unit is inverted according to the expectation, whether the error between the time sequence delay of the time sequence unit in the static analysis result and the time sequence delay of the time sequence unit in the circuit simulation result is within an allowable range or not is verified, if the error between the output time sequence delay of the test circuit in the static analysis result and the output time sequence delay of the test circuit in the circuit simulation result is within the allowable range or not is verified, if the error between the power consumption of the static analysis result and the power consumption of the circuit simulation result is within the allowable range or not is verified, if the error between the power consumption of the test circuit and the power consumption of the test circuit is within the allowable range, the verification is passed (pass), if one of the devices does not meet the requirement, the verification is failed (fail), the verification is finished, and the subsequent verification is not needed.
After the verification is passed, data correlation analysis may be performed on standard cells (cells) of the same type to determine the correctness of the timing model and power model information of the cells of the same type, and the flowchart is shown in fig. 4. For example, assume that within the sorted group a there are 100 standard cells, where there are 6 standard cells (which are standard cells in the test circuit) based on previous verification, such as a (10), B (20), C (30), D (50), E (60), F (80) that have already been verified without problems. Then, based on a, B, C, D, E, F, it is estimated that the delay of the 100 units should be between 10-80, and then it is checked whether there is a standard unit with a delay exceeding the interval, and if not, the timing model and power model information corresponding to such standard unit are considered to be correct. Other correlation analyses include linearity analysis, such as calculating a feature value for each standard cell (which may be calculated in terms of the subdivision characteristics of the standard cell, circuit complexity, process impact, etc.), such as A (x1, 10), B (x2, 20), C (x3, 30), D (x4, 50), E (x5, 60), F (x6, 80). Wherein x1, x2, x3, x4, x5 and x6 are the characteristic values of the corresponding standard cells. Assuming that the coordinates of a cell are (x, y), the linearity of the cell with respect to a is y-10/x-x1, and if the value is within the normal threshold range, the quality verification of the cell is also qualified.
The embodiment of the present application further provides a unit library verification apparatus 100, as shown in fig. 5, the unit library verification apparatus 100 includes a building module 110, a generating module 120, an analyzing and simulating module 130, and a verifying module 140.
The building module 110 is configured to build a test circuit according to the standard cells in the standard cell library to be verified, where the test circuit includes all types of standard cells in the standard cell library to be verified, and uses the time sequence unit as an input and the combined logic unit as an output. Optionally, the building module 110 is configured to group all standard cells in the standard cell library to be verified, and group standard cells with the same function into one group; and respectively selecting at least one standard cell from each group of standard cells, and building the test circuit according to the standard cells. Wherein the test circuit comprises only one complete timing path from input to output. Optionally, the building module 110 is further configured to, when building the test circuit, assign values to other input ends of the multi-input standard cell except for the input end connected to the timing path if the multi-input standard cell exists in the test circuit.
And a generating module 120, configured to generate a gate-level circuit netlist and a simulation circuit netlist according to the test circuit.
And the analysis simulation module 130 is configured to perform static analysis on the gate-level circuit netlist and perform circuit simulation on the simulation circuit netlist, where a test stimulus applied when the static analysis is performed on the gate-level circuit netlist is consistent with a test stimulus applied when the circuit simulation is performed on the simulation circuit netlist.
And the verification module 140 is configured to verify the quality of the standard cell library to be verified according to the static analysis result and the circuit simulation result. Optionally, the verification module 140 is configured to compare a timing delay in the static analysis result with a timing delay in the circuit simulation result, and compare a power consumption in the static analysis result with a power consumption in the circuit simulation result; and if the time sequence delay in the static analysis result is consistent with the time sequence delay in the circuit simulation result and the power consumption in the static analysis result is consistent with the power consumption in the circuit simulation result, the standard cell library to be verified passes the quality verification.
Optionally, the verification module 140 is configured to compare the timing delay of the timing unit in the static analysis result with the timing delay of the timing unit in the circuit simulation result, and compare the output timing delay of the test circuit in the static analysis result with the output timing delay of the test circuit in the circuit simulation result. Wherein before comparing the output timing delay of the test circuit in the static analysis result with the output timing delay of the test circuit in the circuit simulation result, it is required to determine that the timing delay of the timing unit in the static analysis result is consistent with the timing delay of the timing unit in the circuit simulation result.
The standard cell library verification apparatus 100 provided in the embodiment of the present application has the same implementation principle and the same technical effect as those of the foregoing method embodiments, and for the sake of brief description, reference may be made to the corresponding contents in the foregoing method embodiments for the parts of the apparatus embodiments that are not mentioned.
As shown in fig. 6, fig. 6 is a block diagram illustrating a structure of an electronic device 200 according to an embodiment of the present disclosure. The electronic device 200 includes: a transceiver 210, a memory 220, a communication bus 230, and a processor 240.
The elements of the transceiver 210, the memory 220, and the processor 240 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, the components may be electrically coupled to each other via one or more communication buses 230 or signal lines. The transceiver 210 is used for transceiving data. The memory 220 is used to store a computer program such as the software functional module shown in fig. 5, that is, the standard cell library verification apparatus 100. The standard cell library verification apparatus 100 includes at least one software function module, which may be stored in the memory 220 in the form of software or firmware (firmware) or fixed in an Operating System (OS) of the electronic device 200. The processor 240 is configured to execute an executable module stored in the memory 220, such as a software function module or a computer program included in the standard cell library verification apparatus 100. For example, the processor 240 is configured to build a test circuit according to the standard cells in the standard cell library to be verified, where the test circuit includes all types of standard cells in the standard cell library to be verified, and uses the time sequence unit as an input and the combined logic unit as an output; generating a gate-level circuit netlist and a simulation circuit netlist according to the test circuit; performing static analysis on the gate-level circuit netlist and performing circuit simulation on the simulation circuit netlist, wherein test excitation applied when the static analysis is performed on the gate-level circuit netlist is consistent with test excitation applied when the circuit simulation is performed on the simulation circuit netlist; and the quality of the standard cell library to be verified is verified according to the static analysis result and the circuit simulation result.
The Memory 220 may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Read-Only Memory (EPROM), an electrically Erasable Read-Only Memory (EEPROM), and the like.
The processor 240 may be an integrated circuit chip having signal processing capabilities. The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor 240 may be any conventional processor or the like.
The electronic device 200 includes, but is not limited to, a computer, a server, and the like.
The embodiment of the present application further provides a non-volatile computer-readable storage medium (hereinafter, referred to as a storage medium), where the storage medium stores a computer program, and the computer program is executed by the computer, such as the electronic device 200, to execute the standard cell library verification method described above.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a notebook computer, a server, or an electronic device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (11)
1. A method for standard cell library verification, comprising:
building a test circuit according to standard cells in a standard cell library to be verified, wherein the test circuit comprises all types of standard cells in the standard cell library to be verified, and takes a time sequence unit as input and a combined logic unit as output;
generating a gate-level circuit netlist and a simulation circuit netlist according to the test circuit;
performing static analysis on the gate-level circuit netlist and performing circuit simulation on the simulation circuit netlist, wherein test excitation applied when the static analysis is performed on the gate-level circuit netlist is consistent with test excitation applied when the circuit simulation is performed on the simulation circuit netlist;
and verifying the quality of the standard cell library to be verified according to the static analysis result and the circuit simulation result.
2. The method of claim 1, wherein building a test circuit from standard cells in a library of standard cells to be verified comprises:
grouping all standard units in the standard unit library to be verified, and grouping the standard units with consistent functions into a group;
and respectively selecting at least one standard cell from each group of standard cells, and building the test circuit according to the standard cells.
3. A method according to claim 1 or 2, wherein the test circuit comprises only one complete timing path from input to output.
4. The method of claim 3, further comprising:
when the test circuit is built, if a multi-input standard unit exists in the test circuit, assigning values to other input ends of the multi-input standard unit except for the input ends connected with the time sequence path.
5. The method of claim 1, wherein the test stimulus is generated by:
and generating the test excitation meeting the test requirement according to the preset minimum pulse width of the clock signal and the setup time and the hold time of the preset test excitation relative to the clock signal.
6. The method of claim 1, wherein verifying the quality of the standard cell library to be verified based on the static analysis results and the circuit simulation results comprises:
comparing the timing delay in the static analysis result with the timing delay in the circuit simulation result, and comparing the power consumption in the static analysis result with the power consumption in the circuit simulation result;
and if the time sequence delay in the static analysis result is consistent with the time sequence delay in the circuit simulation result and the power consumption in the static analysis result is consistent with the power consumption in the circuit simulation result, the standard cell library to be verified passes the quality verification.
7. The method of claim 6, wherein comparing the timing delay in the static analysis results to the timing delay in the circuit simulation results comprises:
comparing the timing delay of the timing unit in the static analysis result with the timing delay of the timing unit in the circuit simulation result, and comparing the output timing delay of the test circuit in the static analysis result with the output timing delay of the test circuit in the circuit simulation result.
8. The method of claim 7, wherein prior to comparing the output timing delay of the test circuit in the static analysis results to the output timing delay of the test circuit in the circuit simulation results, the method further comprises:
determining that the timing delay of the timing unit in the static analysis result is consistent with the timing delay of the timing unit in the circuit simulation result.
9. A standard cell library verification apparatus, comprising:
the device comprises a building module, a test module and a control module, wherein the building module is used for building a test circuit according to standard units in a standard unit library to be verified, the test circuit comprises all types of standard units in the standard unit library to be verified, a time sequence unit is used as input, and a combined logic unit is used as output;
the generating module is used for generating a gate-level circuit netlist and a simulation circuit netlist according to the test circuit;
the analysis simulation module is used for carrying out static analysis on the gate-level circuit netlist and carrying out circuit simulation on the simulation circuit netlist, wherein the test excitation applied when the static analysis is carried out on the gate-level circuit netlist is consistent with the test excitation applied when the circuit simulation is carried out on the simulation circuit netlist;
and the verification module is used for verifying the quality of the standard cell library to be verified according to the static analysis result and the circuit simulation result.
10. An electronic device, comprising:
a memory and a processor, the processor coupled to the memory;
the memory is used for storing programs;
the processor to invoke a program stored in the memory to perform the method of any of claims 1-8.
11. A storage medium having stored thereon a computer program which, when executed by a processor, performs the method according to any one of claims 1-8.
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