CN102436533A - Time sequence verification method of standard cell library model - Google Patents
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Abstract
The invention provides a time sequence verification method of a standard cell library model, which comprises the following steps: the timing information at the coordinate points and/or interpolation points of the standard cell library model is verified by circuit simulation. The invention provides a method for verifying time sequence information of a library model file after the library model file is built. By using the method, inaccurate time sequence information in the library model file can be corrected in the development process of the library, and each coordinate point in the lookup table can be accurately verified.
Description
Technical field
The present invention relates to the IC design field, relate in particular to a kind of timing verification method of standard cell lib model.
Background technology
In the IC of semi-custom (Integrated Circuit, integrated circuit) design, standard cell lib is the tie between actual chips and the design circuit.Design of Digital Circuit, especially large-scale Design of Digital Circuit of nanometer technology stage, standard cell lib has become the necessary condition of design circuit.With reference to figure 1, Fig. 1 show subordinate act be described to the band delayed data post-simulation supporting whole Design of Digital Circuit flow process.
Along with chip-scale is complicated day by day, process dwindles day by day, and the timing closure problem undoubtedly also becomes increasingly complex and can't avoid.And nearly all will use in the flow process of storehouse model file (.lib file) after comprehensive of reflection cell library time sequence information, as shown in Figure 2.Therefore also increasingly high to the requirement of the order of accuarcy of the storehouse model file that is used for EDA (Electronic Design Automation, automatic electronic design) instrument at present.
Nonlinear model is the most widely used delay computation model of present industry member.It adopts the method for difference estimation; For example the x axle is as the value coordinate of the transit time (Transition time) of input signal; The y axle is as the data point coordinate of output load capacitance, and the z axle is used to show delay (Propagation delay) and the output transit time that is input to output.Synthesizer relies on the time (interpolate value) in four coordinate points scopes of estimation to carry out static timing analysis.Drop on the point (extrapolated value) of coordinate plane scope outside for the estimation interpolation, the estimated value error can be bigger, carries out when comprehensive at synthesizer, usually be used as to violate DRC (Design Rule Check) rule and handle, so this value will be avoided.Wherein, the transit time refers to from the time that 10% to 90% of supply voltage is consumed (rising the transit time) with from the time (descending the transit time) that 90% to 10% of supply voltage is consumed, and is as shown in Figure 3.The time-delay that is input to output refers to the time point of input signal when supply voltage 50% to the time point of output signal when the supply voltage 50%, and is as shown in Figure 4.
Usually, the standard cell lib Developmental Engineer by virtue of experience estimates out the highest frequency and the low-limit frequency of technology according to technology characteristics, estimates maximum capacitor load and minimum capacity load according to minimum and maximum fan-out that the unit can drive.These are exactly the coordinate value of characterization modeling tool at input signal transit time and output load capacitance frontier point.The characterization modeling tool inserts 5 coordinate points through logarithm operation again in the frontier point coordinate, thereby forms the sequential look-up table of 7 row, 7 row.The timing verification method of traditional cell library is exactly to verify through flow.For fear of the extra time delay and the big problem of individual unit measuring error of PAD and the introducing of testing chain external unit, present proof scheme is to realize through the circuit form that unit of the same race is in series mostly.Phase inverter testing chain as shown in Figure 5, as to adopt 200 units in series of the same race to form.Its simulation waveform is with reference to figure 6.
Though method of the prior art is the time sequence information of unit in the authentication unit storehouse effectively, the cost of flow is very high, and the flow proving period is long, iterations is many.
Summary of the invention
The present invention provides a kind of timing verification method of standard cell lib model, is used for the time sequence information that the storehouse model file reflects is verified, and the deviation in the model file of storehouse is dynamically revised.
According to an aspect of the present invention, a kind of timing verification method of standard cell lib model is provided, it is characterized in that, comprising:
Through the coordinate points of circuit simulation validation criteria cell library model and/or the time sequence information on the interpolation points.
The present invention proposes a kind of method that after the storehouse model file has been set up, just can verify its time sequence information.Use said method in the performance history of storehouse model, to verify, and inaccurate time sequence information is revised to the time sequence information in the model file of storehouse.In addition, can also accurately verify each coordinate points in the look-up table.Adopt method of the present invention to guarantee coming to the same thing of emulator and static timing analysis tool, thereby make the deviser can comprehensively go out sequential gate level circuit accurately.
Description of drawings
Through reading the detailed description of doing with reference to following accompanying drawing that non-limiting example is done, it is more obvious that other features, objects and advantages of the present invention will become:
Fig. 1 is that standard cell lib supports synoptic diagram to the ASIC design cycle;
Fig. 2 is the support synoptic diagram of temporal model storehouse to the ASIC flow process;
Fig. 3 is the transit time synoptic diagram;
Fig. 4 is the synoptic diagram of the time-delay (gate delay) that is input to output;
The flow proof scheme unit testing chain of Fig. 5 for designing for example with phase inverter;
Fig. 6 is the simulation waveform of testing chain shown in Figure 5;
Fig. 7 is the coordinate points proof scheme;
Fig. 8 is the interpolate value proof scheme;
Fig. 9 is with DC analysis circuit sequential process flow diagram;
Figure 10 is the schematic flow sheet according to a kind of embodiment of the timing verification method of a kind of standard cell lib model provided by the invention.
Same or analogous Reference numeral is represented same or analogous parts in the accompanying drawing.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, will combine accompanying drawing that embodiments of the invention are described in detail below.
Describe embodiments of the invention below in detail, the example of said embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Be exemplary through the embodiment that is described with reference to the drawings below, only be used to explain the present invention, and can not be interpreted as limitation of the present invention.
Disclosing of hereinafter provides many various embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts and the setting of specific examples are described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.
The transit time of gate delay, output transit time and output load and input signal is all relevant.The look-up table that cell delay information in the storehouse model file that standard cell lib is done for the EDA synthesis tool is made according to transit time and two indexs of output load capacitance of input signal just.As shown in the table:
cell_rise(″del_1_7_7″){
index_1(″4，6.66667，9.33333，12，14.6667，17.3333，20″)；
index_2(″0.0001，0.0349711，0.151229，0.404096，0.653979，0.808093，2.82807″)；
values(″0.5644518，0.6948845，1.0310950，1.7338051，2.4269329，2.8489913，8.4911527″，\
″0.6415743，0.7838954，1.1395935，1.8532345，2.5467970，2.9759573，8.5819405″，\
″0.6890143，0.8439078，1.2118898，1.9399873，2.6488973，3.0795939，8.6743634″，\
″0.7254624，0.8892369，1.2679939，2.0082709，2.7279934，3.1681033，8.7659844″，\
″0.7502326，0.9224236，1.3109829，2.0609843，2.7905380，3.2360545，8.8603738″，\
″0.7700739，0.9528796，1.3523257，2.1109570，2.8494915，3.2916372，8.9382004″，\
″0.7807973，0.9682171，1.3811141，2.1439641，2.8909357，3.3459613，9.0225081″)；
The value of index_1 refers to the transit time of input signal, and the value of index_2 refers to output load capacitance, and the value of values refers to time sequence information, is meant the output rising time-delay (cell_rise) of door here.For example: index_1 is 12, and index_2 is 0.151229 o'clock, in values, refers to the 4th row, the value of the 3rd row, promptly 1.2679939.
In the process of standard cell lib characterization modeling, the deviser must confirm the transit time of input signal and the corresponding coordinate point of output load capacitance.For example, generate the sequential look-up table of one 7 row, 7 row, the deviser just must confirm 7 points of input signal transit time and 7 points of output load capacitance.The look-up table of the follow-up generation of whether suitable directly influence of these point selection accurately whether, and then directly influence the deviation on sequential between designed circuit and the actual produced circuit, if deviation will cause the failure of flow above certain limit.So the accuracy of time sequence information is particularly important for the quality of estimating a cover performance of standard cell library in the model file of storehouse.Go back the ripe method of neither one for choosing of the corresponding coordinate point in the model file of storehouse at present, the developer in most storehouse chooses coordinate points with experience.So be necessary the time sequence information that reflects in the model file of storehouse is verified.
The present invention adopts different verification method to its coordinate points with interpolation points for the standard cell lib model that will verify.Result for (data that provide in the standard cell lib model, for example output delay and output transit time) requirement of the time sequence information on the coordinate points and circuit layer grade simulated (for example HSPICE emulation) is basic identical.For interpolation points, use static timing tool (for example analysis tool DC (Design Compiler)) to estimate the time sequence information on it.Usually, the difference that requires estimation result and the grade simulated result of circuit layer is within 1% scope.And should be in 5% for the estimation of considering the situation use static timing tool that line RC postpones and the grade simulated result's of circuit layer error range.
With reference to Figure 10, Figure 10 is the schematic flow sheet of an embodiment of method provided by the invention.Execution in step S101, through circuit simulation, the coordinate points of validation criteria cell library model and/or the time sequence information on the interpolation points.Further, at first build first artificial circuit of the circuit model that comprises the standard cell lib model; The transit time and the output load capacitance of input signal are set according to the coordinate points of standard cell lib model.Their value is consistent with the value of the point that will measure in storehouse model file (.lib file).Be 12 with index_1 still, index_2 0.151229 is example, promptly verifies the time sequence information when the input signal transit time is 12ns and output load capacitance 0.151229pf:
index_1(″4，6.66667，9.33333，12，14.6667，17.3333，20″)；
index_2(″0.0001，0.0349711，0.151229，0.404096，0.653979，0.808093，2.82807″)；
Promptly adopt said first artificial circuit to carry out emulation, obtain first simulation result.
With reference to figure 7, do HSPICE emulation with artificial circuit shown in Figure 7, measure the transit time and the gate delay time of output terminal, and compare with point in the sequential file, judge whether both are within the acceptable error scope.For example whether the error compared with said first simulation result of the time sequence information on the coordinate points of criterion cell library model is in the first threshold scope, is preferably in 1%.If do not satisfy then record, after all coordinate points checkings of this unit by the time finish, the coordinate points that does not satisfy error requirements is reset the line parameter of going forward side by side extract.Repeat said process, till all points meet the demands.
Further,, build second artificial circuit of the circuit model that comprises the standard cell lib model, place impact damper (buffer) at the input end of said second artificial circuit with reference to figure 8.Come out with HDL (Hardware Description Language) language description.As shown in Figure 8, the purpose that the input end in the unit adds an impact damper is in order the environment of a real circuits to be provided to test cell, to make test result more near actual conditions.For the unit of many inputs, if will be wherein a termination impact damper, all the other ports connect high level or ground low level (only otherwise output terminal is exerted an influence) and get final product.The transit time and the output load capacitance of input signal are set according to the interpolation points of standard cell lib model; Adopt said second artificial circuit to carry out emulation, obtain second simulation result.
Further, use the Library Compiler instrument of synospsys to become the .db form to the file conversion of .lib form; And utilize the static timing analysis tool counting circuit of synospsys to postpone, with reference to figure 9.It should be noted that the output load capacitance value will drop in the coordinate points scope.Do HSPICE emulation according to these input/output conditions with the same circuit afterwards.
At last, check the time series analysis file and the HSPICE simulation result of DC output, relatively whether the error of calculation is preferably in 1% in second threshold value.If it is unreasonable that error just thinks that greater than this scope coordinate points is chosen, needing again put perhaps access time increases time point between the big point of error.
No matter it should be noted that it is in first artificial circuit or second artificial circuit, when existing line RC to postpone, said first threshold and said second threshold value are less than 5%.
Can find out, adopt method provided by the invention can guarantee coming to the same thing of emulator and static timing analysis tool, thereby make the deviser can comprehensively go out sequential gate level circuit accurately.
To those skilled in the art, obviously the invention is not restricted to the details of above-mentioned example embodiment, and under the situation that does not deviate from spirit of the present invention or essential characteristic, can realize the present invention with other concrete form.Therefore; No matter from which point; All should regard embodiment as exemplary; And be nonrestrictive, scope of the present invention is limited accompanying claims rather than above-mentioned explanation, therefore is intended to the implication of the equivalents that drops on claim and all changes in the scope are included in the present invention.Should any Reference numeral in the claim be regarded as limit related claim.In addition, obviously other modules or step do not got rid of in " comprising " speech, and odd number is not got rid of plural number.
Claims (10)
1. the timing verification method of a standard cell lib model comprises:
Through the coordinate points of circuit simulation validation criteria cell library model and/or the time sequence information on the interpolation points.
2. method according to claim 1, wherein said circuit simulation comprises:
Build first artificial circuit of the circuit model that comprises the standard cell lib model;
The transit time and the output load capacitance of input signal are set according to the coordinate points of standard cell lib model;
Adopt said first artificial circuit to carry out emulation, obtain first simulation result.
3. method according to claim 2, wherein said checking comprises:
Whether the error that the time sequence information on the coordinate points of criterion cell library model is compared with said first simulation result is in the first threshold scope, as not in said first threshold scope, then resets said coordinate points.
4. method according to claim 1, wherein said circuit simulation comprises:
Build second artificial circuit of the circuit model that comprises the standard cell lib model, place impact damper at the input end of said second artificial circuit;
The transit time and the output load capacitance of input signal are set according to the interpolation points of standard cell lib model;
Adopt said second artificial circuit to carry out emulation, obtain second simulation result.
5. method according to claim 4, wherein said checking comprises:
Carry out static timing analysis to obtain the static timing analysis result;
More said static timing analysis result and said second simulation result, when both errors in second threshold range, think that then the coordinate points in the model file of storehouse is reasonable, otherwise, then reset said coordinate points.
6. method according to claim 3 is characterized in that, said first threshold is less than 1%.
7. method according to claim 5 is characterized in that, said second threshold value is less than 1%.
8. according to claim 6 or 7 described methods, it is characterized in that when existing line RC to postpone, said first threshold and said second threshold value are less than 5%.
9. method according to claim 1 is characterized in that, adopts HSPICE that first artificial circuit and/or second artificial circuit are carried out emulation.
10. method according to claim 5 is characterized in that, adopts DC to carry out static timing analysis.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103870617A (en) * | 2012-12-12 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Auto-place-route method for low-frequency chip |
| CN104636509A (en) * | 2013-11-08 | 2015-05-20 | 飞思卡尔半导体公司 | Method for verifying timing problem in gate-level simulation |
| CN106503278A (en) * | 2015-09-06 | 2017-03-15 | 创意电子股份有限公司 | Time sequence analysis method and system for digital circuit design |
| CN108090288A (en) * | 2017-12-21 | 2018-05-29 | 北京华大九天软件有限公司 | A kind of method that time sequence parameter is obtained by machine learning |
| CN110632501A (en) * | 2019-09-27 | 2019-12-31 | 上海兆芯集成电路有限公司 | Method and apparatus for predicting operating characteristics of integrated circuit |
| CN110991130A (en) * | 2019-12-04 | 2020-04-10 | 北京华大九天软件有限公司 | Method for checking standard unit time sequence library by circuit simulation |
| CN112232006A (en) * | 2020-10-26 | 2021-01-15 | 海光信息技术股份有限公司 | Standard cell library verification method and device, electronic equipment and storage medium |
| CN115964973A (en) * | 2022-12-30 | 2023-04-14 | 南京邮电大学 | Unit delay calculation method of composite current source model |
| CN116108802A (en) * | 2023-04-12 | 2023-05-12 | 苏州珂晶达电子有限公司 | Standard cell library determination method, device and system |
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Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103870617B (en) * | 2012-12-12 | 2017-04-05 | 上海华虹宏力半导体制造有限公司 | Low frequency chip automatic placement and routing method |
| CN103870617A (en) * | 2012-12-12 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Auto-place-route method for low-frequency chip |
| CN104636509A (en) * | 2013-11-08 | 2015-05-20 | 飞思卡尔半导体公司 | Method for verifying timing problem in gate-level simulation |
| CN104636509B (en) * | 2013-11-08 | 2019-05-28 | 恩智浦美国有限公司 | The system and method for sequence problem is verified in Gate Level Simulation |
| CN106503278A (en) * | 2015-09-06 | 2017-03-15 | 创意电子股份有限公司 | Time sequence analysis method and system for digital circuit design |
| CN106503278B (en) * | 2015-09-06 | 2019-08-23 | 创意电子股份有限公司 | Time sequence analysis method and system for digital circuit design |
| CN108090288B (en) * | 2017-12-21 | 2020-05-12 | 北京华大九天软件有限公司 | Method for acquiring time sequence parameters through machine learning |
| CN108090288A (en) * | 2017-12-21 | 2018-05-29 | 北京华大九天软件有限公司 | A kind of method that time sequence parameter is obtained by machine learning |
| CN110632501A (en) * | 2019-09-27 | 2019-12-31 | 上海兆芯集成电路有限公司 | Method and apparatus for predicting operating characteristics of integrated circuit |
| CN110991130A (en) * | 2019-12-04 | 2020-04-10 | 北京华大九天软件有限公司 | Method for checking standard unit time sequence library by circuit simulation |
| CN110991130B (en) * | 2019-12-04 | 2023-03-24 | 北京华大九天科技股份有限公司 | Method for checking standard unit time sequence library by circuit simulation |
| CN112232006A (en) * | 2020-10-26 | 2021-01-15 | 海光信息技术股份有限公司 | Standard cell library verification method and device, electronic equipment and storage medium |
| CN112232006B (en) * | 2020-10-26 | 2021-07-02 | 海光信息技术股份有限公司 | Standard cell library verification method and device, electronic equipment and storage medium |
| CN115964973A (en) * | 2022-12-30 | 2023-04-14 | 南京邮电大学 | Unit delay calculation method of composite current source model |
| CN115964973B (en) * | 2022-12-30 | 2023-07-04 | 南京邮电大学 | Unit delay calculation method of composite current source model |
| CN116108802A (en) * | 2023-04-12 | 2023-05-12 | 苏州珂晶达电子有限公司 | Standard cell library determination method, device and system |
| CN116108802B (en) * | 2023-04-12 | 2023-08-04 | 苏州珂晶达电子有限公司 | Standard cell library determination method, device and system |
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Application publication date: 20120502 |