JP5831067B2 - Power consumption analysis method, power consumption analysis apparatus, and power consumption analysis program - Google Patents

Description

The present invention, power analysis method for calculating the power consumption of the circuit, and power consumption analysis device and power analysis program.

  In recent years, demands for lower power consumption of LSIs and other circuits have become more stringent due to demands for reducing power density associated with higher system integration, and enactment of power consumption regulations for electrical equipment such as the Energy Star and the Energy Saving Act. The importance of low power consumption technology in LSI design is increasing.

  As a power consumption analysis method at the time of LSI design, a method of calculating power consumption for each circuit element based on operation information of each part of the circuit obtained by logic simulation is generally performed. As a logic simulation for acquiring such operation information, the actual signal propagation delay is reflected in the cell / macro, and if gate-level event-driven simulation is used, high-accuracy operation information that takes glitches into account can be obtained. can get. However, the gate-level event-driven simulation reflecting such actual delay takes a very long simulation time. In recent years, LSIs have become large-scale, and there is an increasing number of cases where such event-driven simulation cannot be executed in a realistic time at the chip level.

  As a method of speeding up logic simulation, there is a method of speeding up gate level simulation by cycle-based logic simulation by a hardware emulator. In addition, there is a technique for reducing simulation time by reducing the amount of description by describing hardware operations at a higher level of abstraction, such as RTL and higher behavior levels. For example, a cycle-based logic simulation is performed using data described in a clock level description, which is an RTL and a behavioral description having an intermediate level of abstraction in the middle of the behavioral level description. There is a technique for calculating power consumption based on a cell / macro power calculation formula (see, for example, Patent Document 1 below).

  On the other hand, the operation information used for power consumption analysis becomes enormous due to the large scale of LSI, and it becomes difficult to acquire and hold information on all internal nodes of LSI due to increase in file size and increase in information acquisition time. It has become to. As a coping method for this problem, for example, only operation information in a limited place such as an input / output signal of a target design, an output of a sequential cell, and an input / output signal of a function macro is acquired. In addition to this limited location, the operation information of all nodes is generated by probabilistically generating and propagating the operation information from the input side to the output side of each element starting from the location where the operation information is given. A method of generating is known. This method is incorporated as a function of a commercially available CAD tool. Examples include Apache PowerArtist, Cadence PowerMeter, and Synopsys PrimeTime PX.

JP 2005-293163 A

  Consider a case where operation information for power consumption analysis of an LSI is acquired from a cycle-based logic simulation. In the cycle-based logic simulation, the value of each element is evaluated only once every clock cycle, so information that changes during the clock cycle is lost, and the operation of each internal signal obtained as a result is one clock cycle. Can only be obtained once. As described above, the operation information can be applied to all the nets of the circuit by applying the operation information obtained by simulation, input / output signals to be analyzed, output of sequential cells, output signals of function macros, etc. For example, there is a method of generating / applying the operation information to the remaining nodes and generating and applying the operation information to the remaining signals by stochastic propagation processing of the operation information.

  With regard to the operation information of each cell in a circuit that does not include a macro, a certain degree of accuracy improvement can be expected for the operation rate by improving the probability propagation method of the operation information. However, since the macro internal logic is complicated, it is difficult to propagate the operation information of the input signal to the output signal with probability, so there is an error between the cycle-based operation information and the actual operation. In a circuit including a large macro, it is difficult to improve the accuracy of the operation rate only by improving the probability propagation method.

  As for the power consumption of the macro itself, it is possible to improve the accuracy of the macro power consumption analysis by creating a power model that takes into account the uncertainty of the operation information in advance, but the latter stage connected to the output pin of the macro For logic circuits, even if the probability propagation method is used, the operation information of the macro output that is the propagation source is inaccurate, so the accuracy cannot be increased, resulting in a decrease in the analysis accuracy of the power consumption analysis. .

  As a macro having a large error between the cycle-based operation information and the actual operation, for example, an output signal of a macro having a structure in which glitches are likely to occur, such as XOR logic or a many-to-one selector structure, or a dynamic circuit Function macro logic output signals using

Power analysis method disclosed, power consumption analyzer and power analysis program is to solve the problems described above, consumption of the whole circuit by correcting the operation information of the circuit of the subsequent macro output circuit units The purpose is to improve the accuracy of power analysis.

In order to solve the above-described problems and achieve the object, the disclosed technology is based on a cycle-based logic of a circuit to be analyzed in a power consumption analysis method using a power consumption analysis device. The circuit operation information obtained by the simulation execution and the error corresponding to the difference between the simulated operation by the cycle-based logic simulation and the actual operation of the output signal of the circuit to be analyzed included in the circuit to be analyzed based on the operation correction information for the operation information of the macro, the correcting the error contained in the operation information of the macro in a circuit to be analyzed, determination processing unit that the power consumption analysis device has the circuit of the analyzed when determining the operation information of each signal of the inner, after the macro operation information corrected by belief propagation on a circuit of a subsequent stage of the macro To confirm the operation information of the circuit, the power consumption calculation section included in the power consumption analysis device includes determining the power consumption of the circuit in the subsequent stage of the macro by using the said operation information obtained by belief propagation.

Power analysis method disclosed, according to the power consumption analysis device and power consumption analysis program, by correcting the operation information of the circuit of the subsequent macro output circuit units, it is possible to improve the accuracy of power analysis of the entire circuit There is an effect.

FIG. 1 is a diagram illustrating an outline of processing of power consumption analysis according to the first embodiment. FIG. 2 is a block diagram of the power consumption analysis apparatus according to the first embodiment. FIG. 3 is a flowchart illustrating a procedure of power consumption analysis processing. FIG. 4 is a diagram for explaining a glitch signal waveform. FIG. 5 is a diagram for explaining the output signal waveform of the dynamic circuit. FIG. 6 is a chart showing correction information in consideration of glitches. FIG. 7 is a chart showing correction information of the dynamic circuit. FIG. 8 is a flowchart illustrating an example of a detailed procedure of the operation information correction process. FIG. 9 is a circuit diagram illustrating an example of a circuit that performs power consumption analysis, operation information, and operation correction information. FIG. 10 is a diagram illustrating operation information correction processing and operation information propagation for a macro instance. FIG. 11 is a circuit diagram for explaining an example of calculating power by power analysis according to the first embodiment (part 1). FIG. 12 is a circuit diagram for explaining an example of calculating power by power analysis according to the first embodiment (part 2). FIG. 13 is a circuit diagram illustrating an example of power calculation when the method of power analysis according to the first embodiment is not applied. FIG. 14 is a diagram illustrating operation correction information and a macro circuit configuration according to the second embodiment. FIG. 15 is a diagram for explaining operation information correction processing according to the second embodiment. FIG. 16 is a diagram illustrating a circuit including a macro according to the second embodiment. FIG. 17 is a circuit diagram for explaining operation information correction processing. FIG. 18 is a circuit diagram for explaining the result of determining the operation information. FIG. 19 is a circuit diagram illustrating an example of calculating power when the method of power analysis according to the second embodiment is not applied.

(Embodiment 1)
Hereinafter, preferred embodiments of the disclosed technology will be described in detail with reference to the accompanying drawings. The disclosed technology calculates power consumption in units of circuits (gates) based on operation information obtained by cycle-based logic simulation, thereby improving analysis accuracy of power consumption in units of circuits. In particular, even if it is difficult to improve the accuracy of motion information by propagating motion information, it is possible to improve the power analysis accuracy of the entire circuit by improving the accuracy of the motion information of the previous circuit from this macro output. To improve.

(Outline of processing for power consumption analysis)
FIG. 1 is a diagram illustrating an outline of processing of power consumption analysis according to the first embodiment. In the disclosed technology, correction information for each output signal of the output pin 101a to be corrected by the macro 101 is separately prepared for a macro (target macro) 101 in which the operation of the actual output signal is greatly different from the cycle-based operation information. (1) Based on the correction information, the operation information of the output signal of the output pin 101a of the target macro 101 is corrected among the operation information of the entire circuit 100. As a result, (2) the corrected operation information is input to the output pin 101a. Next, (3) in the phase for determining the operation information of each signal in the circuit 100 before power calculation, the corrected operation information is propagated to the subsequent gate (circuit) 102. In (4) power calculation processing, power consumption accuracy of the circuit 100 is improved by executing power consumption analysis based on final operation information after propagation by probability propagation.

  The operation information of the internal node used in the power consumption analysis of the embodiment includes the toggle rate of the signal (expected value of the number of times the signal is inverted within one cycle of the reference clock) and the duty ratio of the signal (in the entire analysis period, The ratio of the period when the signal value was 1) is assumed. As the operation information used for the power consumption analysis, it is also possible to use information such as a timing window indicating a range in which the signal may change in the cycle as auxiliary information for probability propagation of the operation information. In the following description, the toggle rate and the duty ratio are used.

(Configuration of power consumption analyzer)
FIG. 2 is a block diagram of the power consumption analysis apparatus according to the first embodiment. The power consumption analysis apparatus 200 shown in FIG. 2 can be configured using a general-purpose computer or server. The power consumption analysis apparatus 200 includes a CPU 201, a ROM 202, a RAM 203, an I / F 204, a bus 205, and a storage 206 such as an HDD.

  The CPU 201 executes a power consumption analysis program stored in the ROM 202 and functions as a control unit that performs power consumption analysis processing by using the RAM 203 as a work area. Cycle-based circuit operation information, analysis target netlist, macro 101 operation correction information, and the like are input to the I / F 204 from the keyboard 210 or an external hardware emulator 211 and stored in the storage 206. The CPU 201 corrects the operation information of the macro 101 and calculates power consumption based on the input information. The calculated power consumption can be output externally via a display or the I / F 204.

(Overview of power consumption analysis)
FIG. 3 is a flowchart illustrating a procedure of power consumption analysis processing. An overview of the entire power consumption analysis process performed by the power consumption analysis apparatus 200 will be described. In the following description, each macro actually embedded in the netlist is referred to as a macro “instance” and used separately from the word “macro” 101 as the type of component.

1. Preparation: Step S301
Operation correction information of the macro 101 having an output signal with a large error from the cycle-based operation is prepared in advance (step S301). Information to be prepared includes cycle-based circuit operation information 310 obtained by simulation processing of the hardware emulator 211, a net list 311 of a circuit to be analyzed for power, and operation correction information 312 of the macro 101. The cycle-based circuit operation information 310 may be either all node in the circuit 100 or limited node operation information including the output signal of the macro instance. The motion correction information 312 includes a macro name, a target output signal name, correction information, and the like.

2. Operation information correction process: Step S302
Next, a process for correcting the circuit operation information 310 based on the inputs of the cycle-based circuit operation information 310, the netlist 311 and the operation correction information 312 is performed. In this correction processing, among all macro instances included in the netlist 311, all of the macro instances included in the operation correction information 312 are all described in the operation correction information 312 among the output pins 101 a of the macro instance. For the output pin 101a, the operation information of the net to which the output pin 101a is connected is corrected based on the operation correction information 312. As a result, corrected cycle-based circuit operation information 310a is obtained. Specific contents of the operation information and the correction method in this correction process will be described later.

3. In-circuit operation information determination process: Step S303
In the process of determining the operation information of all the nets in the circuit 100 for power consumption calculation, the circuit operation information 310a of all the nets that have been subjected to the operation correction in the operation information correction processing step S302 is obtained with respect to the circuit of the subsequent stage of the net. Then, the circuit operation information 310a is propagated until the order cell 103, the macro 101, and the circuit output 104 are reached. In the in-circuit operation information determination process, other data (for example, wiring capacity information, cell / macro power library, etc.) 313 necessary for power analysis can be received and processed. If there is a net for which other operation information has not been determined, the circuit operation information 310a is determined by probability propagation processing.

4). Power consumption calculation process: Step S304
Power consumption calculation is performed using the corrected circuit operation information 310a propagated in the in-circuit operation information determination processing step S303, and information on the power consumption analysis result 314 is obtained. Each of the above information (data) is externally output after being stored in the storage 206, RAM 203, etc. of the power consumption analysis apparatus 200.

(About motion information correction processing)
Next, the correction process of the circuit operation information 310 will be described. In the correction of the circuit operation information 310, a. Correction in consideration of glitch, b. Make corrections considering the dynamic circuit.

  These glitches and dynamic circuits will be described. As macros with large error between cycle-based operation information and actual operation, for example, use macro output signals or dynamic circuits with structures that are prone to glitches such as XOR logic and many-to-one selector structures. Function macro logic output signal.

  FIG. 4 is a diagram for explaining a glitch signal waveform. FIG. 4A shows a signal waveform acquired by a cycle-based simulation, and FIG. 4B shows a state in which a glitch is placed on this signal waveform. It can be seen that when the glitch as shown in FIG. 4B is applied, the operation rate becomes larger than the signal waveform acquired by the cycle-based simulation. For the macro 101 having a circuit structure (XOR logic, many-to-one selector, etc.) on which glitches can be easily steadily placed, the error in power consumption calculation becomes very large. Specifically, since the signal waveform on which the glitch is changed changes within the clock cycle CK, the power consumption calculation considering the toggle change (inversion rate) of the signal waveform cannot be performed.

  FIG. 5 is a diagram for explaining the output signal waveform of the dynamic circuit. In the dynamic circuit, the evaluation operation is executed every clock cycle CK. If the logic output value of the dynamic circuit continues to be output in reverse to the output value at the time of precharging the circuit, the actual circuit operation is that the signal is forcibly precharged at each precharge phase. It will be driven to (the value opposite to the logical output value).

  As a result, as shown in FIG. 5B, a signal waveform having a pulse on every clock cycle is obtained. In the case of cycle-based simulation, since only the value of the evaluation phase is acquired as the operation information, the signal waveform shown in FIG. 5A is recorded as the operation information, which is far from the actual operation of the circuit. The operation rate will be low. In order to conceal the precharge pulse, a latch is often provided at the output portion of the macro 101. In order to avoid the influence of the delay increase due to this latch, the signal waveform for operating the dynamic circuit is output from the macro 101 as it is. Not a few.

a. About Correction Considering Glitch As a correction considering the effect of the glitch, a coefficient value corresponding to the ease of riding the glitch on the macro output signal is used as correction information. Then, the circuit operation information 310 is corrected by multiplying the toggle rate of the output signal by a factor.

FIG. 6 is a chart showing correction information in consideration of glitches. In the example of the motion correction information 312 related to the glitch illustrated in FIG. 6, for example, the coefficient value 2.0 is set for the output signal 2 of the macro 1. This “coefficient” can be obtained and prepared in advance by examining the relationship between the toggle rate of the logic output obtained by simulation of the macro 101 alone and the toggle rate obtained from the actual waveform in advance. it can. This factor is multiplied by the toggle rate. That is, the correction formula is as follows.
New toggle rate = toggle rate x coefficient value New duty ratio = duty ratio

b. About Correction Considering Dynamic Circuit In the correction considering dynamic circuit, the control clock pin name and the precharge polarity are used as correction information for each output signal. The control clock pin is a clock input pin that is timing the precharge / evaluation phase of the dynamic circuit that produces the output signal, and the precharge polarity is set to 0 or 1 when the output signal becomes 0 in the precharge phase. This is information indicating whether or not

  FIG. 7 is a chart showing correction information of the dynamic circuit. In the example of the operation correction information 312 related to the dynamic circuit shown in FIG. 7, for example, the precharge polarity is set to 1 and the control clock name for precharging is set to CK2 for the output signal 1 of the macro 2. These correction information “control clock pin name” and “precharge polarity” are information that can be easily obtained from the logic specifications of the macro 101 or the developer of the macro 101 and prepared in advance. The dynamic circuit output does not change when the logic output value is the same as the precharge polarity, and outputs a pulse signal having the same cycle as the control clock when the logic output value is opposite to the precharge polarity. Therefore, when attention is paid to the fact that the duty ratio is the ratio of the period in which the signal is 1, the correction equations are as follows when the precharge polarity is 1 and 0, respectively. In the following, the toggle rate is calculated based on the probability that the output signal of the macro 101 included in the circuit operation information has a value opposite to the precharge polarity and the operation rate of the control clock.

When precharge polarity = 0 New toggle rate = Control clock toggle rate x Duty ratio New duty ratio = Duty ratio-Duty ratio / 2 = Duty ratio / 2

When precharge polarity = 1 New toggle rate = Control clock toggle rate x (1-duty ratio)
New duty ratio = Duty ratio + (1-Duty ratio) / 2

  Further, when there is a control input signal that suppresses the operation of the dynamic circuit, these “control input signal” and “control polarity” can be added to the correction information as information based on the logic specifications of the macro 101 and the like. . In the example of FIG. 7, for example, the control input signal of macro 2 is EN1, and the control polarity is 1. Accordingly, the new toggle rate may be further corrected as follows by regarding the duty ratio of the control input signal as the rate at which the dynamic circuit operates. In this case, correction is performed based on the probability that the control input signal is a suppression value.

When the control input signal is 1 and the circuit is operating New toggle rate '= New toggle rate x (duty ratio of control input signal)
When the control input signal is 0 and the circuit is operating New toggle rate '= New toggle rate x (1- Duty ratio of control input signal)

The new duty ratio when there is a control input signal is as follows because the change in duty due to the precharge pulse is corrected by the duty ratio of the control input signal.
Circuit operation with precharge polarity = 0 and control input signal = 1 New duty ratio = duty ratio-duty ratio / 2 x (control input signal duty ratio)
In case of circuit operation with precharge polarity = 0 and control input signal = 0, new duty ratio = duty ratio-duty ratio / 2 x (1-control input signal duty ratio)
In case of circuit operation with precharge polarity = 1, control input signal = 1 new duty ratio = duty ratio + (1-duty ratio) / 2 × (control input signal duty ratio)
In case of circuit operation with precharge polarity = 1, control input signal = 0, new duty ratio = duty ratio + (1-duty ratio) / 2 × (1-control input signal duty ratio)

  In the case where a glitch is further added in the middle of the macro 101 until the dynamic circuit output reaches the macro output, the above a. A glitch; b. Provide correction information for both dynamic circuits, b. After correction of the dynamic circuit, a. A glitch correction may be performed.

(About the flow of motion information correction processing)
FIG. 8 is a flowchart illustrating an example of a detailed procedure of the operation information correction process. Details of the operation information correction processing shown in step S302 of FIG. 3 performed by the power consumption analysis apparatus 200 will be described. First, one of all macro instances included in the netlist 311 that has not been subjected to the operation information correction process (step S302) is selected (step S801). For example, assume that instance A (macro type B) is selected.

  Next, macro B information is acquired from the motion correction information 312 (step S802). Then, it is checked whether or not macro B information exists in the motion correction information 312 (step S803). If it exists (step S803: Yes), the process proceeds to step S804, and if it does not exist (step S803: No), step The process returns to S801.

  In step S804, one unselected output pin 101a is selected from the output pins 101a of the instance A (step S804). For example, assume that the output pin S is selected. Then, it is checked whether the information of the selected output pin S exists in the operation correction information 312 (step S805). If it exists (step S805: Yes), the process proceeds to step S806, and if it does not exist (step S805: No). ), The process returns to step S804.

  Next, in step S806, the operation information (toggle rate, duty ratio) of the signal connected to the output pin S of the instance A is acquired from the circuit operation information 310, and the new toggle rate and duty ratio are obtained based on the correction information of the output pin S. And the circuit operation information 310 is updated. At this time, it is recorded that correction processing has been performed (step S806).

  Next, it is checked whether all the output pins 101a of the instance A have been selected (step S807). If all the output pins 101a have been selected (step S807: Yes), the process proceeds to step S808, and has not yet been selected. If there is the output pin 101a (step S807: No), the process returns to step S804.

  Finally, in step S808, it is checked whether all macro instances in the netlist 311 have been selected (step S808). If there is an unselected macro instance (step S808: No), the process returns to step S801, and all macros are selected. If the instance has been selected (step S808: Yes), the operation information correction process described above is terminated.

(Specific example of power consumption analysis processing)
Next, the power consumption analysis process will be described using a specific circuit example. FIG. 9 is a circuit diagram illustrating an example of a circuit that performs power consumption analysis, operation information, and operation correction information. An example in which the toggle rate T, the duty ratio D, and the operation correction information 312 described in each net are processed as input will be described.

  FIG. 10 is a diagram illustrating operation information correction processing and operation information propagation for a macro instance. In FIG. 10, the upper, middle, and lower stages are described for each process for one macro instance A (macro X). First, as shown in the upper part of FIG. In the motion information correction process (step S302), since the macro instance A is an instance of the macro X (101), information on the macro X is retrieved from the motion correction information 312. Thereby, the correction information of the output pins S1 and S2 is obtained as the correction information of the macro X. From the obtained correction information, the output pin S1 is connected to the a. Glitch correction, output pin S2 is b. The dynamic circuit is corrected.

  In the operation information correction process (step S302), as shown in the middle part of FIG. 10, the circuit operation information 310 of the net connected to each output pin S1, S2 is corrected according to the correction formula. For example, the toggle rate T (toggle_rate) of the output pin S1 is corrected to 0.3 × 2.5 = 0.75, and the duty ratio D (duty) of the output pin S2 is 0.4+ (1−0.4 ) /2=0.7.

  Thereafter, the above-mentioned 3. In the in-circuit operation information determination process (step S303), as shown in the lower part of FIG. 10, the circuit operation information 310a of the two nets subjected to correction is propagated to the subsequent circuit. In this circuit example, since the subsequent circuit is a simple buffer (Buf) 1001, it is only necessary to propagate the circuit operation information 310a of the input signal to the output as it is, and no probability calculation is required.

  Next, power consumption analysis based on the above-described corrected circuit operation information 310a will be described. Considering the power consumption of each buffer subsequent to the macro 101, the switching power of the buffer (Buf) 1001 (power consumed by the operation of the circuit) is “(toggle rate) × (buffer consumption per signal change). Energy) ”. For this reason, the switching power of the buffer 1001a connected to the output pin S1 of the instance A (macro X) 101 is 2.5 times (0.75 / 0) that of the case where the power analysis method of the present embodiment is not applied. .3), the dynamic power of the buffer 1001b connected to the output pin S2 is 6 times (1.2 / 0.2).

  This means that the power consumption analyzed based on the cycle-based operating rate, which has not been applied to the power analysis method of the present embodiment, is underestimated. A. As for the correction considering the glitch, some correction errors occur due to the difference between the coefficient calculation operation and the actual operation, but b. Since the correction considering the dynamic circuit is based on the signal waveform by the dynamic circuit operation, the correction is almost error-free.

  In addition, for leakage power (power that continues to be consumed even if the circuit does not operate due to leakage current, etc.), this leakage power generally varies depending on the value of the input signal. When performing power analysis, calculation is performed using the duty ratio of the input signal. From this, b. In the correction considering the dynamic circuit, the duty ratio is also corrected by the above-described method, so that the analysis accuracy of the leakage power can also be improved.

(Example of calculating power consumption)
Next, an example of calculating the switching power according to the present embodiment will be described. As an example, the switching power of the circuit 100 shown in FIG. 9 excluding the macro will be described. The circuit operation information 310 is given to the input signal of each circuit and the output signal of the macro 101, and other network operation information is obtained by probability propagation. In order to simplify the description, in the illustrated circuit example, in addition to the macro 101, only two-input AND, OR, XOR, and buffer (Buf) circuits are used. In order to simplify the description, the switching power of each gate other than the macro 101 is calculated as follows.
Switching power of each gate = (toggle ratio of output signal of target gate) × 100 [uW]

  A simple model is used as a method of probability propagation of motion information. In the case of AND or OR, when the input signal on one side changes, the signal change propagates to the output when the input on the other side is AND, and when it is OR, the value of the other input signal in the case of XOR. Regardless, it will propagate to the output. When the two input signals and output signals (toggle ratio T, duty ratio D) are (T1, D1) (T2, D2) (TO, DO), (T1, D1) (T2, D2) (TO, DO) is determined as follows.

AND: TO = T1 × D2 + T2 × D1, DO = D1 × D2
OR: TO = T1 * (1-D2) + T2 * (1-D1), DO = 1- (1-D1) * (1-D2)
XOR: TO = T1 + T2, DO = D1 * (1-D2) + (1-D1) * D2
The buffer uses the input (T, D) as it is for output.

  FIG. 11 and FIG. 12 are circuit diagrams illustrating an example of calculating power by power analysis according to the first embodiment. As shown in FIG. In the operation information correction process (step S302), since the correction information for the output pins S1 and S2 of the macro X is given as the operation correction information 312, the output signals of the output pins S1 and S2 of the macro instances A and B respectively. The operation information is corrected. A. Glitch, b. New (corrected) operation information of each signal obtained based on a calculation formula considering the dynamic circuit is shown in the subsequent stage of the arrow (→). For the output pin S1, the toggle rate is 2.5 times based on the coefficient, and for the output pin S2, the toggle rate 2.0 of the clock CK multiplied by (1-duty ratio) is the new toggle rate.

  2. As described above. In the in-circuit operation information determination process (step S303), the corrected circuit operation information 310a is probabilistically propagated to the subsequent circuit. The operation information of each net after propagation is shown in FIG. The dynamic power of the circuits (a) to (h) other than the macro for which the power consumption is calculated based on the result is (a) 0.3 × 100 + (b) 0.9 × 100 + (c) 0.6 × 100+ (d) 0.41 × 100 + (e) 1.53 × 100 + (f) 1.53 × 100 + (g) 1.6 × 100 + (h) 1.6 × 100 = 847 uW.

  For comparison, the power in the case where the power analysis method of the present embodiment is not applied will be described. FIG. 13 is a circuit diagram illustrating an example of power calculation when the method of power analysis according to the first embodiment is not applied. FIG. 13 shows a state in which motion information is propagated with probability from the input side to the output side and the motion information of all nets is determined. Circuit operation information generated by probability propagation is underlined. Here, it is assumed that the macro X (101) cannot propagate the probability of the motion information from the input to the output, and propagates the motion information set as the output value as it is to the subsequent stage. The dynamic power of the portion other than the macro X (101) at this time is (a) 0.3 × 100 + (b) 0.9 × 100 + (c) 0.6 × 100 + (d) 0.29 × 100 + (e ) 0.52 × 100 + (f) 0.52 × 100 + (g) 1.3 × 100 + (h) 1.3 × 100 = 573 uW. Thus, when the method of power analysis according to the first embodiment is not applied, it can be seen that the power consumption is calculated to be about 32% too low.

  According to the first embodiment described above, the accuracy of power analysis can be improved without increasing the number of steps of logic simulation for acquiring operation information. Only the processing for correcting (converting) the operation information is included, and since no large processing is added to the subsequent power analysis processing itself, the overhead for the entire analysis time is small and analysis can be performed in a short time.

(Embodiment 2)
Next, in the second embodiment, in the correction of circuit operation information in consideration of the dynamic circuit operation, an example of operation correction when a plurality of clocks and control input signals are added in addition to the configuration of the first embodiment will be described. . FIG. 14 is a diagram illustrating operation correction information and a macro circuit configuration according to the second embodiment. The polarity of the control input signal in the operation correction information 312 is 1 when the control input is 1 and the circuit is operating, and 0 when the circuit is operating. In the following description, this operation correction information 312 will be used.

  The macro A (101) includes dynamic circuits 1401 and 1402, and the dynamic circuit 1401 operates with the control signal EN1 and the control clock CK1 and outputs a signal from the output pin S1. The dynamic circuit 1402 operates with the control signal INH2 and the control clock CK2, and outputs signals from the output pins S2 and S3.

  FIG. 15 is a diagram for explaining operation information correction processing according to the second embodiment. The upper part of FIG. 15 is the operation information before correction, and the lower part is the operation information after correction. As shown in the upper part of FIG. 15, the toggle rate T and the duty ratio D (T, D) will be described for each signal of the operation information before correction of the macro A (101). The control clock CK1 is (2, 0.5), the control clock CK2 is (0.5, 0.5), the control signal EN1 is (0.3, 0.7), and the control signal INH2 is (0.2, 0). .2), the output pin S1 is (0.3, 0.3), the output pin S2 is (0.1, 0.4), and the output pin S3 is (0.1, 0.4).

  As shown in the lower part of FIG. 15, when the operation correction for the output pin S <b> 1 is performed by the correction using the operation correction information 312, the toggle rate toggle_rate = (1-duty) × (control CK toggle_rate) × control signal duty = ( 1−0.3) × 2.0 × 0.7 = 0.98. Also, the duty ratio duty = duty + [(1-duty) / 2} × control signal duty = 0.3 + {(1-0.3) / 2} × 0.7 = 0.545.

  When the operation correction for the output pin S2 is performed, the toggle rate toggle_rate = (1-duty) × (control CK toggle_rate) × (1-control signal duty) = (1-0.4) × 0.5 × (1-0 .2) = 0.24. Further, duty ratio duty = duty + {(1-duty) / 2} × (1-control signal duty) = 0.4 + {(1-0.4) / 2} × (1-0.2) = 0. 64.

  When the operation correction for the output pin S3 is performed, the toggle rate toggle_rate = duty × (control CK toggle_rate) × (1−control signal duty) = 0.4 × 0.5 × (1-0.2) = 0.16. Become. Further, the duty ratio becomes duty = duty− (duty / 2) × (1−control signal duty) = 0.4− (0.4 / 2) × (1−0.2) = 0.24.

  FIG. 16 is a diagram illustrating a circuit including a macro according to the second embodiment. The circuit of FIG. 16 is an example of a circuit including the macro A (101) shown in FIGS. 14 and 15, and the cycle base shown in FIG. 16 is used for the input of each circuit and the input / output of the macro A (101). Is assumed to be annotated. (Toggle rate T, Duty ratio D)

  FIG. 17 is a circuit diagram for explaining operation information correction processing. In FIG. 17, the result of correcting the operation information of the output pins S1, S2, and S3 of the macro instance 1 (macro A) using the operation correction information 312 is shown in the subsequent stage of the arrow (→). The operation information of the control input signal is finally the above described 3. In the in-circuit operation information determination process (step S303), the operation information propagated from the input-side circuit is overwritten.

  However, 2. In the operation information correction process (step S302), since it is handled as control information of the internal clocks CK1 and CK2 of the macro A (101), 3. It is necessary to use cycle-based operation information, which is initial operation information, instead of operation information including glitches after the in-circuit operation information determination process (step S303). Since the inputs of the control clocks CK1 and CK2 are signals in which waveforms in cycle units are defined, 3. The operation information is not rewritten by the in-circuit operation information determination process (step S303).

  FIG. 18 is a circuit diagram for explaining the result of determining the operation information. 3. above. The result of determining the operation information by the in-circuit operation information determination process (step S303) is shown. The dynamic power of the circuits (a) to (i) other than the macro A (101) when the power analysis method according to the second embodiment is applied is ((a) 0.3+ (b) 0.5+ (c) 0. 2+ (d) 0.9205+ (e) 0.9205+ (f) 0.16+ (g) 0.16+ (h) 0.36+ (i) 0.36) × 100 uW = 388.1 uW.

  For comparison, the power in the case where the power analysis method of the present embodiment is not applied will be described. FIG. 19 is a circuit diagram illustrating an example of calculating power when the method of power analysis according to the second embodiment is not applied. When the dynamic power of the circuits (a) to (i) is determined as “(toggle ratio T of the output signal of the target gate) × 100 [uW]” and the dynamic power of the circuits other than the macro is obtained, the dynamic power is ((a) 0.3+ (b) 0.5+ (c) 0.2+ (d) 0.45+ (e) 0.45+ (f) 0.08+ (g) 0.08+ (h) 0.3+ (i) 0. 3) × 100 uW = 266 uW Thus, it can be seen that when the method of power analysis according to the second embodiment is not applied, the power consumption is calculated to be about 31% too low.

  According to the second embodiment described above, even when a plurality of control signals and a clock input include a macro, the accuracy of power analysis is improved without increasing the number of logic simulation steps for acquiring operation information. Can do. Only the processing for correcting (converting) the operation information is included, and since no large processing is added to the subsequent power analysis processing itself, the overhead for the entire analysis time is small and analysis can be performed in a short time.

  The correction of the operation information according to each of the above embodiments corrects the operation information in units of gates based on the operation information obtained by the cycle-based logic simulation, so that the operation information is probabilistically propagated to improve the accuracy of the operation information. Even if a difficult macro is included, the accuracy of the operation information of the previous circuit can be improved from this macro output, and the power analysis process can be performed at high speed. In addition, correction is performed in consideration of glitches that change during the clock cycle and the output of the dynamic circuit. As a result, it becomes possible to deal with macros having large errors between cycle-based operation information and actual operations, and power consumption analysis of circuits including these macros can be performed with high accuracy in a short time.

101 Macro 101a (S1, S2, S3) Output pin 200 Power consumption analyzer 201 CPU
202 ROM
203 RAM
204 I / F
211 Hardware Emulator 310 Circuit Operation Information 310a Corrected Circuit Operation Information 311 Netlist 312 Operation Correction Information 314 Power Consumption Analysis Result CK1, CK2 Control Clock

Claims (9)

In the power consumption analysis method using the power consumption analysis device,
The correction processing unit included in the power consumption analysis apparatus includes circuit operation information obtained by executing cycle-based logic simulation of a circuit to be analyzed , simulation operation by the cycle-based logic simulation included in the circuit to be analyzed , and the based on the operation correction information for the operation information of the macro including the error corresponding to the difference between the actual operation of the output signal of a circuit to be analyzed, the error included in the operation information of the macro in the circuit of the analyzed Correct,
Determination processing unit that the power consumption analyzer possessed, when determining the operation information of each signal in the circuit of the analyzing object, the macro operation information corrected by belief propagation on a circuit of a subsequent stage of the macro Confirm the operation information of the subsequent circuit,
A power consumption analysis method, wherein a power consumption calculation unit included in the power consumption analysis apparatus obtains power consumption of a circuit subsequent to the macro using the operation information propagated by the probability. The power consumption analysis method according to claim 1, wherein the circuit operation information includes a toggle rate of the analysis target circuit and a duty ratio of the analysis target circuit during an analysis period.   The power consumption analysis method according to claim 2, wherein the operation correction information includes a coefficient for an operation rate of the macro output signal, and the toggle rate is corrected using the coefficient.   The operation correction information includes a precharge control clock name of an output signal of the macro that operates in a dynamic circuit and polarity information in a precharge phase, and the probability that the output signal of the macro is a value opposite to the precharge polarity. The power consumption analysis method according to claim 2, wherein the toggle rate is calculated based on an operation rate of a control clock.   The operation correction information further includes a control input signal name for controlling operation / inhibition of the macro output signal and a control polarity of the control input signal, and the control input signal is based on a probability that the control input signal is an inhibition value. The power consumption analysis method according to claim 4, wherein the toggle rate is corrected.   The coefficient included in the motion correction information uses a coefficient obtained in advance based on a relationship between a toggle rate of a logical output obtained by simulation of the macro alone and a toggle rate obtained from an actual waveform. The power consumption analysis method according to claim 3.   5. The power consumption analysis method according to claim 4, wherein the precharge control clock name and the polarity information included in the operation correction information are prepared in advance based on specifications of the macro. Circuit operation information obtained by executing cycle-based logic simulation of the circuit to be analyzed, simulation operation by the cycle-based logic simulation and actual operation of the output signal of the circuit to be analyzed included in the circuit to be analyzed a correction processing unit for correcting the error contained in the operation information of the macro in the circuit of the analyzed based on the operation correction information for the operation information of the macro including the error corresponding to the difference between,
When determining the operation information of each signal in the circuit of the analyzing target, determination processing of the operation information corrected by belief propagation to the subsequent circuit of the macro determines the operation information of a circuit of a subsequent stage of the macro And
Power analysis device characterized by Ru with a power consumption calculation section for obtaining the power consumption of the circuit in the subsequent stage of the macro by using the operation information said to belief propagation. In the power consumption analysis program of the power consumption analyzer,
  In the correction processing unit included in the power consumption analysis device, circuit operation information obtained by executing cycle-based logic simulation of a circuit to be analyzed, simulation operation by the cycle-based logic simulation included in the circuit to be analyzed, and The error included in the macro operation information in the analysis target circuit is calculated based on the operation correction information for the macro operation information including an error corresponding to a difference from the actual operation of the output signal of the analysis target circuit. Let me correct it,
  When the operation information of each signal in the analysis target circuit is determined by the determination processing unit included in the power consumption analysis apparatus, the corrected operation information is probabilistically propagated to the subsequent circuit of the macro, and the macro Confirm the operation information of the subsequent circuit,
  Causing a power consumption calculation unit included in the power consumption analysis apparatus to calculate power consumption of a circuit subsequent to the macro using the operation information propagated by the probability.
  Power consumption analysis program characterized by

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