CN114626324A - Post-simulation verification method and device for FPGA circuit, electronic equipment and storage medium - Google Patents
Post-simulation verification method and device for FPGA circuit, electronic equipment and storage medium Download PDFInfo
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Abstract
The invention provides a post-simulation verification method and device for an FPGA circuit, electronic equipment and a computer-readable storage medium. The invention provides a post-circuit simulation verification method of an FPGA (field programmable gate array), which comprises the following steps of: acquiring circuit device time delay information and line time delay information; acquiring a time sequence information file according to the time delay information of the circuit device and the line time delay information, and performing time sequence denormalization on the circuit according to the time sequence information file; and carrying out simulation verification according to the time delay of the circuit and the port signal after the time sequence is inversely scaled to obtain a circuit simulation verification result. The post-simulation verification method for the FPGA circuit improves the efficiency of the post-simulation verification of the FPGA circuit.
Description
Technical Field
The invention relates to the technical field of FPGA circuit simulation, in particular to a post-simulation verification method and device for an FPGA circuit, electronic equipment and a computer-readable storage medium.
Background
Currently, an FPGA (Field-Programmable gate array) chip has important applications in the fields of communication, security, medical treatment, finance, industry and the like, along with the gradual improvement of the process level, the scale of the FPGA chip is continuously enlarged, the performance of the FPGA chip is continuously improved, the applicable scene and the applicable environment range of the FPGA chip are continuously expanded, and the market demand on a large-scale FPGA circuit is continuously improved. In order to ensure the completeness of the functions and performances of the large-scale FPGA circuit, how to efficiently perform function simulation and timing verification on the large-scale FPGA circuit becomes an important subject of current FPGA chip design and development.
The expansion of the circuit scale of the FPGA means that the number of each module in the chip, the scale of the circuit netlist, and the complexity of the circuit are also multiplied. For post simulation of a parasitic parameter netlist extracted from a conventional layout circuit, due to the fact that the running speed of simulation tools (VCS and UVM) is limited, the netlist is large in scale, and simulation time is generally long. In the design process of the FPGA chip, the larger the scale of the established time sequence model is, the higher the complete requirement on the time sequence constraint is, and the heavier the efficiency of the post-simulation verification is. The conventional post-simulation process only simply and directly introduces the time sequence information after the wiring layout, and the processing mode is relatively complicated and does not process the conditions of port signals and the like, so that the efficiency of the post-simulation verification mode is low.
Disclosure of Invention
The invention aims to provide a post-simulation verification method and device for an FPGA circuit, electronic equipment and a computer readable storage medium, so as to solve the technical problem of low efficiency of post-simulation verification of the FPGA circuit in the prior art.
The technical scheme of the invention is as follows, and provides a post-simulation verification method of an FPGA circuit, which comprises the following steps:
acquiring circuit device time delay information and line time delay information;
acquiring a time sequence information file according to the time delay information of the circuit device and the line time delay information, and performing time sequence denormalization on the circuit according to the time sequence information file;
and carrying out simulation verification according to the time delay of the circuit and the port signal after the time sequence is inversely scaled to obtain a circuit simulation verification result.
Optionally, the obtaining of the circuit device delay information and the line delay information specifically includes: and acquiring time delay information and line time delay information of circuit devices under different processes and temperatures.
Optionally, performing time sequence denormalization on the circuit according to the time sequence information file specifically includes:
and establishing a mapping relation between the time sequence information file and the circuit level description in the circuit netlist, and performing time sequence denormalization on the circuit according to the mapping relation.
Optionally, the step of establishing a mapping relationship between the timing information file and a circuit level description in a circuit netlist, and performing timing denormalization on a circuit according to the mapping relationship specifically includes:
generating a script file according to the circuit device time delay information and the line time delay information, establishing a mapping relation between the time sequence information file and circuit level description in the circuit netlist through the script file, and performing time sequence denormalization on the circuit according to the mapping relation.
Optionally, the step of determining the time delay of the port signal specifically includes:
respectively determining a signal time delay parameter of an input port and a time delay parameter of an output port of the circuit according to an input interface and an output interface of the circuit;
acquiring a signal delay parameter value of an input port and a delay parameter value of an output port according to the different processes, temperatures and modes;
and determining the time delay of the port signal according to the input port signal time delay parameter, the output port time delay parameter, the input port signal time delay parameter value and the output port time delay parameter value.
Optionally, the post-FPGA circuit simulation verification method further includes comparing the circuit simulation verification result with the real circuit simulation result in a time delay manner, determining whether all time delay errors are within a corresponding preset error range, and if so, determining that the circuit simulation verification is successful.
Optionally, the method for performing post-simulation verification on the FPGA circuit further includes determining that the circuit simulation verification is unsuccessful if the delay error is not within the corresponding preset error range.
The invention also provides a post-circuit simulation verification device of the FPGA, which comprises a time delay information acquisition module, a circuit anti-standard module and a simulation verification module;
the time delay information acquisition module is used for acquiring time delay information and line time delay information of the circuit device;
the circuit denotation module is used for acquiring a time sequence information file according to the circuit device time delay information and the line time delay information and performing time sequence denotation on the circuit according to the time sequence information file;
and the simulation verification module is used for performing simulation verification according to the time delay of the circuit and the port signal after the time sequence is inversely calibrated to obtain a circuit simulation verification result.
Another technical solution of the present invention is as follows, an electronic device is provided, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the method for post-FPGA circuit simulation verification according to any one of the above technical solutions is implemented.
Another technical solution of the present invention is to provide a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method for verifying the post-simulation of the FPGA circuit according to any one of the above technical solutions is implemented.
The invention has the beneficial effects that: acquiring time delay information and line time delay information of a circuit device; acquiring a time sequence information file according to the time delay information of the circuit device and the line time delay information, and performing time sequence denormalization on the circuit according to the time sequence information file; performing simulation verification according to the time delay of the circuit and port signals after the time sequence is inversely scaled to obtain a circuit simulation verification result; by the aid of the method, the efficiency of post-simulation verification of the FPGA circuit is improved.
Drawings
FIG. 1 is a schematic flow chart of a post-simulation verification method for an FPGA circuit according to a first embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a post-FPGA circuit simulation verification apparatus according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of an electronic device according to a third embodiment of the invention;
fig. 4 is a schematic structural diagram of a storage medium according to a fourth embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Fig. 1 is a schematic flow chart of a post-simulation verification method for an FPGA circuit according to a first embodiment of the present invention. It should be noted that the method for post-simulation verification of FPGA circuits of the present invention is not limited to the flow sequence shown in FIG. 1 if the results are substantially the same. As shown in fig. 1, the post-simulation verification method for the FPGA circuit mainly includes the following steps:
s101, obtaining circuit device time delay information and line time delay information;
s102, acquiring a time sequence information file according to the time delay information of the circuit device and the line time delay information, and performing time sequence denormalization on the circuit according to the time sequence information file;
s103, performing simulation verification according to the time delay of the circuit and the port signal after the time sequence is inversely calibrated to obtain a circuit simulation verification result.
The simulation verification of the FPGA circuit comprises a function simulation stage and a post-simulation stage, wherein the function simulation belongs to pre-simulation, and the simulation verification of the stage only focuses on the completeness of the design of a function point and does not consider the corresponding time sequence problem; and (3) performing simulation verification in a post-simulation stage, paying attention to the influence of time sequence on the circuit, and performing time sequence simulation on the circuit and each circuit module in the stage to analyze the time sequence relation, check whether the circuit performance reaches the standard, check whether competition risk exists or not and detect whether time sequence violation condition exists or not.
In a specific embodiment, the timing information file is an SDF (Standard delay file) timing information file, which includes circuit device delay and line delay information extracted at different processes and temperatures after layout and wiring. The SDF time sequence information files can be divided into different SDF time sequence information file types according to different application modes.
In specific implementation, after a complete circuit netlist is obtained, related SDF timing information files under all processes, temperatures and modes (working modes) need to be obtained at the same time, and then the SDF timing information files are classified, wherein the general format of the DELAY information in the SDF timing information files is (CELL (BUF _ 1)) (INSTANCE I1) (DELAY [ ABSOLUTE (patohax (0.0194::0.0221) (0.0199::0.0227)))), in the DELAY information format, CELL represents a DELAY information start flag of an SDF circuit module, CELL "BUF _1" represents the name of the circuit module, INSTANCE I1 represents a number corresponding to the circuit module, and iopatx (0.0194::0.0221) (0.0199::0.0227) represents specific information of a — X of a port of the circuit module. The general format of the delay information in the SDF timing information file covers the circuit module name BUF _1, the instantiation name I1, and the delay range information of the rising edge and the falling edge from the a port to the X port.
In an optional implementation manner, the obtaining of the circuit device delay information and the line delay information specifically includes: and acquiring time delay information and line time delay information of circuit devices under different processes and temperatures.
The process is a chip manufacturing process of the FPGA circuit, and includes a finfet process, an euv process, an lpp process, and the like, where the temperature is an ambient temperature of the FPGA circuit during operation, and the temperature range is-40 to 125 ℃. In order to simulate and verify circuits under different processes and temperatures, time delay information and line time delay information of circuit devices under different processes and temperatures need to be determined and acquired. Taking post-simulation verification of a certain module in a circuit as an example, the post-simulation verification totally involves 4 SDF timing information files, and the 4 SDF timing information files respectively correspond to different processes, temperatures and MODEs, namely, the process is CWT (one of various processes), the temperature is 40 ℃, the MODE is MODE1 (MODE one), the process is CB (another process different from CWT), the temperature is 125 ℃, the MODE is MODE1, the process is CWT, the temperature is 40 ℃, the MODE is MODE2 (MODE two), the process is CB, the temperature is 125 ℃ and the MODE is MODE 2.
In an optional embodiment, performing timing denormalization on a circuit according to the timing information file specifically includes:
and establishing a mapping relation between the time sequence information file and the circuit level description in the circuit netlist, and performing time sequence denormalization on the circuit according to the mapping relation.
In an optional embodiment, the creating a mapping relationship between the timing information file and a circuit level description in a circuit netlist, and performing timing denormalization on a circuit according to the mapping relationship specifically includes:
generating a script file according to the circuit device time delay information and the line time delay information, establishing a mapping relation between the time sequence information file and circuit level description in the circuit netlist through the script file, and performing time sequence denormalization on the circuit according to the mapping relation.
In one embodiment, the circuit is denormalized with the SDF timing information file in the general format of
Wherein, 'ifdef CWT40 indicates a specific process and temperature value, where the process is CWT and the temperature is 40 ℃,' ifdef MODE1 indicates a specific MODE value, $ SDF _ annotate ("./../. I1/SDF/part0_ ct 40_1.SDF", u _ wrap.u.u.1. part, "/. sdf.log", "MAXIMUM",) indicates that a mapping relationship between a circuit net table and an SDF timing information file is established by a function SDF _ annotate to perform timing inversion, and $ fdisk "- - - - - - - - - - - -CWT40- - - - - - - -e- -) indicates that printing information is successfully output after inversion. In the general format for performing reverse marking on the circuit by the SDF time sequence information file, ". SDF" is an SDF time sequence information file path selected and introduced, dut.I1.part0 is a circuit level description, "sdf.log" is a reverse marking log name, whether the reverse marking of the SDF time sequence information file is completed can be checked in the sdf.log, and "MAXIMUM" indicates that the MAXIMUM time delay value is selected.
In an optional embodiment, the determining the time delay of the port signal specifically includes:
respectively determining a signal time delay parameter of an input port and a time delay parameter of an output port of the circuit according to an input interface and an output interface of the circuit;
acquiring a signal delay parameter value of an input port and a delay parameter value of an output port according to the different processes, temperatures and modes;
and determining the time delay of the port signal according to the input port signal time delay parameter, the output port time delay parameter, the input port signal time delay parameter value and the output port time delay parameter value.
In a specific embodiment, the time delays of the input port signal and the output signal under different processes, temperatures and modes are respectively determined by defining and setting different input and output time delay values, and the time delays of the input port signal and the output signal under different processes, temperatures and modes and the time delay information and the line time delay information of circuit devices under different processes and temperatures in a time sequence information file jointly form a complete post-simulation verification time sequence, so that the accuracy of post-simulation verification can be ensured. The mode is a working mode of the FPGA circuit in the using process, and the FPGA circuit has functions in different working modes.
It should be noted that, after performing timing denormalization on a circuit according to delay information of circuit devices and lines, the delay of a port signal needs to be determined to ensure the correctness of timing verification. Determining the time delay of the port signal comprises defining time delay parameters of the input port signal and the output port signal in the input port and the output port of the circuit, and endowing corresponding time delay parameter values in a top-level file according to the process and the mode selected by the time sequence information file. The general format for defining the delay parameters for the input and output port signals is,
interface ilogic_agent_interface#(INPUT_DELAY＝0，OUTPUT_DELAYO＝0，OUTPUT_DELAY1＝0，OUTPUT_DELAY2＝θ，OUTPUT_DELAY3＝0)(input bit clk)；
parameter setup_time＝INPUT_DELAY,hold_time_0＝OUTPUT_DELAY0,hold_time_1＝OUTPUT_DELAY 1，hold_time_2＝OUTPUT_DELAY2,hold_time_3＝0UTPUT_DELAY3；
logic clk__stgθ；
logic di；
clocking cb_stg0_pos_2@(posedge clk_stq0)；
default input#setup_time output#hold_time_1；
output di
endclocking:cb_stgθ_pos_2
wherein, the logic _ agent _ interface represents an interface name, (INPUT _ DELAY ═ 0, OUTPUT _ DELAY1 ═ 0, OUTPUT _ DELAY Y2 ═ θ, OUTPUT _ DELAY3 ═ 0) (INPUT bit clk) represents the definition of the DELAY parameter; parameter setup _ time ═ INPUT _ DELAY, hold _ time _0 ═ OUTPUT _ DELAY0, hold _ time _1 ═ OUTPUT _ DELAY1, hold _ time _2 ═ OUTPUT _ DELAY2, hold _ time _3 ═ 0UTPUT _ DELAY3 represents the assignment operation of the DELAY parameter; logic clk __ stg theta represents port signal definition, logic di represents port parameter definition, default input # setup _ time output # hold _ time _1 represents input and output delay value introduced by selective setting, and output di represents output port name; the input specific port di DELAY of the circuit is controlled by a hold _ time _1, which defines the source as OUTPUT _ DELAY 1.
The general format for assigning the delay parameter is
’ifdefPOST_SIM
parameter INPUT_DELAY＝0,OUTPUT_DELAY＝480，OUTPUT_DELAY0＝460，OUTPUT_DELAY2＝70,OUTPUT_D ELAY3＝120；
parameter OUTPUT_DELAY1＝(CP_MODE＝＝"MODE1")？434
:(CP_MODE＝＝"MODE2")？1233
Wherein,' ifdefPOST _ SIM indicates whether there is a determination parameter for introducing a call DELAY, parameter INPUT _ DELAY ═ 0, OUTPUT _ DELAY ═ 480, OUTPUT _ DELAY0 ═ 460, OUTPUT _ DELAY2 ═ 70, OUTPUT _ D _ DELAY3 ═ 120 indicates a DELAY value for defining a port, and parameter OUTPUT _ DELAY1 ═ CP _ MODE ═ 1? 434 (CP _ MODE ═ MODE2 ")? 1233, which indicates that different DELAY values are selected according to the mode, OUTPUT _ DELAY1 may be selected to be 434ns or 1233ns according to the mode of the SDF timing information file.
In an optional embodiment, the post-simulation verification method for the FPGA circuit further includes comparing the circuit simulation verification result with the real circuit simulation result in a time delay manner, determining whether all time delay errors are within a corresponding preset error range, and if so, determining that the circuit simulation verification is successful.
And the real circuit simulation result is obtained by a reference model, and the reference model is a functional comparison model built according to a module design plan. Because the simulation verification results after the circuit are different due to different SDF time sequence information files, the time delay comparison of the simulation verification results of the circuit and the simulation results of the real circuit cannot adopt a real-time zero-delay comparison mode consistent with the function verification, and different time delays are added to the circuit simulation verification results corresponding to different types of the SDF time sequence information files in the comparison process.
In a specific embodiment, a verification platform may be set up to compare the circuit simulation verification result with the real circuit simulation result in a time delay manner, so as to improve the efficiency of simulation verification. The verification platform mainly comprises an excitation file, a circuit design netlist, a reference model, a comparison score board, an interface file and a project level file. The excitation file is an input signal applied according to circuit function control, the circuit design netlist is a netlist to be verified extracted according to a circuit, the reference model is a functional comparison model built according to a module design plan, the comparison score board is a control part for comparing a circuit simulation verification result with a reference model output result, the interface file is a summary file of circuit port signals, and the top file is highest-level instantiation information (including reference of the reference model and the circuit netlist file and control information of simulation duration) of the whole verification platform.
The general format for comparing the time delay of the circuit simulation verification result with the real circuit simulation result is,
in an optional embodiment, the method for post-simulation verification of the FPGA circuit further includes determining that the circuit simulation verification is unsuccessful if the delay error is not within the corresponding preset error range.
Where, the developer begin indicates the start of the alignment, @ (closege mo _ intf. chk _ ishiftout0) indicates the rise-in-clock trigger, mr _ time _ ishiftout0 ═ time indicates the current simulation time assignment, @ (newge mo _ intf. chk __ ishiftout0) indicates the fall-in-clock trigger, if (($ time-mr _ time __ ishiftout0) > mo _ scb _ scg.mui _ delta _ time)' uvm _ error ("$ sformatf (" iol _ ishiftout0 check failed ")) indicates whether the alignment error is determined to be within the error delay parameter (preset error) mui _ delta _ time range, and if so, the error information is printed.
The method for post-simulation verification of the FPGA circuit provided by the embodiment of the invention obtains the time delay information and the line time delay information of a circuit device; acquiring a time sequence information file according to the time delay information of the circuit device and the line time delay information, and performing time sequence denormalization on the circuit according to the time sequence information file; performing simulation verification according to the time delay of the circuit and port signals after the time sequence is inversely scaled to obtain a circuit simulation verification result; by the aid of the method, the efficiency of post-simulation verification of the FPGA circuit is improved.
In post-simulation circuit verification, the verification only needs to concern about the influence of time sequence on a circuit model, and the method for post-simulation verification of the FPGA circuit provided by the embodiment of the invention acquires various time sequence information files after the layout and wiring are finished at the back end, performs post-simulation verification of time sequence anti-standard through the various time sequence information files, and does not need to perform post-simulation with a parasitic parameter netlist. The embodiment of the invention not only relates to gate-level time sequence information but also relates to time delay of port signals during simulation verification so as to ensure the accuracy of post simulation verification.
Fig. 2 is a schematic structural diagram of an FPGA circuit post-simulation verification apparatus according to a second embodiment of the present invention, and as shown in fig. 2, the FPGA circuit post-simulation verification apparatus 20 includes a delay information obtaining module 21, a circuit denotation module 22, and a simulation verification module 23; the delay information obtaining module 21 is configured to obtain delay information of a circuit device and line delay information; the circuit denotation module 22 is configured to obtain a timing information file according to the circuit device delay information and the line delay information, and perform timing denotation on a circuit according to the timing information file; and the simulation verification module 23 is configured to perform simulation verification according to the time delay of the circuit and the port signal after the time sequence is inversely scaled, so as to obtain a circuit simulation verification result.
Further, the delay information obtaining module 21 is further configured to obtain delay information and line delay information of circuit devices in different processes and temperatures.
Further, the circuit denormalization module 22 is further configured to establish a mapping relationship between the timing information file and a circuit level description in the circuit netlist, and perform a timing denormalization on the circuit according to the mapping relationship.
Further, the circuit denormalization module 22 is further configured to generate a script file according to the circuit device delay information and the line delay information, establish a mapping relationship between the timing information file and a circuit level description in the circuit netlist through the script file, and perform timing denormalization on the circuit according to the mapping relationship.
Further, the circuit denormalization module 22 is further configured to determine a signal delay parameter of an input port and a delay parameter of an output port of the circuit according to the input and output interfaces of the circuit, respectively; acquiring a signal delay parameter value of an input port and a delay parameter value of an output port according to the different processes, temperatures and modes; and determining the time delay of the port signal according to the input port signal time delay parameter, the output port time delay parameter, the input port signal time delay parameter value and the output port time delay parameter value.
Further, the simulation verification module 23 is further configured to perform a time delay comparison between the circuit simulation verification result and the real circuit simulation result, determine whether all the time delay errors are within the corresponding preset error range, and if so, determine that the circuit simulation verification is successful.
Further, the simulation verification module 23 is further configured to determine that the circuit simulation verification is unsuccessful when the delay error is not within the corresponding preset error range.
Fig. 3 is a schematic structural diagram of an electronic device according to a third embodiment of the present invention. As shown in fig. 3, the electronic device 30 includes a processor 31 and a memory 32 coupled to the processor 31.
The memory 32 stores program instructions for implementing the post-FPGA circuit simulation verification method of any of the above embodiments.
The processor 31 is operative to execute program instructions stored in the memory 32 for performing code testing.
The processor 31 may also be referred to as a CPU (Central Processing Unit). The processor 31 may be an integrated circuit chip having signal processing capabilities. The processor 31 may also be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a storage medium according to a fourth embodiment of the invention. The storage medium of the embodiments of the present invention, which stores program instructions 41 capable of implementing all the methods described above, may be either non-volatile or volatile. The program instructions 41 may be stored in the storage medium in the form of a software product, and include several instructions to enable a computer device (which may be a personal computer, a server, or a network device) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a mobile hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, or terminal devices, such as a computer, a server, a mobile phone, and a tablet.
In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of modules is merely a division of logical functions, and an actual implementation may have another division, for example, a plurality of modules or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules, and may be in an electrical, mechanical or other form.
In addition, functional modules in the embodiments of the present invention may be integrated into one processing unit, or each module may exist alone physically, or two or more modules are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit. The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A post-simulation verification method for an FPGA circuit is characterized by comprising the following steps:
acquiring time delay information and line time delay information of a circuit device;
acquiring a time sequence information file according to the time delay information of the circuit device and the line time delay information, and performing time sequence denormalization on the circuit according to the time sequence information file;
and carrying out simulation verification according to the time delays of the circuit and the port signals after the time sequence is inversely scaled to obtain a circuit simulation verification result.
2. The method for post-circuit simulation verification of an FPGA of claim 1, wherein the obtaining of circuit device delay information and line delay information specifically comprises: and acquiring time delay information and line time delay information of circuit devices under different processes and temperatures.
3. The post-circuit simulation verification method of the FPGA circuit according to claim 1, wherein performing timing denormalization on the circuit according to the timing information file specifically comprises:
and establishing a mapping relation between the time sequence information file and the circuit level description in the circuit netlist, and performing time sequence denormalization on the circuit according to the mapping relation.
4. The method for post-simulation verification of the FPGA circuit according to claim 3, wherein a mapping relationship between the timing information file and a circuit level description in a circuit netlist is established, and a timing denormalization is performed on a circuit according to the mapping relationship, specifically comprising:
generating a script file according to the circuit device time delay information and the line time delay information, establishing a mapping relation between the time sequence information file and circuit level description in the circuit netlist through the script file, and performing time sequence denormalization on the circuit according to the mapping relation.
5. The post-circuit simulation verification method of the FPGA circuit according to claim 2, wherein the step of determining the delay of the port signal specifically includes:
respectively determining a signal time delay parameter of an input port and a time delay parameter of an output port of the circuit according to an input interface and an output interface of the circuit;
acquiring a signal delay parameter value of an input port and a delay parameter value of an output port according to the different processes, temperatures and modes;
and determining the time delay of the port signal according to the input port signal time delay parameter, the output port time delay parameter, the input port signal time delay parameter value and the output port time delay parameter value.
6. The method of claim 1, further comprising comparing the circuit simulation verification result with a real circuit simulation result in a time delay manner, determining whether all time delay errors are within a corresponding preset error range, and if so, determining that the circuit simulation verification is successful.
7. The method of claim 6, further comprising determining that the circuit emulation verification is unsuccessful if the delay error is not within the corresponding predetermined error range.
8. A post-circuit simulation verification device of an FPGA (field programmable gate array) circuit is characterized by comprising a time delay information acquisition module, a circuit anti-standard module and a simulation verification module;
the time delay information acquisition module is used for acquiring time delay information and line time delay information of the circuit device;
the circuit denotation module is used for acquiring a time sequence information file according to the circuit device time delay information and the line time delay information and performing time sequence denotation on the circuit according to the time sequence information file;
and the simulation verification module is used for performing simulation verification according to the time delay of the circuit and the port signal after the time sequence is inversely calibrated to obtain a circuit simulation verification result.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the FPGA circuit post-simulation verification method of any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, in which a computer program is stored, which, when being executed by a processor, implements the FPGA circuit post-simulation verification method according to any one of claims 1 to 7.
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