CN109902318B - Method and device for generating standard time delay format file - Google Patents
Method and device for generating standard time delay format file Download PDFInfo
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- CN109902318B CN109902318B CN201711284392.9A CN201711284392A CN109902318B CN 109902318 B CN109902318 B CN 109902318B CN 201711284392 A CN201711284392 A CN 201711284392A CN 109902318 B CN109902318 B CN 109902318B
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Abstract
The invention provides a method and a device for generating a standard time delay format file. The method comprises the following steps: performing time sequence analysis on the chip according to a standard cell library and an input file used by the chip to determine standard cells of time sequence violation; replacing the standard unit of the time sequence violation by using a virtual unit of the standard unit of the time sequence violation, wherein the virtual unit meets the Setup/Hold time sequence requirement to obtain a tcl format file for repairing the time sequence; generating a standard delay format file meeting the Setup/Hold time sequence requirement according to the tcl format file; and modifying the name of the virtual unit of the standard unit for replacing the time sequence violation in the standard time delay format file into the name of the replaced standard unit of the time sequence violation to obtain a final standard time delay format file. The invention can generate the SDF file which simultaneously meets the Setup/Hold time sequence requirement at the early stage of back-end time sequence convergence under the condition of not changing a netlist.
Description
Technical Field
The invention relates to the technical field of chip design, in particular to a method and a device for generating a standard time delay format file.
Background
For ASIC chip design, a Standard Delay Format (SDF) file needs to be output during the process of timing convergence at the back end of the chip, and a constraint error or a design error that may exist in the chip can be found through post-simulation with the SDF file.
The SDF file is generated by a rear-end timing sequence convergence tool through reading a Netlist Netlist and a SPEF parasitic parameter, the SDF file describes delay of each unit cell/net in design and a Setup/Hold check value of a timing sequence unit, and after the post simulation tool reads the SDF file for countermarking, a waveform and a working environment close to reality can be output, so that whether the chip can work correctly or not is finally verified.
However, in the design process, the time point of providing the SDF file satisfying the Setup/Hold timing requirement is generally later, and after the post-simulation with the SDF finds a problem, the modification time is correspondingly very short, so that how to generate the SDF file satisfying the Setup/Hold timing requirement at the same time in the early stage of the back-end timing convergence is necessary.
The method commonly used in the industry at present is set _ indexed _ delay, the Hold timing requirement can only be met by adding extra indexed _ delay, the Setup timing requirement cannot be met, and for the Setup timing, post-simulation is required to avoid timing violation and complete simulation through frequency reduction. The problem of down-conversion is also obvious, and some real problems can not be verified due to down-conversion, so that the existing method has great limitation.
Disclosure of Invention
The method and the device for generating the standard delay format file can generate the SDF file which simultaneously meets the Setup/Hold time sequence requirement at the early stage of back-end time sequence convergence under the condition of not changing a netlist.
In a first aspect, the present invention provides a method for generating a standard delay format file, including:
performing time sequence analysis on a chip according to a standard cell library and an input file used by the chip to determine a standard cell of a time sequence violation;
replacing the standard unit of the time sequence violation by a virtual unit meeting the Setup/Hold time sequence requirement of the standard unit of the time sequence violation by using a size _ cell method to obtain a tcl format file for repairing the time sequence;
generating a standard delay format file meeting the Setup/Hold time sequence requirement according to the tcl format file;
and modifying the name of the virtual unit of the standard unit used for replacing the time sequence violation in the standard delay format file into the name of the replaced standard unit of the time sequence violation to obtain a final standard delay format file.
Optionally, the virtual unit meeting the Setup/Hold timing requirement of the standard unit with the timing violation includes a virtual unit with a delay of delayX50, delayX10, delayX5, delayx0.1, or delayx0.01, where delay is the delay of the standard unit with the timing violation.
Optionally, the input file includes: netlist files, standard parasitic interchange format files, and delay constraint files.
In a second aspect, the present invention provides an apparatus for generating a standard delay format file, including:
the determining module is used for carrying out time sequence analysis on the chip according to a standard cell library and an input file used by the chip and determining a standard cell of a time sequence violation;
a replacing module, configured to replace the standard unit with the virtual unit meeting the Setup/Hold time sequence requirement of the standard unit with the time sequence violation by using a size _ cell method, so as to obtain a tcl format file for repairing the time sequence;
the generating module is used for generating a standard delay format file meeting the Setup/Hold time sequence requirement according to the tcl format file;
and the modification module is used for modifying the name of the virtual unit of the standard unit used for replacing the time sequence violation in the standard time delay format file into the name of the replaced standard unit of the time sequence violation to obtain a final standard time delay format file.
Optionally, the virtual unit meeting the Setup/Hold timing requirement of the standard unit of the timing violation used by the replacement module includes a virtual unit with a delay of delayX50, delayX10, delayX5, delayX0.1, or delayX0.01, where delay is the delay of the standard unit of the timing violation.
Optionally, the input file includes: netlist files, standard parasitic interchange format files, and delay constraint files.
The method and the device for generating the standard delay format file provided by the invention construct virtual units with different delays of all standard units, repair the time sequence by a size _ cell method, and finally revise the name of the replaced virtual unit into the name of the original standard unit, so that the SDF file meeting the requirement of Setup/Hold time sequence at the early stage of back-end time sequence convergence can be generated without changing the netlist. The SDF file is used for post-simulation without frequency reduction operation, the reliability of a simulation result is greatly improved, and the post-simulation time is greatly advanced.
Drawings
Fig. 1 is a flowchart of a method for generating a standard format file according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an apparatus for generating a standard delay format file according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a method for generating a standard delay format file, as shown in fig. 1, where the method includes:
and S11, analyzing the time sequence of the chip according to the standard cell library and the input file used by the chip, and determining the standard cell of the time sequence violation.
The chip foundry provides a standard cell library, reads in the standard cell library, reads in an input file including a netlist file netlist, a standard parasitic exchange format (spef) file and a delay constraint (sdc) file, uses the standard cell library, does not set a PTSI (PTSI is signal integrity analysis based on PrimeTime), does not set an AOCV (Advanced on chip variation) for describing normal distribution in a chip manufacturing process, retains clock uncertainty (clock uncertainty for describing uncertainty of a chip clock), outputs a timing analysis result of different working mode modes of a current process corner, and determines a standard cell of a timing violation according to the timing analysis result.
S12, replacing the standard cell with the virtual cell meeting the Setup/Hold time sequence requirement of the standard cell with the time sequence violation standard cell by the size _ cell method to obtain the tcl format file for repairing the time sequence.
Before the size _ cell, we will construct a library with different delay characteristics according to the standard cell library used by the chip. Specifically, a virtual cell having a different delay time is constructed for each standard cell with reference to all standard cells in a standard cell library used for a chip. Assuming that the delay of the standard cell is delay, virtual cells with different delays of the standard cell are constructed by using a multiplication algorithm, and the delays of the constructed virtual cells are delayX50, delayX10, delayX5, delayx0.1 and delayx0.01 respectively, where delayX50 represents 50 times of delay, and similarly, delayX10 represents 10 times of delay, delayX5 represents 5 times of delay, delayx0.1 represents 0.1 times of delay, delayx0.01 represents 0.01 times of delay, and the name of each virtual cell is prefixed by super, for example, super _ X0p01 represents a virtual cell of 0.01 of delay.
Taking a standard unit with a time sequence violation as an example when the size _ cell is used, selecting a virtual unit with a time sequence capable of meeting the Setup/Hold time sequence requirement from all virtual units of the standard unit with the time sequence violation, replacing the original standard unit with the virtual unit, wherein the time sequence after replacement meets the requirement, generating a tcl format file for repairing the time sequence, and naming the file as ECO.tcl.
And S13, generating a standard delay format file meeting the time sequence requirement of Setup/Hold according to the tcl format file.
And reading in ECO.tcl, and outputting a standard delay format file of the current process corner, which meets the Setup/Hold time sequence requirement, by the write _ sdf.
S14, the name of the virtual unit of the standard unit used for replacing the time sequence violation in the standard time delay format file is modified into the name of the replaced standard unit of the time sequence violation, and the final standard time delay format file is obtained.
Before size _ cell, we output a list of all standard cells in the standard cell library used by the chip, where the format of this list is inst _ name ref _ name, where inst _ name represents the hierarchical name of the standard cell in the chip, ref _ name represents the cell name of the standard cell, and this list may be named file.
After the standard delay format file is obtained, the list file is used for modifying the name of the virtual unit of the standard unit for replacing the timing violation into the name of the replaced standard unit of the timing violation, so that the unit name of the final standard delay format file is consistent with the unit name in the netlist, although the unit names are consistent, the delay of the unit is changed, and the delay of the virtual unit is used, so that the timing requirement can be met.
And reading the final standard delay format file and the netlist file netlist again, similarly not setting PTSI and AOCV, removing clock uncertainties, verifying whether the final standard delay format file meets the time sequence requirement or not, and outputting the final standard delay format file when the final standard delay format file meets the time sequence requirement.
In the following, a specific example is described, in which there is a buffer in the chip, the timing of which does not meet the requirements, and its name in file
u _ top/u _ block1/u _ cpu/u _ core1/u1BUFFD1HVT, wherein u _ top/u _ block1/u _ cpu/u _ core1/u1 represents the layer name of the buffer in the chip, BUFFD1HVT represents the name of the buffer, for this buffer a faster time-sequenced buffer and a slower time-sequenced buffer are constructed, assuming that the delay of the buffer is delay, respectively constructing a virtual buffer named BUFFD 50, delayX10, delayX5, delayX0.1 and delayX0.01, and respectively named BUFFD1 HVUPX 50, BUFFD1 HVTUPERX 10, BUFFD1 HVUPERX 5, BUFFD1 HVUPX 0p1, BUFFD1 HVP 3, and PrimeUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUpUp, after the time sequence is corrected, the following steps are carried out:
u _ top/u _ block1/u _ cpu/u _ core1/u1BUFFD1 HVTupserX 50, and the standard delay format SDF file generated at this time is:
(CELL
(CELLTYPE“BUFFD1HVTsuperX50”)
(INSTANCE u_top/u_block1/u_cpu/u_core1/u1
…)
finally, we need to change the changed ref _ name back to the original ref _ name according to file.list, i.e. modify BUFFD1HVTsuperX50 to BUFFD1HVT, the SDF file will become:
(CELL
(CELLTYPE“BUFFD1HVT”)
(INSTANCE u_top/u_block1/u_cpu/u_core1/u1
…)
in this way, the cell names and netlist remain the same, although the cell names are also BUFFD1HVT, but the delay is actually BUFFD1 HVTsuuperX 50.
By the method, the SDF file of the current process corner can be obtained, for different process corners, the SDF file of the process corner can be obtained according to the method, one set of SDF file is provided for each process corner, and the problem that MAX/MIN mutual blocking is introduced by heterozygosis of a plurality of corners is avoided.
The method for generating the standard delay format file provided by the embodiment of the invention constructs the virtual units with different delays of all the standard units, restores the time sequence by the size _ cell method, and finally revises the replaced virtual unit name into the original standard unit name again to keep the netlist information consistent.
An embodiment of the present invention further provides a device for generating a standard delay format file, as shown in fig. 2, the device includes:
the determining module 21 is configured to perform timing analysis on the chip according to a standard cell library and an input file used by the chip, and determine a standard cell of a timing violation;
a replacing module 22, configured to replace, by using a size _ cell method, the standard cell with the timing violation by using a virtual cell that meets the Setup/Hold timing requirement of the standard cell with the timing violation, so as to obtain a tcl format file for repairing the timing;
the generating module 23 is configured to generate a standard delay format file meeting the Setup/Hold time sequence requirement according to the tcl format file;
a modifying module 24, configured to modify the name of the virtual unit of the standard unit used for replacing the timing violation in the standard delay format file into the name of the replaced standard unit of the timing violation, so as to obtain a final standard delay format file.
Further, the dummy cells meeting Setup/Hold timing requirements of the standard cells of the timing violation used by the replacement module 22 include dummy cells with a delay of delayX50, delayX10, delayX5, delayx0.1, or delayx0.01, where delay is the delay of the standard cells of the timing violation.
Further, the input file used by the determining module 21 includes: netlist files, standard parasitic interchange format files, and delay constraint files.
The device for generating the standard delay format file provided by the embodiment of the invention constructs the virtual units with different delays of all the standard units, restores the time sequence by the size _ cell method, and finally revises the replaced virtual unit name into the original standard unit name again to keep the netlist information consistent.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are also within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (6)
1. A method for generating a standard time-lapse format file, comprising:
performing time sequence analysis on a chip according to a standard cell library and an input file used by the chip to determine a standard cell of a time sequence violation;
replacing the standard unit of the time sequence violation by a virtual unit meeting the Setup/Hold time sequence requirement of the standard unit of the time sequence violation by using a size _ cell method to obtain a tcl format file for repairing the time sequence;
generating a standard delay format file meeting the Setup/Hold time sequence requirement according to the tcl format file;
and modifying the name of the virtual unit of the standard unit used for replacing the time sequence violation in the standard time delay format file into the name of the replaced standard unit of the time sequence violation to obtain a final standard time delay format file.
2. The method of claim 1, wherein the dummy cells meeting Setup/Hold timing requirements of the standard cells for the timing violation comprise dummy cells with a delay of delayX50, delayX10, delayX5, delayX0.1, or delayX0.01, where delay is the delay of the standard cells for the timing violation.
3. The method of claim 1, wherein the input file comprises: netlist files, standard parasitic interchange format files, and delay constraint files.
4. An apparatus for generating a standard time-lapse format file, comprising:
the determining module is used for carrying out time sequence analysis on the chip according to a standard cell library and an input file used by the chip and determining a standard cell of a time sequence violation;
a replacing module, configured to replace the standard unit with the virtual unit meeting the Setup/Hold time sequence requirement of the standard unit with the time sequence violation by using a size _ cell method, so as to obtain a tcl format file for repairing the time sequence;
the generating module is used for generating a standard delay format file meeting the Setup/Hold time sequence requirement according to the tcl format file;
and the modification module is used for modifying the name of the virtual unit of the standard unit used for replacing the time sequence violation in the standard time delay format file into the name of the replaced standard unit of the time sequence violation to obtain a final standard time delay format file.
5. The apparatus of claim 4, wherein the dummy cells meeting Setup/Hold timing requirements of the standard cells of the timing violation used by the replacement module comprise dummy cells with a delay of delayX50, delayX10, delayX5, delayX0.1, or delayX0.01, where delay is the delay of the standard cells of the timing violation.
6. The apparatus of claim 4, wherein the input file comprises: netlist files, standard parasitic interchange format files, and delay constraint files.
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| CN111881637B (en) * | 2020-07-08 | 2021-05-04 | 广芯微电子（广州）股份有限公司 | Method, system and storage medium for optimizing power consumption of digital circuit |
| CN112287569B (en) * | 2020-12-29 | 2021-03-23 | 芯华章科技股份有限公司 | Method, electronic device and storage medium for simulating logic system design |
| CN112800704B (en) * | 2021-04-06 | 2021-06-25 | 深圳英集芯科技股份有限公司 | Function buffer-based chip rear-end revising method and device and computer equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102147567A (en) * | 2011-04-01 | 2011-08-10 | 中国科学院微电子研究所 | Cell-based hierarchical optical proximity correction (OPC) method |
| CN105488287A (en) * | 2015-12-04 | 2016-04-13 | 上海兆芯集成电路有限公司 | Time sequence correction method and electronic device |
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| JP2016177535A (en) * | 2015-03-20 | 2016-10-06 | 株式会社リコー | Data transmission device, data transmission system, and program |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102147567A (en) * | 2011-04-01 | 2011-08-10 | 中国科学院微电子研究所 | Cell-based hierarchical optical proximity correction (OPC) method |
| CN105488287A (en) * | 2015-12-04 | 2016-04-13 | 上海兆芯集成电路有限公司 | Time sequence correction method and electronic device |
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