CN111881637B - Method, system and storage medium for optimizing power consumption of digital circuit - Google Patents
Method, system and storage medium for optimizing power consumption of digital circuit Download PDFInfo
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- CN111881637B CN111881637B CN202010653908.8A CN202010653908A CN111881637B CN 111881637 B CN111881637 B CN 111881637B CN 202010653908 A CN202010653908 A CN 202010653908A CN 111881637 B CN111881637 B CN 111881637B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/337—Design optimisation
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/06—Power analysis or power optimisation
Abstract
One embodiment of the present application provides a method, a system, and a storage medium for optimizing power consumption of a layer digital circuit, wherein the method includes: repairing the established time sequence violation; restoring a set-up time sequence program according to the set-up time sequence violation; screening and deleting the removable buffer through the repaired establishment time program according to the establishment time sequence violation; and repairing the retention time violation and finishing the power consumption optimization of the digital circuit. The invention mainly utilizes different flow sequences, and achieves the purpose of better optimizing power consumption by changing the sequence of the repair time sequence and the power consumption optimization. Since the power consumption optimization method is to reduce the size of the device or reduce the number of buffers, the power consumption and the retention time are both favorable after the size of the device is reduced, so that the use amount of the device can be reduced when the repair retention time is reduced after the power consumption optimization, and the optimization of the area and the power consumption is further favorable.
Description
Technical Field
The present invention relates to the field of digital circuit design technologies, and in particular, to a method, a system, and a storage medium for optimizing power consumption of a digital circuit.
Background
With the rapid development of technology and process, power consumption becomes a very critical problem in integrated circuit design, and after deep submicron and nanometer processes are performed, the size of a device is further reduced, the performance of a circuit is rapidly improved, the integration level of the circuit is rapidly increased, and a plurality of new power consumption problems occur, for example, a series of new problems are caused by rapid increase of leakage current. Low power designs also face more problems and higher demands, especially in applications sensitive to increased power consumption, such as high performance computer systems, portable electronic products, and mobile communication products.
In the process of realizing the digital circuit, the traditional power consumption optimization flow is to optimize the power consumption after the time sequence is completely converged, although the method can reduce the power consumption of the chip to a certain extent, the chip area increased for repairing and maintaining the time sequence violation when the time sequence convergence of the chip is met is wasted. For example, the added buffer to fix the hold violation, may not need to be added after power consumption optimization.
Disclosure of Invention
The invention provides a method and a system for optimizing the power consumption of a digital circuit.A time sequence signing and checking tool is PrimeTime which can be repeatedly used on different process platforms and different items, so that the power consumption and the area of the digital circuit of a chip are reduced, and the production and manufacturing cost of the chip is saved.
One embodiment of the present invention provides a method for optimizing power consumption of a layer digital circuit, comprising:
repairing the established time sequence violation;
restoring a set-up time sequence program according to the set-up time sequence violation;
screening and deleting the removable buffer through the repaired establishment time program according to the establishment time sequence violation;
according to the setup time sequence violation, screening and replacing the device meeting the preset size through the repaired setup time program;
and repairing the retention time violation and finishing the power consumption optimization of the digital circuit.
Further, the repairing the setup time timing violation comprises: and screening connecting wires and load circuits meeting preset conditions, judging the insertion position of the buffer, and completing the insertion of the buffer according to the position.
Further, the remediating a hold time violation comprises: judging and establishing a time violation path, judging the insertion position of a buffer or a delayer on the violation path, and inserting the buffer or the delayer according to the insertion position of the buffer or the delayer.
One embodiment of the present invention provides a system for optimizing power consumption of a digital circuit, including:
the establishing time sequence violation repairing module is used for repairing establishing time sequence violation;
the repair program installation module is used for repairing the establishment time sequence program according to the establishment time sequence violation;
the buffer removing module is used for repairing according to the setup time sequence violation, and screening and deleting the removable buffer through the repaired setup time program;
the device replacing module is used for screening and replacing devices meeting the preset size through the repaired establishing time program according to the establishing time sequence violation;
and the repair holding time violation module is used for repairing the holding time violation and finishing the power consumption optimization of the digital circuit.
Further, the system for optimizing power consumption of a digital circuit further includes: the buffer insertion first module is used for screening connecting wires and load circuits meeting preset conditions, judging the insertion position of the buffer, and completing the buffer insertion according to the position.
Further, the system for optimizing power consumption of a digital circuit further includes: and the buffer or delay unit is inserted into the second module and used for judging and establishing a time violation path, judging the insertion position of the buffer or the delay unit on the violation path and inserting the buffer or the delay unit according to the insertion position of the buffer or the delay unit.
One embodiment of the present invention provides a computer-readable storage medium, comprising: the storage medium comprises a stored computer program, wherein the apparatus in which the computer readable storage medium is located is controlled to perform any one of the above methods for power consumption optimization of a digital circuit when the computer program runs.
Compared with the prior art, the embodiment of the invention has the beneficial effects that:
one embodiment of the present application provides a method for optimizing power consumption of a layer digital circuit, including: repairing the established time sequence violation; restoring a set-up time sequence program according to the set-up time sequence violation; screening and deleting the removable buffer through the repaired establishment time program according to the establishment time sequence violation; according to the setup time sequence violation, screening and replacing the device meeting the preset size through the repaired setup time program; and repairing the retention time violation and finishing the power consumption optimization of the digital circuit. The invention mainly utilizes different flow sequences, and achieves the purpose of better optimizing power consumption by changing the sequence of the repair time sequence and the power consumption optimization. Since the power consumption optimization method is to reduce the size of the device or reduce the number of buffers, the power consumption and the retention time are both favorable after the size of the device is reduced, so that the usage amount of the device can be reduced when the repair retention time is reduced after the power consumption optimization, and the optimization of the area and the power consumption is further favorable.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow chart of a method for power consumption optimization of a digital circuit according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for power consumption optimization of a digital circuit according to another embodiment of the present invention;
FIG. 3 is a diagram of an apparatus for a system for power consumption optimization of a digital circuit according to an embodiment of the present invention;
fig. 4 is a diagram of a system for power consumption optimization of a digital circuit according to another embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be understood that the step numbers used herein are for convenience of description only and are not intended as limitations on the order in which the steps are performed.
It is to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
The terms "comprises" and "comprising" indicate the presence of the described features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The term "and/or" refers to and includes any and all possible combinations of one or more of the associated listed items.
A first aspect.
Referring to fig. 1, an embodiment of the invention provides a method for optimizing power consumption of a digital circuit, including:
and S10, repairing the establishing time sequence violation.
And S20, repairing the program of establishing the time sequence according to the violation of establishing the time sequence.
S30, screening and deleting the removable buffer by the repaired time repairing program according to the established time sequence violation.
And S40, repairing the retention time violation and finishing the power consumption optimization of the digital circuit.
In one embodiment, the power consumption is optimized by changing the device size and deleting the buffer.
Changing the size of the device means that a device with a larger size is changed into a smaller device, and the small device can reduce power consumption and chip area. In the alternative to device cells with different threshold voltages, generally, the threshold voltages of the same device cell can be classified into HVT (high voltage threshold), RVT (normal voltage threshold), LVT (low voltage threshold). Their velocity magnitudes are arranged in order of LVT, RVT, HVT, fast to slow. The power consumption is the opposite. Therefore, on the premise that the chip timing allows, the device unit with the high voltage threshold can be used for replacing the device unit with the low voltage threshold, which is a common method for repairing leakage. And the device units with different drives are replaced, and the devices with smaller drives are replaced on the premise of meeting the time sequence, so that the power consumption and the area of the devices with smaller drives and larger drives are smaller, and the optimization of the power consumption and the area of the chip is facilitated.
The elimination of the buffer device unit is optimized on the premise of ensuring no deterioration of the time sequence as the size of the device is changed, and the reduction of the buffer device can reduce not only the power consumption but also the chip area. When power consumption is repaired, a holding time margin and a building time margin are required to be set, and safety margins are respectively reserved for building time and holding time when power consumption is optimized.
The time violation of repair and establishment can flexibly adopt various methods, and a proper mode is selected under the condition of comprehensively considering the power consumption and the area of the chip.
The insertion buffer builds a time violation. Because some setup time violations are due to drv (design rule violations), the delay of a device cell is calculated from its input transition time, and the output load by looking up a table. Therefore, we solve the problems of capacitive loading and input switching time, and the timing sequence is naturally solved. The problem with drv is that it can be repaired by inserting a buffer, for example, if the connection line is too long and the drive is weak, the buffer can be inserted and the drive can be increased by breaking it continuously; too large a load may also reduce the number of loads by inserting buffers. If the driving capability of a certain device cell is too weak, a larger delay is easily generated, so that the driving capability can be improved by replacing the larger device cell, for example, the buffer of X1 is replaced by X4, X8, and the like. However, before the amplifier is replaced, the change of the input/output transition time of the device unit needs to be noticed, because the device unit with strong driving capability is also larger as a load, and the situation that the previous-stage device unit cannot drive the device unit can be caused, the actual data path situation is more complicated, and the delay is reduced without replacing the driving unit with a larger one. In general, if we see that the output transition time of a cell is much larger than the input transition time, which indicates that the cell is not driven enough, we can try to make the cell larger. In addition, the length of the starting clock path and the acquiring clock path can be changed manually, so that the establishment time violation can be repaired.
And finally, repairing the hold time violation, wherein the repair of the hold time violation is simpler than the establishment of the time violation. It is common to insert buffers or delay devices on paths where there is a setup time violation. In addition, the lengths of the starting clock path and the acquiring clock path can be changed manually, and the holding time violation can be repaired.
The invention mainly utilizes different flow sequences and achieves the purpose of better optimizing power consumption by changing the sequence of time sequence repair and power consumption optimization. Because the power consumption optimization method is to reduce the size of the device or reduce the number of buffers, the device unit is beneficial to both power consumption and holding time after being reduced, so that the holding time is put after the power consumption optimization to reduce the use amount of the device when the holding time is violated, and further the optimization of the area and the power consumption is facilitated.
Referring to fig. 2, the present invention provides a method for optimizing power consumption of a digital circuit, further comprising:
s11, screening connecting wires and load circuits meeting preset conditions, judging the insertion position of the buffer, and completing the insertion of the buffer according to the position.
And S31, screening and replacing the devices meeting the preset size through the repaired establishing time program according to the establishing time sequence violation.
S41, judging and establishing a time violation path, judging the insertion position of a buffer or a delayer on the violation path, and inserting the buffer or the delayer according to the insertion position of the buffer or the delayer.
The invention mainly utilizes different flow sequences and achieves the purpose of better optimizing power consumption by changing the sequence of time sequence repair and power consumption optimization. Since the power consumption optimization method is to reduce the size of the device or reduce the number of buffers, the device size is reduced, and then the power consumption and the holding time are both favorable, so that the use amount of the device is reduced when the holding time is reduced after the power consumption optimization, and further the optimization of the area and the power consumption is favorable.
A second aspect.
Referring to fig. 3, an embodiment of the invention provides a system for optimizing power consumption of a digital circuit, including:
and a setup time sequence violation repairing module 10, configured to repair the setup time sequence violation.
And a repairing program installing module 20, configured to repair the establishing time sequence program according to the establishing time sequence violation.
And a buffer removing module 30, configured to filter and delete the removable buffer according to the setup time sequence violation through the repaired setup time program.
And a repair hold time violation module 40, configured to repair the hold time violation and complete power consumption optimization of the digital circuit.
In one embodiment, the power consumption is optimized by changing the device size and deleting the buffer.
Changing the size of the device means that a device with a larger size is changed into a smaller device, and the small device can reduce power consumption and chip area. In the alternative to device cells with different threshold voltages, generally, the threshold voltages of the same device cell can be classified into HVT (high voltage threshold), RVT (normal voltage threshold), LVT (low voltage threshold). Their velocity magnitudes are arranged in order of LVT, RVT, HVT, fast to slow. The power consumption is the opposite. Therefore, on the premise that the chip timing allows, the device unit with the high voltage threshold can be used for replacing the device unit with the low voltage threshold, which is a common method for repairing leakage. And the device units with different drives are replaced, and the devices with smaller drives are replaced on the premise of meeting the time sequence, so that the power consumption and the area of the devices with smaller drives and larger drives are smaller, and the optimization of the power consumption and the area of the chip is facilitated.
The elimination of the buffer device unit is optimized on the premise of ensuring no deterioration of the time sequence as the size of the device is changed, and the reduction of the buffer device can reduce not only the power consumption but also the chip area. When power consumption is repaired, a holding time margin and a building time margin are required to be set, and safety margins are respectively reserved for building time and holding time when power consumption is optimized.
The time violation of repair and establishment can flexibly adopt various methods, and a proper mode is selected under the condition of comprehensively considering the power consumption and the area of the chip.
The insertion buffer builds a time violation. Because some setup time violations are due to drv (design rule violations), the delay of a device cell is calculated from its input transition time, and the output load by looking up a table. Therefore, we solve the problems of capacitive loading and input switching time, and the timing sequence is naturally solved. The problem with drv is that it can be repaired by inserting a buffer, for example, if the connection line is too long and the drive is weak, the buffer can be inserted and the drive can be increased by breaking it continuously; too large a load may also reduce the number of loads by inserting buffers. If the driving capability of a certain device cell is too weak, a larger delay is easily generated, so that the driving capability can be improved by replacing the larger device cell, for example, the buffer of X1 is replaced by X4, X8, and the like. However, before the amplifier is replaced, the change of the input/output transition time of the device unit needs to be noticed, because the device unit with strong driving capability is also larger as a load, and the situation that the previous-stage device unit cannot drive the device unit can be caused, the actual data path situation is more complicated, and the delay is reduced without replacing the driving unit with a larger one. In general, if we see that the output transition time of a cell is much larger than the input transition time, which indicates that the cell is not driven enough, we can try to make the cell larger. In addition, the length of the starting clock path and the acquiring clock path can be changed manually, so that the establishment time violation can be repaired.
And finally, repairing the hold time violation, wherein the repair of the hold time violation is simpler than the establishment of the time violation. It is common to insert buffers or delay devices on paths where there is a setup time violation. In addition, the lengths of the starting clock path and the acquiring clock path can be changed manually, and the holding time violation can be repaired.
The invention mainly utilizes different flow sequences and achieves the purpose of better optimizing power consumption by changing the sequence of time sequence repair and power consumption optimization. Because the power consumption optimization method is to reduce the size of the device or reduce the number of buffers, the device unit is beneficial to both power consumption and holding time after being reduced, so that the holding time is put after the power consumption optimization to reduce the use amount of the device when the holding time is violated, and further the optimization of the area and the power consumption is facilitated.
Referring to fig. 4, an embodiment of the present invention provides a system for optimizing power consumption of a digital circuit, further including:
and a device replacement module 50, configured to screen and replace the device meeting the preset size through the repaired setup time program according to the setup time sequence violation.
The buffer insertion first module 60 is used for screening the connection lines and the load circuits meeting the preset conditions, judging the buffer insertion positions, and completing the buffer insertion according to the positions.
The buffer or delay insertion second module 70 is used for determining to establish a time violation path, determining a buffer or delay insertion position on the violation path, and performing buffer or delay insertion according to the buffer or delay insertion position.
In a third aspect.
An embodiment of the present invention provides a computer-readable storage medium, including: the storage medium comprises a stored computer program, wherein the computer program, when executed, controls an apparatus in which the computer readable storage medium is located to perform a method for power consumption optimization of a digital circuit as described in any one of the above.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (7)
1. A method for power consumption optimization of a digital circuit, comprising:
repairing the established time sequence violation;
restoring a set-up time sequence program according to the set-up time sequence violation;
screening and deleting the removable buffer through the repaired establishment time program according to the establishment time sequence violation;
according to the setup time sequence violation, screening and replacing the device meeting the preset size through the repaired setup time program;
and repairing the retention time violation and finishing the power consumption optimization of the digital circuit.
2. The method of power consumption optimization for digital circuits according to claim 1, wherein said repairing setup time timing violations comprises: and screening connecting wires and load circuits meeting preset conditions, judging the insertion position of the buffer, and completing the insertion of the buffer according to the position.
3. The method of power consumption optimization for digital circuits according to claim 1, wherein said repairing a hold time violation comprises: judging and establishing a time violation path, judging the insertion position of a buffer or a delayer on the violation path, and inserting the buffer or the delayer according to the insertion position of the buffer or the delayer.
4. A system for power consumption optimization of a digital circuit, comprising:
the establishing time sequence violation repairing module is used for repairing establishing time sequence violation;
the repair program installation module is used for repairing the establishment time sequence program according to the establishment time sequence violation;
the buffer removing module is used for repairing according to the setup time sequence violation, and screening and deleting the removable buffer through the repaired setup time program;
the device replacing module is used for screening and replacing devices meeting the preset size through the repaired establishing time program according to the establishing time sequence violation;
and the repair holding time violation module is used for repairing the holding time violation and finishing the power consumption optimization of the digital circuit.
5. The system for power consumption optimization of digital circuits according to claim 4, further comprising: the buffer insertion first module is used for screening connecting wires and load circuits meeting preset conditions, judging the insertion position of the buffer, and completing the buffer insertion according to the position.
6. The system for power consumption optimization of digital circuits according to claim 4, further comprising: and the buffer or delay unit is inserted into the second module and used for judging and establishing a time violation path, judging the insertion position of the buffer or the delay unit on the violation path and inserting the buffer or the delay unit according to the insertion position of the buffer or the delay unit.
7. A computer-readable storage medium, comprising: the storage medium comprises a stored computer program, wherein the computer program, when executed, controls an apparatus in which the computer readable storage medium is located to perform a method of power consumption optimization for a digital circuit according to any of claims 1 to 3.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113343622B (en) * | 2021-06-23 | 2023-06-13 | 海光信息技术股份有限公司 | Circuit optimization method and device, electronic equipment and readable storage medium |
| CN114861578B (en) * | 2022-07-05 | 2022-10-11 | 飞腾信息技术有限公司 | Method, device, equipment and storage medium for repairing hold time violation |
| CN115796093B (en) * | 2023-01-03 | 2023-08-08 | 摩尔线程智能科技(北京)有限责任公司 | Circuit time sequence optimization method and device, electronic equipment and storage medium |
| CN116702664B (en) * | 2023-08-03 | 2024-01-26 | 飞腾信息技术有限公司 | Time violation repairing method and device, computer equipment and storage medium |
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