CN207115406U - A kind of FPGA accelerates board and server cluster - Google Patents
A kind of FPGA accelerates board and server cluster Download PDFInfo
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- CN207115406U CN207115406U CN201720866367.0U CN201720866367U CN207115406U CN 207115406 U CN207115406 U CN 207115406U CN 201720866367 U CN201720866367 U CN 201720866367U CN 207115406 U CN207115406 U CN 207115406U
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- fpga
- power supply
- board
- master card
- accelerates
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- 238000003780 insertion Methods 0.000 claims description 5
- 230000037431 insertion Effects 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 4
- 230000001133 acceleration Effects 0.000 abstract description 6
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 230000006870 function Effects 0.000 description 16
- 238000013461 design Methods 0.000 description 6
- 238000003860 storage Methods 0.000 description 5
- 238000012360 testing method Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Abstract
This application discloses a kind of FPGA to accelerate board, including：It is integrated with the master card of fpga chip and each function component；It is vertically connected with master card, predeterminated voltage and the power supply subcard of predetermined current is provided for master card using integrated power supply module.By the power supply subcard where the module that is split as powering by existing FPGA acceleration boards and it is integrated with the master card of fpga chip and other function components, and make full use of the groove position thickness of itself, power supply subcard is vertically mounted in master card so that power supply subcard is not take up the length that the FPGA accelerates board.Provide the FPGA that a kind of integrated level is higher, occupancy groove bit space is smaller and accelerate board, in same amount of service tank position more FPGA can be set to accelerate boards, arithmetic speed is faster.Disclosed herein as well is a kind of server cluster, has above-mentioned beneficial effect.
Description
Technical field
The application is related to FPGA technology field, and more particularly to a kind of FPGA accelerates board and server cluster.
Background technology
Increasingly wider with FPGA technology application, the board based on FPGA technology occurs extensively, FPGA
(Field-Programmable Gate Array, Chinese are entitled：Field programmable gate array), it is in PAL, GAL, CPLD etc.
The product further developed on the basis of programming device, and as a kind of semi-custom circuit in application specific integrated circuit field and
Occur, both solved the deficiency of common custom circuit, and overcome the shortcomings that original programming device gate circuit number is limited again.
The existing FPGA accelerator cards card produced based on FPGA technology would generally large scale deployment in server cluster
In environment, and its size is typically compliant with the standard of total length overall height and a groove position thickness so that a standard cell on server
Position can only set a FPGA to accelerate board, largely occupy limited groove bit space.
So how on the premise of number of slots amount, assurance function integrality is not increased, there is provided a kind of integrated level is higher,
It is those skilled in the art's urgent problem to be solved to take the smaller FPGA of groove bit space to accelerate board.
Utility model content
The purpose of the application is to provide a kind of FPGA and accelerates board and server cluster, and its integrated level is higher, takes groove position
Space is smaller, enabling sets greater number of FPGA to accelerate board, arithmetic speed in same amount of service tank position
Faster.
In order to solve the above technical problems, the application, which provides a kind of FPGA, accelerates board, the FPGA accelerates board to include：
It is integrated with the master card of fpga chip and each function component；
It is vertically connected with the master card, predeterminated voltage and predetermined current is provided for the master card using integrated power supply module
Power supply subcard.
Optionally, the power supply daughter cards removable is vertically mounted in the master card.
Optionally, connector is provided with the master card, the slot of the first predetermined number is provided with the connector；It is described
Power supply subcard is provided with and the first contact pin of the slot quantity identical, the insertion slot of first pins normal.
Optionally, the power supply subcard is welded in the master card.
Optionally, the hole of the second predetermined number is provided with the master card；The power supply subcard is provided with and described hole
The contact pin of quantity identical second, second pins normal are welded in described hole.
Optionally, the FPGA accelerates the size of board to meet a half high half long and groove position thickness calibration.
Optionally, it is specially height 68mm, length 167mm, thickness 21mm that the FPGA, which accelerates the size of board,.
Optionally, the power supply module is specially six road power supplys.
Optionally, the fpga chip is specially the GX 10AX115H3F34E2SG chips of Arria 10.
Present invention also provides a kind of server cluster, the FPGA that the server cluster is provided with as described in above-mentioned content adds
Fast board.
A kind of FPGA provided herein accelerates board, including is integrated with the mother of fpga chip and each function component
Card；It is vertically connected with the master card, predeterminated voltage and the electricity of predetermined current is provided for the master card using integrated power supply module
Source subcard.
Obviously, technical scheme provided herein is by the way that existing FPGA acceleration boards are split as where power supply module
Power supply subcard and the master card for being integrated with fpga chip and other function components, and the groove position thickness of itself is made full use of, will
Power supply subcard is vertically mounted in master card so that power supply subcard is not take up the length that the FPGA accelerates board.Provide a kind of collection
Into Du Genggao, the smaller FPGA acceleration boards of groove bit space are taken, can be set in same amount of service tank position more
FPGA accelerate board, arithmetic speed is faster.Present invention also provides a kind of server cluster, has above-mentioned beneficial effect,
This is repeated no more.
Brief description of the drawings
, below will be to embodiment or existing in order to illustrate more clearly of the embodiment of the present application or technical scheme of the prior art
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
The embodiment of application, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
The accompanying drawing of offer obtains other accompanying drawings.
A kind of FPGA that Fig. 1 is provided by the embodiment of the present application accelerates the structured flowchart of board；
A kind of FPGA that Fig. 2 is provided by the embodiment of the present application accelerates the structured flowchart of master card in board；
A kind of structured flowchart for server cluster that Fig. 3 is provided by the embodiment of the present application.
Embodiment
The core of the application is to provide a kind of FPGA and accelerates board and server cluster, and its integrated level is higher, takes groove position
Space is smaller, enabling sets greater number of FPGA to accelerate board, arithmetic speed in same amount of service tank position
Faster.
To make the purpose, technical scheme and advantage of the embodiment of the present application clearer, below in conjunction with the embodiment of the present application
In accompanying drawing, the technical scheme in the embodiment of the present application is clearly and completely described, it is clear that described embodiment is
Some embodiments of the present application, rather than whole embodiments.Based on the embodiment in the application, those of ordinary skill in the art
The all other embodiment obtained under the premise of creative work is not made, belong to the scope of the application protection.
Fig. 1 is referred to below, and a kind of FPGA that Fig. 1 is provided by the embodiment of the present application accelerates the structured flowchart of board.
The FPGA accelerates board to include：
It is integrated with the master card 100 of fpga chip and each function component；
The master card 100 be with it is existing meet total length overall height, the FPGA of groove position thickness calibration accelerates board
The FPGA being substantially the same accelerates board, and only it eliminates the power supply that the existing FPGA for meeting arm's length standard accelerates board
Module, that is, possess the interface of common PCIE all the way × 8, two-way 10G optical module SFP+ interfaces, two SODIMM slots, JTAG and survey
Try mouth, necessary LED light and button, the flash card of certain capacity and most important FPGA process chips, it is simply single
It is single to accelerate to separate power supply module on board by original FPGA, think that making higher integrated level lays the groundwork.It is specific how
Each function component above-mentioned is set, may refer to Fig. 2, a kind of FPGA that Fig. 2 is provided by the embodiment of the present application accelerates
The structured flowchart of master card in board.
Wherein, FPGA accelerates board, and be otherwise known as FPGA hardware accelerator card, hardware-accelerated to refer to utilize hardware module,
FPGA computing chips and periphery function component substitute software algorithm to make full use of the intrinsic rapid charater of hardware.From
From the point of view of software, hardware accelerator interface is just with calling a function.Only difference is that this function resides in
It is transparent to call function in hardware.Further, hardware-accelerated degree depends on the difference of algorithm, performs the time most
Height can than without using it is hardware-accelerated when foreshorten to 1 percent, and hardware when performing various operations much faster, such as perform
Complicated math function, data are transferred to another place from a place, and same manipulation is performed a plurality of times.Some classes
Like such popular software also achievable operation, these, which are operated, after hardware-accelerated can obtain great performance raising.
If FPGA is used in system design, then whenever can add the hard of customization in the design cycle
Part.Designer can write software code, and being run before final finalize a text on hardware components at once.Further, it is also possible to
Method of addition is taken to determine which partial code is realized with hardware rather than with software.The developing instrument that FPGA suppliers are provided
The seamless switching between hardware and software can be achieved, this is the mesh for setting FPGA to accelerate board on a large scale in server cluster
's.
In addition, the interface of PCIE × 8 used, PCIE interfaces employ at present popular point-to-point serial connection in the industry, energy
Higher transmission rate and quality are provided.PCIE interface is different according to bus bit wide and difference, including X1, X4, X8 with
And X16, specification are connected to 32 passages from 1 passage, different port numbers mainly has an impact to bandwidth, adopted under normal circumstances
X8 interface.
SFP+ (Small Form-factor Pluggables) interface, for kilomegabit electric signal to be converted into light letter
Number, and the SFP+ interfaces are the upgrade versions of SFP interfaces, can possess in the case of size identical with SFP interfaces and be several times as much as SFP
The transmission rate of interface, reaches 10G, and the design of two-way is sufficient for the demand largely calculated.
SODIMM (Small Outline Dual In-line Memory Module, small outline dual inline internal memory mould
Block), it is a type of calculator memory module, for providing sufficient internal memory to calculate.Certain capacity also be present simultaneously
NOR FLASH storage chips, this is a kind of very common storage chip, its possess power failure data do not lose, program can be straight
The characteristics of being performed in FLASH pieces is connected on, therefore, in embedded systems, NOR FLASH storage chips are well suited as starting journey
As long as reading of the storage medium .NOR FLASH storage chips of sequence to data can provide the address of data, data/address bus is with regard to energy
It is enough correctly to provide data.
JTAG (Joint Test Action Group, joint test working group) is a kind of international standard test protocol, main
It is used for chip internal test.Most high-grade devices all supports JTAG protocol, including FPGA devices provided herein now
Part etc..
It is vertically connected with master card 100, predeterminated voltage and the electricity of predetermined current is provided for master card using integrated power supply module
Source subcard 200.
The power supply module of board is accelerated to peel off out because original is present in into FPGA, the power supply mould that the application will separate
Group is separately provided as a power supply subcard, is each function component because in the FPGA that prior art is provided accelerates board
Between often carry out the transmission of high speed signal, and mix the power supply module being arranged on same plate with them often to this
A little high speed signals are disturbed so that are accelerated board efficiently to run FPGA and manufactured obstacle, and strong influence is stable
Property.
The application makes full use of one by the way that power supply module to be individually stripped out to form a single power supply subcard
The standard of groove position thickness, vertical is installed in master card 100, i.e. the height of the power supply subcard and the thickness for being no more than groove position, can
To accomplish and be arranged on the highly consistent of each function component in horizontal positioned master card, such design need not only make confession
Electric module and other function components are mixed in together, greatly reduce shadow of the power supply module to high speed signal in plate
Ring, also sufficiently make use of the space on the vertical direction of a groove position thickness, the space that can be not take up in length, Neng Gouda
To higher integrated level so that this FPGA that the application provides accelerates board to meet the height of half length half and a groove position thickness mark
Standard, can a defined total length overall height, groove position thickness calibration groove position in, be merely able to set one by prior art
Old-fashioned FPGA accelerator cards snap into this FPGA that two the application can be set to provide and accelerate board., groove position can not increased
In the case of so that FPGA hardware acceleration effect, which reaches, to be increased exponentially, and is calculated more data volumes and is possessed faster calculating
Speed.
As for specifically how to be arranged on power supply subcard 200 is vertical in master card 100, the embodiment of the present application combines specific
Actual conditions propose two kinds of mounting means, are installed and two kinds fixed of installation to be dismountable, it is of course also possible to exist it is other more
Add the mounting means for meeting special occasions, two kinds merely just proposed for most common scene are the most commonly used and are easily understood
Scheme for reference, herein and be not specifically limited.
Optionally, power supply subcard 200 is removably vertically mounted in master card 100.
Optionally, connector is provided with master card 100, the slot of the first predetermined number is provided with connector；Power supply subcard
200 are provided with and slot quantity the first contact pin of identical, the insertion slot of the first pins normal.
That is, a special connector is provided with master card 100, the connector is used to be connected with power supply subcard 200,
So that power supply subcard 200 is realized by the connector realizes predetermined current and default electricity to each function component in master card 100
The supply of pressure so that each Functional Unit proper device operation in master card 100.Specifically, can by the way of stitch and slot,
The slot of predetermined number is provided with the connector, the corresponding contact pin that identical quantity is provided with power supply subcard 200, is passed through
Slot corresponding to the insertion of each contact pin is realized into good, firm connection；Can also using it is other it is feasible by the way of, do not do
It is specific to limit, it is only necessary to can to realize and open unload power supply subcard 200 is installed in master card 100, it can realize stabilization
Power supply.Slot does not do specific amount of restriction, should regard actual particular situation knot as with the quantity of contact pin being also
Close various influence factors and require to carry out most suitable selection.
A dismountable maximum benefit is exactly that modular design to lead to not continue in a certain partial destruction
In use, only needing worse corresponding part, O＆M cost can be effectively saved.
Optionally, power supply subcard 200 is welded in master card 100.
Optionally, the hole of the second predetermined number is provided with master card 100；Power supply subcard 200 is provided with and pore quantity phase
The second same contact pin, the second pins normal are welded in hole.
And fixed mounting means is used, the special connector for being used to detachably install need not be just set, most simply
It is to use welded type, i.e., the through hole of predetermined number is provided with master card 100, by the stitch of identical quantity on power supply subcard 200
In through hole corresponding to insertion, and both firm weldings are connected with this to realize.This mode opens what is unloaded due to having abandoned
Modularized design, it can further improve integrated level, reduce manufacturing cost.
Optionally, FPGA accelerates the size of board to meet a half high half long and groove position thickness calibration.
Optionally, it is specially height 68mm, length 167mm, thickness 21mm that FPGA, which accelerates the size of board,.
Standard is specified in server cluster：Total length 334mm, total length 176mm, and using 21mm as a thickness list
The groove position size of position.New FPGA accelerator cards card provided herein by designing described above so that it is high that it meets half
68mm, half long 167mm and 21mm thickness calibration, can be in the space that can only originally set an old-fashioned FPGA to accelerate board
It is interior to set two new FPGA to accelerate board, can be in the case where not increasing groove position so that FPGA hardware acceleration effect reaches
To increasing exponentially, calculate more data volumes and possess faster calculating speed.
Optionally, module of powering is specially six road power supplys.
Optionally, fpga chip is specially the GX 10AX115H3F34E2SG chips of Arria 10.
Present invention also provides a kind of server cluster, the FPGA that the server cluster is provided with as described in above-mentioned content adds
Fast board.
Based on above-mentioned technical proposal, by the power supply subcard where the module that is split as powering by existing FPGA acceleration boards with
And the master card of fpga chip and other function components is integrated with, and the groove position thickness of itself is made full use of, power supply subcard is hung down
Directly it is arranged in master card so that power supply subcard is not take up the length that the FPGA accelerates board.Provide that a kind of integrated level is higher, accounts for
Accelerate board with the smaller FPGA of groove bit space, more FPGA accelerator cards can be set in same amount of service tank position
Card, arithmetic speed is faster.
Fig. 3, a kind of structured flowchart for server cluster that Fig. 3 is provided by the embodiment of the present application are referred to below.
As shown in figure 3, under the premise of the dimensional standard of number of slots amount and groove position is immovable, the embodiment of the present application can be
One total length overall height, thickness calibration groove position in set two new FPGA that such as above-mentioned contents provide to accelerate boards, compared with
The present situation that can only set one in a groove position in the prior art, by significant change so that FPGA accelerates the integrated of board
Du Genggao, space-consuming is smaller, groove position it is limited, groove position size is not transformed in itself when, can be in same server
Set the FPGA of twice prior art quantity to accelerate board in cluster, bring faster arithmetic speed.Because situation is complicated,
It can not enumerate and be illustrated, those skilled in the art should be able to recognize that the basic skills principle that more the application provides combines
Actual conditions may have many examples, should be in the protection domain of the application in the case where not paying enough creative works
It is interior.Each embodiment is described by the way of progressive in specification, and what each embodiment stressed is and other embodiment
Difference, between each embodiment identical similar portion mutually referring to.
Specific case used herein is set forth to the principle and embodiment of the application, and above example is said
It is bright to be only intended to help and understand the present processes and its core concept.It should be pointed out that the ordinary skill for the art
For personnel, on the premise of the application principle is not departed from, some improvement and modification, these improvement can also be carried out to the application
Also fallen into modification in the application scope of the claims.
Claims (10)
1. a kind of FPGA accelerates board, it is characterised in that including：
It is integrated with the master card of fpga chip and each function component；
It is vertically connected with the master card, predeterminated voltage and the electricity of predetermined current is provided for the master card using integrated power supply module
Source subcard.
2. FPGA according to claim 1 accelerates board, it is characterised in that the right angle setting of the power supply daughter cards removable
In the master card.
3. FPGA according to claim 2 accelerates board, it is characterised in that connector is provided with the master card, it is described
The slot of the first predetermined number is provided with connector；The power supply subcard is provided with to be inserted with the slot quantity identical first
Pin, the insertion slot of first pins normal.
4. FPGA according to claim 1 accelerates board, it is characterised in that the power supply subcard is welded on the master card
On.
5. FPGA according to claim 4 accelerates board, it is characterised in that the second predetermined number is provided with the master card
Hole；The power supply subcard is provided with is welded on institute with described hole quantity the second contact pin of identical, second pins normal
State in hole.
6. the FPGA according to any one of claim 1 to 5 accelerates board, it is characterised in that the FPGA accelerates board
Size meets a half high half long and groove position thickness calibration.
7. FPGA according to claim 6 accelerates board, it is characterised in that the FPGA accelerates the size of board to be specially
Height 68mm, length 167mm, thickness 21mm.
8. FPGA according to claim 7 accelerates board, it is characterised in that the power supply module is specially six road power supplys.
9. FPGA according to claim 8 accelerates board, it is characterised in that the fpga chip is specially Arria 10
GX 10AX115H3F34E2SG chips.
10. a kind of server cluster, it is characterised in that set just like the FPGA accelerator cards described in any one of claim 1 to 9
Card.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720866367.0U CN207115406U (en) | 2017-07-17 | 2017-07-17 | A kind of FPGA accelerates board and server cluster |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720866367.0U CN207115406U (en) | 2017-07-17 | 2017-07-17 | A kind of FPGA accelerates board and server cluster |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207115406U true CN207115406U (en) | 2018-03-16 |
Family
ID=61583856
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| CN201720866367.0U Expired - Fee Related CN207115406U (en) | 2017-07-17 | 2017-07-17 | A kind of FPGA accelerates board and server cluster |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108845658A (en) * | 2018-06-01 | 2018-11-20 | 曙光信息产业(北京)有限公司 | Power supply power supply plate for liquid cooled server |
| CN109062858A (en) * | 2018-08-01 | 2018-12-21 | 郑州云海信息技术有限公司 | A kind of FPGA accelerator card based on Xilinx XCVU37P chip |
| CN114546062A (en) * | 2022-02-18 | 2022-05-27 | 苏州浪潮智能科技有限公司 | Board card slot connection element installation control method and device and storage medium |
-
2017
- 2017-07-17 CN CN201720866367.0U patent/CN207115406U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108845658A (en) * | 2018-06-01 | 2018-11-20 | 曙光信息产业(北京)有限公司 | Power supply power supply plate for liquid cooled server |
| CN109062858A (en) * | 2018-08-01 | 2018-12-21 | 郑州云海信息技术有限公司 | A kind of FPGA accelerator card based on Xilinx XCVU37P chip |
| CN114546062A (en) * | 2022-02-18 | 2022-05-27 | 苏州浪潮智能科技有限公司 | Board card slot connection element installation control method and device and storage medium |
| CN114546062B (en) * | 2022-02-18 | 2023-07-14 | 苏州浪潮智能科技有限公司 | Board card slot joint element installation control method, device and storage medium |
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Granted publication date: 20180316 Termination date: 20200717 |