CN115048889B - Asynchronous path extraction method and system based on back-end time sequence convergence simulation - Google Patents
Asynchronous path extraction method and system based on back-end time sequence convergence simulation Download PDFInfo
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Abstract
The invention belongs to the technical field of simulation environment optimization, and particularly relates to an asynchronous path extraction method and system based on back-end time sequence convergence simulation, which comprises the steps of extracting an asynchronous path and determining maximum delay.
Description
Technical Field
The invention belongs to the technical field of simulation environment optimization, and particularly relates to an asynchronous path extraction method and system based on back-end time sequence convergence simulation.
Background
ASIC timing constraints mainly include period constraints (FFS to FFS, i.e., paths between flip-flops to flip-flops) and offset constraints (IPAD to FFS, FFS to OPAD, i.e., paths from input port to first stage flip-flop, paths from last stage flip-flop to output port) and static path constraints, so that the design meets the timing requirements;
the general strategy of adding timing constraint is TO add global constraint, define all the designed packet additional period constraint, then input and output PAD additional offset constraint, and add constraint TO PAD TO PAD path of full combinational logic; secondly, adding special constraints to the fast exceptional path and the slow exceptional path, wherein the special constraints comprise a speed-per-hour exceptional path, a multi-cycle path and other special paths, and the constraint on the maximum delay of the asynchronous path is particularly important for ensuring the functional performance of the asynchronous path;
the multiple modules of a chip can be in the same clock domain (single clock domain) or asynchronous clock domain (multiple clock domains), and due to the existence of the multiple clock domains, the problem of cross-clock domain processing of signals, namely various asynchronous circuits to be researched, is caused; for signal processing of multiple clock domains, a sending clock domain (a source clock domain) reaches a receiving clock domain (a destination clock domain) through a synchronous circuit (a synchronizer), the process can be called as signal cross asynchronization, and a circuit structure is called as an asynchronous circuit; the basic meaning of the asynchronous clock async is that the asynchronous clock async is specific to clocks, and the asynchronous clock async means that the phase between the clocks is uncertain; asynchronous circuits are sometimes also referred to as clockless (clockless) or self-timed (self-timed) circuits, which, as the name implies, are circuits without a global clock; in an asynchronous circuit, everyone does not have a unified clock, and a front stage and a back stage directly inform a counterpart whether data can be received or not; specifically, the correctness of data transmission is ensured by directly sending handshake signals through front and back stages;
from the functional point of view, compared with the design of various functions in a synchronous system, the design can be ensured through eda verification, and the function of processing the cross-clock domain signal transmission by the asynchronous interaction module cannot test the correctness of the function through an rtl simulation case; in physical implementation, since the asynchronous circuit clock has no fixed phase relationship, the asynchronous circuit clock cannot restrict path routing through the clock relationship like a synchronous circuit, and the asynchronous circuit clock also needs to be specially treated; the particularity determines that the asynchronous circuit needs designers to have more correct and perfect understanding on the structural function of the asynchronous circuit, so that the requirements can be identified in real time at the rtl stage, review work is done, the correctness of the design is inspected through the cdc, and reasonable constraint requirements are put forward for rear-end physical implementers;
it is obvious that the back-end personnel can not use clock to restrict the asynchronous circuit under the condition of no synchronous clock, and the use of virtual clock is not feasible; the control circuit of the asynchronous circuit is complex, and the direct use of a virtual clock means the use of simple constraint from an input port to an output port, however, the critical path obtained by the constraint is often far from the actual critical path; setting a more refined path constraint with set _ max _ delay has better results;
generally, an asynchronous circuit cannot be synthesized by a synthesis tool of a synchronous circuit, and in order to ensure the function and performance of an asynchronous path, the maximum delay max _ delay of the asynchronous path needs to be constrained in a synthesis constraint file SDC, so that the extraction method of the asynchronous circuit is particularly important;
more specifically, as shown in fig. 4, the asynchronous circuit is mainly a combinational logic circuit for generating read/write control signal pulses of an address decoder, FIFO or RAM, the logic output of which is independent of any clock signal, and glitches generated by the decoded output can be monitored in general. Asynchronous circuits cannot be defined according to whether clocks are homologous or not, and no definite phase relationship between clocks is the only criterion. The input clocks of the two triggers belong to different asynchronous clocks; CLK1 is input to the sending register, CLK2 is input to the receiving register, and CLK1 and CLK2 belong to asynchronous clocks; the asynchronous nature of its clock does not provide a deterministic relationship between data switching and clock edges. The data transmission of the asynchronous path can time the propagation time between two triggers working at different working frequencies, and the extraction of the asynchronous path plays a crucial role;
to sum up, the prior art has the problem of constraining the maximum delay of the asynchronous path under the premise of ensuring the function and performance of the asynchronous path in the backend timing sequence convergence simulation environment.
Disclosure of Invention
The invention provides an asynchronous path extraction method and system based on back-end time sequence convergence simulation, which aim to solve the problem that the prior art has the constraint on the maximum delay of an asynchronous path in the back-end time sequence convergence simulation environment on the premise of ensuring the function and performance of the asynchronous path.
The technical problem solved by the invention is realized by adopting the following technical scheme: the asynchronous path extraction method based on the back-end time sequence convergence simulation comprises the following steps:
extracting time of pt in the static time sequence analysis stage:
and (3) extracting an asynchronous path: extracting an asynchronous time sequence path between an asynchronous sending register and an asynchronous receiving register based on a test case of an asynchronous interactive simulation circuit;
determining the maximum time delay: and determining the maximum delay period of the asynchronous time sequence path between the asynchronous sending register and the asynchronous receiving register based on the asynchronous time sequence path constraint rule.
Further, the extracting the asynchronous path further comprises:
extracting an asynchronous sending register: extracting any asynchronous sending register in a test case of the asynchronous interactive simulation circuit, and determining the asynchronous sending register as an asynchronous sending register;
extracting an asynchronous receiving register: based on the asynchronous sending register, determining any asynchronous receiving register according to the connection relation between the output port of the asynchronous sending register and the asynchronous receiving register, and determining the asynchronous receiving register as the asynchronous receiving register;
the determination is as follows: and determining the connection relation of the asynchronous sending register and the asynchronous receiving register as an asynchronous timing path.
Further, the determining the maximum delay further includes:
and determining the minimum clock period of the asynchronous time sequence path based on the asynchronous time sequence path constraint rule in the time sequence constraint file SDC, and determining the minimum clock period as the maximum delay period.
Further, the extracting the asynchronous send register further comprises:
first fetch asynchronous send register loop:
establishing a whole register set comprising all register units;
converting all register sets into asynchronous sending register sets according to the fan-out relation characteristics of the asynchronous sending registers;
any asynchronous sending register in the asynchronous sending register set is extracted and determined to be an asynchronous sending register.
Further, the extracting asynchronous send register further comprises:
if the connection relation does not exist between the registers, closing an asynchronous time sequence path of an unconstrained rule in the time sequence constraint file SDC;
and if the connection relation exists between the registers but the constraint rule does not exist, opening the asynchronous time sequence path of the unconstrained rule in the time sequence constraint file SDC.
Further, the extracting asynchronous receiving register further comprises:
second fetch asynchronous receive register cycle:
based on the asynchronous send register;
converting the output relation of all external output pins of the asynchronous transmitting register into an asynchronous receiving register set through the connection of a D input port of a Q output port;
and extracting any asynchronous receiving register in the asynchronous receiving register set and determining the asynchronous receiving register.
Further, the determining as an asynchronous path further includes:
the third determination is an asynchronous path loop:
based on the determined asynchronous sending register and the determined asynchronous receiving register, acquiring an asynchronous time sequence path from an output port Q end of the asynchronous sending register to an input port D end of the asynchronous receiving register;
further, the determining the maximum delay further includes:
the method comprises the steps of obtaining and comparing the clock period of an asynchronous sending register and the clock period of an asynchronous receiving register based on an asynchronous time sequence path, comparing the clock period of the asynchronous sending register and the clock period of the asynchronous receiving register through a clock period comparison function, determining the minimum clock period of the asynchronous sending register and the clock period of the asynchronous receiving register, and determining the maximum time delay from an output port Q end of the asynchronous sending register to an input port D end of the asynchronous receiving register as the minimum clock period of the asynchronous sending register and the clock period of the asynchronous receiving register.
Further, the clock period comparison function is:
the DelaymaxIs the maximum delay period;
the DelaystartClock cycles for the asynchronous transmit register;
the DelayendIs the clock cycle of the asynchronous receive register.
Meanwhile, the invention also provides an asynchronous path extraction system based on the back-end time sequence convergence simulation, and the asynchronous path extraction method based on the back-end time sequence convergence simulation is executed, and the system comprises the following steps: extracting an asynchronous path module and determining a maximum delay module;
and an asynchronous path extraction module: for extracting an asynchronous path;
a maximum delay determining module: for determining a maximum delay;
the asynchronous path extracting module comprises an asynchronous sending register extracting submodule, an asynchronous receiving register extracting submodule and an asynchronous path determining submodule;
extracting an asynchronous sending register submodule: for extracting the asynchronous send register;
extracting an asynchronous receiving register submodule: for extracting an asynchronous receive register;
determining as an asynchronous path submodule: for determining as an asynchronous path;
the maximum delay determining module comprises a maximum delay determining core submodule;
determining a maximum delay core submodule: for determining the maximum delay kernel.
The beneficial technical effects are as follows:
the patent adopts the extraction opportunity at the static time sequence analysis stage pt: and (3) extracting an asynchronous path: extracting an asynchronous time sequence path between an asynchronous sending register and an asynchronous receiving register based on a test case of the asynchronous interactive simulation circuit; determining the maximum time delay: the maximum delay period of the asynchronous time sequence path between the asynchronous sending register and the asynchronous receiving register is determined based on the asynchronous time sequence path constraint rule, and due to the complexity of the asynchronous circuit, designers need to have more correct and complete knowledge on the structural function of the asynchronous circuit, and reasonable constraint requirements are provided for rear-end physical implementation personnel in all aspects. In order to avoid that when an asynchronous path is constrained, partial paths with constraint requirements are omitted so as to influence the function and the performance of the asynchronous path, the extraction method of the asynchronous circuit is that when the SDC is generated at a pt stage, all internal asynchronous paths are automatically analyzed and extracted, and the maximum delay (max _ delay) of the asynchronous paths is constrained so as to be used for carrying out sequential inspection and maintenance on the subsequent asynchronous paths at a rear end, therefore, the asynchronous paths automatically extracted at the pt stage and the maximum delay (max _ delay) of the asynchronous paths are automatically constrained, the characteristic that the path delays of two asynchronous clock domains are still constrained is ensured, the more detailed path constraint is set to a certain extent, all asynchronous paths are extracted in a comprehensive constraint file SDC by using a tool, and the maximum delay of the asynchronous paths is constrained so as to ensure the function and the performance of the asynchronous paths.
Drawings
FIG. 1 is a method flow diagram of the asynchronous path extraction method of the present invention;
FIG. 2 is a flow chart of a method for extracting an asynchronous path according to the asynchronous path extraction method of the present invention;
FIG. 3 is a flow chart of a method for determining maximum delay for the asynchronous path extraction method of the present invention;
fig. 4 is a diagram of a prior art asynchronous circuit configuration.
Detailed Description
The invention is further described below with reference to the accompanying drawings:
in the figure:
s101, extracting opportunity of pt at a static time sequence analysis stage;
s102, extracting an asynchronous path;
s1021, extracting an asynchronous time sequence path between an asynchronous sending register and an asynchronous receiving register based on a test case of an asynchronous interactive simulation circuit;
s103, determining the maximum delay;
s1031, determining the maximum delay period of an asynchronous time sequence path between an asynchronous sending register and an asynchronous receiving register based on an asynchronous time sequence path constraint rule;
s201, extracting an asynchronous sending register;
s2011-any asynchronous sending register in the test case of the asynchronous interactive simulation circuit is extracted and determined as an asynchronous sending register;
s202, extracting an asynchronous receiving register;
s2021-based on the asynchronous sending register, determining any asynchronous receiving register according to the connection relation between the output port of the asynchronous sending register and the asynchronous receiving register, and determining the asynchronous sending register as an asynchronous receiving register;
s203, determining as an asynchronous path;
s2031, determining the connection relation between the asynchronous sending register and the asynchronous receiving register as an asynchronous time sequence path;
s3031-based on asynchronous time sequence path constraint rules in the time sequence constraint file SDC;
s3032-determining the minimum clock period of the asynchronous timing path;
s3033, determining the minimum clock period as the maximum delay period;
the embodiment is as follows:
in this embodiment: as shown in fig. 1, the asynchronous path extraction method based on the back-end timing closure simulation includes:
at an extraction opportunity S101 of the static timing analysis stage pt:
extracting an asynchronous path S102: based on the test case of the asynchronous interactive simulation circuit, extracting an asynchronous time sequence path S1021 between an asynchronous sending register and an asynchronous receiving register;
determining the maximum delay S103: and determining the maximum delay period S1031 of the asynchronous time sequence path between the asynchronous sending register and the asynchronous receiving register based on the asynchronous time sequence path constraint rule.
Due to the adoption of the extraction opportunity in the static timing analysis stage pt: extracting an asynchronous path: extracting an asynchronous time sequence path between an asynchronous sending register and an asynchronous receiving register based on a test case of an asynchronous interactive simulation circuit; determining the maximum time delay: the maximum delay period of the asynchronous time sequence path between the asynchronous sending register and the asynchronous receiving register is determined based on the asynchronous time sequence path constraint rule, and due to the complexity of the asynchronous circuit, designers need to have more correct and complete knowledge on the structural function of the asynchronous circuit, and reasonable constraint requirements are provided for rear-end physical implementation personnel in all aspects. In order to avoid that when an asynchronous path is constrained, partial paths with constraint requirements are omitted so as to influence the function and the performance of the asynchronous path, the extraction method of the asynchronous circuit is that when the SDC is generated at a pt stage, all internal asynchronous paths are automatically analyzed and extracted, and the maximum delay (max _ delay) of the asynchronous paths is constrained so as to be used for carrying out sequential inspection and maintenance on the subsequent asynchronous paths at a rear end, therefore, the asynchronous paths automatically extracted at the pt stage and the maximum delay (max _ delay) of the asynchronous paths are automatically constrained, the characteristic that the path delays of two asynchronous clock domains are still constrained is ensured, the more detailed path constraint is set to a certain extent, all asynchronous paths are extracted in a comprehensive constraint file SDC by using a tool, and the maximum delay of the asynchronous paths is constrained so as to ensure the function and the performance of the asynchronous paths.
As shown in fig. 2, the extracting asynchronous path S102 further includes:
fetch asynchronous send register S201: extracting any asynchronous sending register in a test case of the asynchronous interactive simulation circuit, and determining the asynchronous sending register as an asynchronous sending register S2011;
fetch asynchronous receive register S202: based on the asynchronous sending register, determining any asynchronous receiving register according to the connection relation between the output port of the asynchronous sending register and the asynchronous receiving register, and determining the asynchronous sending register as an asynchronous receiving register S2021;
determined as asynchronous path S203: the connection relationship of the asynchronous transmission register and the asynchronous reception register is determined as an asynchronous timing path S2031.
The adoption of the extraction asynchronous path further comprises the following steps: extracting an asynchronous sending register: extracting any asynchronous sending register in a test case of the asynchronous interactive simulation circuit, and determining the asynchronous sending register as an asynchronous sending register; extracting an asynchronous receiving register: based on the asynchronous sending register, determining any asynchronous receiving register according to the connection relation between the output port of the asynchronous sending register and the asynchronous receiving register, and determining the asynchronous receiving register as an asynchronous receiving register; the determination is as an asynchronous path: the connection relation of the asynchronous sending register and the asynchronous receiving register is determined as an asynchronous time sequence path, in the process of extracting the asynchronous path, the asynchronous sending register, the asynchronous receiving register and the asynchronous receiving register are further extracted and determined, the asynchronous sending register is determined through the connection relation of the output port and the asynchronous receiving register after the asynchronous sending register is determined, the asynchronous receiving register is determined after the asynchronous sending register and the asynchronous receiving register are determined, the connection relation of the asynchronous sending register and the asynchronous receiving register is determined as the asynchronous time sequence path, the asynchronous circuit needs a designer to know the structure function more correctly and perfectly due to the particularity of the asynchronous circuit, then reasonable constraint requirements are put forward to back-end physical implementers, and the paths with constraint requirements are found for the back-end personnel to carry out constraint maximum delay (max _ delay) so as to prepare early.
As shown in fig. 3, the determining the maximum delay S103 further includes:
based on the asynchronous timing path constraint rule S3031 in the timing constraint file SDC, the minimum clock period S3032 of the asynchronous timing path is determined, and the minimum clock period is determined as the maximum delay period S3033.
The determining the maximum delay time further comprises: the method comprises the steps of determining a minimum clock cycle of an asynchronous time sequence path based on an asynchronous time sequence path constraint rule in a time sequence constraint file SDC, determining the minimum clock cycle as a maximum delay cycle, wherein in the process of determining the maximum delay, further, a static time sequence analysis stage pt generates the time sequence constraint file SDC, the time sequence constraint file SDC also comprises the asynchronous time sequence path constraint rule, finding the asynchronous time sequence path by extracting the asynchronous path, the asynchronous time sequence path has the minimum clock cycle, and the minimum clock cycle is determined as the maximum delay cycle, so that the maximum delay (max _ delay) of the asynchronous path is constrained by the automatically extracted asynchronous path, the characteristic that the path delays of two asynchronous clock domains are still constrained is ensured, more detailed path constraint is set to a certain extent, and a tool is used for extracting all the asynchronous paths to ensure the functions and performances of the asynchronous path.
The fetch asynchronous transmit register S201 further includes:
first fetch asynchronous send register cycle:
establishing a whole register set comprising all register units;
converting all register sets into asynchronous sending register sets according to the fan-out relation characteristics of the asynchronous sending registers;
any asynchronous sending register in the asynchronous sending register set is extracted and determined to be an asynchronous sending register.
The adoption of the extraction asynchronous sending register further comprises the following steps: first fetch asynchronous send register loop: establishing a whole register set comprising all register units; converting all register sets into asynchronous sending register sets according to the fan-out relation characteristics of the asynchronous sending registers; extracting any asynchronous sending register in the asynchronous sending register set and determining the asynchronous sending register as the asynchronous sending register, wherein the process of extracting the asynchronous sending register is as follows: after SDC constraint is generated at pt stage, acquiring all register collections including all cells related to instance (namely register DFF) in current design, searching the cells related to the current instance (namely register DFF) layer by layer, and transmitting the collection to other variables or commands through screening and filtering matching results; and after all the register sets (collections) are acquired, returning object names of the specified sets, setting the object names of all the register sets as all _ regs, and after all the register sets are acquired, converting all the register sets (all _ regs) into an asynchronous transmission register start list.
The extracting asynchronous transmission register S201 further includes:
if the connection relation does not exist among the registers, closing an asynchronous time sequence path of an unconstrained rule in the time sequence constraint file SDC;
and if the connection relation exists between the registers but the constraint rule does not exist, opening an asynchronous time sequence path of the unconstrained rule in the time sequence constraint file SDC.
The adoption of the extraction asynchronous sending register further comprises the following steps: if the connection relation does not exist between the registers, closing an asynchronous time sequence path of an unconstrained rule in the time sequence constraint file SDC; if the connection relation exists between the registers but the constraint rule does not exist, opening an asynchronous time sequence path of the unconstrained rule in the SDC, and generally, in order to better reduce the running time of a tool, closing an option reporting the unconstrained path in the pt process because the unconstrained path exists in a clock domain of the asynchronous path; now, for extracting the asynchronous path subsequently, the first work is to open the setting in the pt and inform the pt analysis that an unconstrained path exists in the asynchronous clock domain to be reported, and to know the reported unconstrained asynchronous path, so that the subsequent analysis is performed on the asynchronous path.
The extracting asynchronous receiving register S202 further includes:
second fetch asynchronous receive register cycle:
based on the asynchronous send register;
converting the output relation of all external output pins of the asynchronous transmitting register into an asynchronous receiving register set through the connection of a D input port of a Q output port;
any asynchronous receiving register in the asynchronous receiving register set is extracted and determined as an asynchronous receiving register.
The adoption of the extraction asynchronous receiving register further comprises the following steps: second fetch asynchronous receive register cycle: based on the asynchronous send register; converting the output relation of all external output pins of the asynchronous transmitting register into an asynchronous receiving register set through the connection of a D input port of a Q output port; any asynchronous receiving register in the asynchronous receiving register set is extracted and determined as an asynchronous receiving register, and in the process of extracting the asynchronous receiving register, all register set (all _ regs) lists as sending registers of an asynchronous path enter a cycle to be analyzed sequentially; starting to analyze all fan-out all _ fanouts at the Q end of an output port of each register when each register enters the inside of the circulation; the default report of fanout is to be the input pin of a downstream cell and the output pin of the cell (which should be the output pin having a relative relationship with the input pin of fanout), and is sent to the D end or design output port of a lower-level DFF; analyzing all _ fanout of the all _ fanout and searching for fanout of the all _ fanout; the cell displaying the fanout, the register (DFF) meeting the filtering condition, the fanout register of each register entering the circulation of the start list and the register entering the circulation form an asynchronous path; it specifies the object name satisfying the condition register set, the set of the sending register of the asynchronous path is start, each sending register may correspond to one or more receiving registers of the asynchronous path, and now the object name of the fanout receiving register set of each sending register is set as end _ list.
The determining as the asynchronous path S203 further includes:
the third determination is an asynchronous path loop:
based on the determined asynchronous transmitting register and the determined asynchronous receiving register, acquiring an asynchronous time sequence path from an output port Q end of the asynchronous transmitting register to an input port D end of the asynchronous receiving register;
the adoption of the determination as an asynchronous path further comprises: the third determination is an asynchronous path loop: based on the determined asynchronous transmitting register and the determined asynchronous receiving register, acquiring an asynchronous time sequence path from an output port Q end of the asynchronous transmitting register to an input port D end of the asynchronous receiving register; in the process of determining as an asynchronous path, each receiving register of the fanout of each sending register sequentially enters the inside of a loop, all receiving register sets (end _ list) are converted into an end list, and the end _ list serving as the receiving registers of the asynchronous path sequentially enters the loop to be analyzed; after the receiving register enters circulation in sequence, some specific paths are extracted and found according to specified conditions, problems in design can be quickly located by using some attributes in return values of the specific paths, and then a special asynchronous path is extracted to obtain a time sequence path from an output port Q end of the sending register to an input port D end of the receiving register.
The determining the maximum delay S103 further includes:
the method comprises the steps of obtaining and comparing the clock period of an asynchronous sending register and the clock period of an asynchronous receiving register based on an asynchronous time sequence path, comparing the clock period of the asynchronous sending register and the clock period of the asynchronous receiving register through a clock period comparison function, determining the minimum clock period of the asynchronous sending register and the clock period of the asynchronous receiving register, and determining the maximum time delay from an output port Q end of the asynchronous sending register to an input port D end of the asynchronous receiving register as the minimum clock period of the asynchronous sending register and the clock period of the asynchronous receiving register.
The determining the maximum delay further comprises: acquiring and comparing a clock period of an asynchronous transmitting register and a clock period of an asynchronous receiving register based on an asynchronous time sequence path, comparing the clock period of the asynchronous transmitting register and the clock period of the asynchronous receiving register through a clock period comparison function, determining the minimum clock period of the asynchronous transmitting register and the asynchronous receiving register, determining the maximum time delay between an output port Q end of the asynchronous transmitting register and an input port D end of the asynchronous receiving register as the minimum clock period of the asynchronous transmitting register and the clock period of the asynchronous receiving register, and acquiring the clock period of the transmitting register and the clock period of the receiving register of the asynchronous path timing _ path due to the fact that the asynchronous path timing _ path is extracted in the circulating process; according to the constraint rule in the integrated constraint file SDC, the data transmission of the asynchronous path may time the propagation time between two flip-flops that operate at different operating frequencies, and in the clock cycle of the sending register and the clock cycle of the receiving register, the minimum cycle min _ clk is selected for setting the maximum delay (max _ delay), so far, the extracted constraint of the asynchronous path is completed, where the maximum time delay from the output port Q end of the sending register to the input port D end of the receiving register is the minimum cycle in the clock cycle of the sending register and the clock cycle of the receiving register.
The clock period comparison function is:
the DelaymaxIs the maximum delay period;
the DelaystartClock cycles for the asynchronous transmit register;
the DelayendIs the clock cycle of the asynchronous receive register.
The clock period comparison function is adopted as follows:
the constraint relation of the asynchronous path is as follows: set _ max _ delay [ expr $ min _ clk _ [ [ 1 ] ], from [ get _ pins $ start/Q ] ], to [ get _ pins $ end/D ]; wherein the set _ max _ delay is a maximum delay period; from [ get _ pins $ start/Q ] - [ get _ pins $ end/D ] is the clock cycle of the asynchronous sending register and the clock cycle of the asynchronous receiving register, the smaller cycle in the comparison is set as the maximum delay (max _ delay) through the comparison of the clock cycle of the asynchronous sending register and the clock cycle of the asynchronous receiving register, then the pt tool will automatically complete the cycle according to the previous input command, analyze and complete the end set corresponding to each sending register in the start set list, extract each asynchronous path in the project, output the constraint of the asynchronous path and then complete the cycle, and complete the extraction of the asynchronous path.
Meanwhile, the invention also provides an asynchronous path extraction system based on the back end time sequence convergence simulation, and the asynchronous path extraction method based on the back end time sequence convergence simulation is executed, and the system comprises the following steps: extracting an asynchronous path module and determining a maximum delay module;
and an asynchronous path extraction module: for extracting an asynchronous path; s102
A maximum delay determining module: for determining a maximum delay; s103
The asynchronous path extracting module comprises an asynchronous sending register extracting submodule, an asynchronous receiving register extracting submodule and an asynchronous path determining submodule;
extracting an asynchronous sending register submodule: for extracting the asynchronous send register; s201
Extracting an asynchronous receiving register submodule: for extracting an asynchronous receive register; s202
Determining as an asynchronous path submodule: for determining as an asynchronous path; s203
The module for determining the maximum delay comprises a module for determining the maximum delay core;
determining a maximum delay core submodule: for determining the maximum delay S103 kernel.
Meanwhile, the invention also provides an asynchronous path extraction system based on rear end time sequence convergence simulation, which comprises the following steps: extracting an asynchronous path module and determining a maximum delay module; and an asynchronous path extraction module: the asynchronous path extraction method is realized; a maximum delay determining module: the maximum delay is determined by the asynchronous path extraction method; the asynchronous path extracting module comprises an asynchronous transmitting register extracting submodule, an asynchronous receiving register extracting submodule and an asynchronous path determining submodule; extracting an asynchronous sending register submodule: the extraction asynchronous sending register for extracting the asynchronous path is realized; extracting an asynchronous receiving register submodule: the extraction asynchronous receiving register for extracting the asynchronous path is realized; determining as an asynchronous path submodule: the determination that the extracted asynchronous path is an asynchronous path is realized; the module for determining the maximum delay comprises a module for determining the maximum delay core; determining a maximum delay core submodule: the system constructed based on the method can realize the extraction of all asynchronous circuits in a logic structure by a tool without a back-end person going deep into a code to search for the path of the asynchronous circuit, thereby ensuring the convenient operability of subsequent work, ensuring the characteristic that the path delay of two asynchronous clock domains is still restrained, and realizing setting of more detailed path restraint to a certain extent; meanwhile, the maximum delay (max _ delay) is constrained after the asynchronous circuit extracts to ensure the function and the performance of the asynchronous paths, ensure the correct propagation of signals among the asynchronous paths in the design and ensure the functional correctness of the design.
The first embodiment is as follows:
and (3) extracting an asynchronous path:
extracting an asynchronous sending register:
(1) After SDC constraint is generated in the pt stage, all register collections are obtained;
(2) Acquiring all register collections, creating a collection (collection) by using a basic command get _ cells, wherein the collection comprises all cells related to an instance (namely, a register DFF) in the current design, and searching the cells related to the current instance (namely, the register DFF) layer by using a command-hierarchical;
(3) The command-filter expression is used for screening the collection and filtering the matching result, and the collection can be transmitted to other variables or commands;
(4) After all register sets (collections) are acquired, object names of specified sets need to be returned by using a command get _ object _ name, and the object names of all register sets are set to be all _ regs;
(5) After all register sets are acquired, foreach is used, which circulates a list in a general form, and each element in the list is separated by a blank space; the method comprises the steps that Foreach start $ all _ regs, all register sets (all _ regs) are converted into start lists, and the start analysis of a loop is carried out sequentially by taking all register set (all _ regs) lists as sending registers of an asynchronous path;
first fetch asynchronous send register cycle:
1. starting to analyze all _ fanout at the Q end of an output port of each register when each register enters the inside of the circulation; the default report of fanout is to be the input pin of a downstream cell and the output pin of the cell (which should be the output pin having a relative relationship with the input pin of fanout) until the D end or design output port of a lower DFF;
2. when analyzing all _ fanout, setting a command-flat to ignore the boundary of the Hier, and only searching the fanout inside the Hier when not specified; setting a command-only _ cells to show that only the cell of fanout is displayed, but not the port of fanout, and only displaying the pin/port of the port load when fanout is searched when the fanout is not specified; setting a command-endipoints _ only to indicate that only the all _ fanout output port or the D port of the DFF is reported;
3. the register (DFF) meeting the filter _ collection filtering condition is a fanout register of each register entering the loop of the start list, and forms an asynchronous path with the register entering the loop; the method also needs to use a command get _ object _ name to specify an object name meeting the condition register set, and the set of the sending registers of the asynchronous path is start;
second fetch asynchronous receive register cycle:
(1) Each send register may correspond to one or more receive registers of the asynchronous path, now setting the fanout receive register set object name of each send register to end _ list;
(2) Sequentially entering the interior of a cycle for each receiving register of the fanout of each sending register, converting all receiving register sets (end _ list) into an end list by using a forward end $ end _ list command, and sequentially entering the cycle for analysis by taking all receiving register sets (end _ list) as receiving registers of an asynchronous path;
(3) After the receiving registers sequentially enter circulation, according to a use command get _ timing _ paths, some specific paths can be found according to specified conditions, and some attributes in return values of the specific paths can be used for quickly positioning problems in design; extracting a special asynchronous path by using a command get _ timing _ paths-from $ start/Q _ -to $ end/D _, wherein the special asynchronous path obtains a time sequence path from an output port Q end of a sending register to an input port D end of a receiving register;
the third determination is an asynchronous path loop:
extracting an asynchronous path timing _ path in a loop process, and acquiring a clock cycle of a sending register and a clock cycle of a receiving register of the asynchronous path timing _ path by using a get _ attribute command (the attribute value of an object or an object set can be retrieved);
determining the maximum delay:
according to the constraint rule in the comprehensive constraint file SDC, the data transmission of the asynchronous path can time the propagation time between two triggers working at different working frequencies; in the clock period of the sending register and the clock period of the receiving register, selecting a minimum period min _ clk for setting the maximum delay (max _ delay); one asynchronous path constraint extracted up to this point is completed, which is the maximum time delay from the output port Q end of the sending register to the input port D end of the receiving register is the minimum period in the clock cycle of the sending register and the clock cycle of the receiving register, i.e., set _ max _ delay [ expr $ min _ clk × 1 ] -from [ get _ pins $ start/Q ] -to [ get _ pins $ D ];
the clock period comparison function is:
then the pt tool will automatically continue to complete the cycle according to the previously input command, analyze and complete the end set corresponding to each sending register in the start set list, extract each asynchronous path in the project, finish the cycle after outputting the constraint of the asynchronous path, and complete the extraction of the asynchronous path;
the second embodiment:
based on the first embodiment, in the process of extracting the asynchronous path of the first embodiment:
after SDC constraint is generated in the pt stage, because an unconstrained path exists in a clock domain of an asynchronous path, in order to better reduce the running time of a tool, an option of reporting the unconstrained path is suggested to be closed in the pt process; now for subsequent fetching of asynchronous paths, the primary job is to open the settings in pt:
set_app_var timing_report_unconstrained_pathstrue；
set_app_var timing_report_unconstrained_paths true
the operation is that pt analysis is informed that an unconstrained path exists in an asynchronous clock domain to be reported, and an unconstrained asynchronous path reported is informed, so that the follow-up analysis is carried out on the asynchronous path;
the working principle is as follows:
the patent adopts the extraction opportunity at the static time sequence analysis stage pt: and (3) extracting an asynchronous path: extracting an asynchronous time sequence path between an asynchronous sending register and an asynchronous receiving register based on a test case of the asynchronous interactive simulation circuit; determining the maximum delay: based on the constraint rule of the asynchronous time sequence path, the maximum delay period of the asynchronous time sequence path between the asynchronous sending register and the asynchronous receiving register is determined, and due to the complexity of the asynchronous circuit, designers need to have more correct and complete knowledge on the structural function of the asynchronous circuit, and reasonable constraint requirements are provided for rear-end physical implementers in all aspects; in order to avoid that when the asynchronous circuit is restrained, partial paths with restraint requirements are omitted so as to influence the function and performance of the asynchronous circuit, the extraction method of the asynchronous circuit is that all internal asynchronous paths are automatically analyzed and extracted while SDC is generated at a pt stage, and the maximum delay (max _ delay) of the asynchronous paths is restrained so as to be used for carrying out sequential inspection and maintenance on subsequent asynchronous paths at a rear end, therefore, the asynchronous paths are automatically extracted at the pt stage and the maximum delay (max _ delay) of the asynchronous paths is automatically restrained, meanwhile, in the process of extracting the asynchronous paths, the asynchronous circuit comprises extracting an asynchronous transmitting register, extracting an asynchronous receiving register and determining the asynchronous transmitting register, after the asynchronous transmitting register is determined, the asynchronous receiving register is determined through the connection relation between an output port and the asynchronous receiving register, after the asynchronous transmitting register and the asynchronous receiving register are determined, the connection relation between the asynchronous transmitting register and the asynchronous receiving register is determined, the asynchronous transmitting register is determined as an asynchronous timing path, and because the particularity of the asynchronous circuit determines that designers need to correctly and perfect the structure function of the asynchronous circuit, and provide a reasonable restraint for the designers to find the maximum restraint end of the physical requirements of the asynchronous paths (max) and then carry out early restraint on the constraint end, and provide the constraint for the constraint of the personnel; meanwhile, in the process of determining the maximum delay, furthermore, because the static timing analysis stage pt generates a timing constraint file SDC which also comprises an asynchronous timing path constraint rule, an asynchronous timing path is found by extracting the asynchronous path, the asynchronous timing path has a minimum clock period, and the minimum clock period is regarded as the maximum delay period, therefore, the maximum delay (max _ delay) of the asynchronous path is constrained in the automatically extracted asynchronous path, the characteristic that the path delays of two asynchronous clock domains are still constrained is ensured, the more detailed path constraint is set to a certain extent, and all the asynchronous paths are extracted by using a tool to ensure the function and the performance of the asynchronous path;
the invention solves the problem that the prior art has the function and performance of the asynchronous path in the back-end time sequence convergence simulation environment and restricts the maximum delay of the asynchronous path on the premise of ensuring the function and performance of the asynchronous path, has the characteristic of ensuring that the path delays of two asynchronous clock domains are still restricted, realizes the more detailed path restriction to a certain extent, extracts all the asynchronous paths in a comprehensive restriction file SDC by using a tool, and restricts the maximum delay of the asynchronous path to ensure the function and performance of the asynchronous path.
The technical solutions of the present invention or those skilled in the art, based on the teachings of the technical solutions of the present invention, are designed to achieve the above technical effects, and all of them fall into the protection scope of the present invention.
Claims (7)
1. The asynchronous path extraction method based on the back end time sequence convergence simulation is characterized by comprising the following steps:
extracting time of pt in the static time sequence analysis stage:
and (3) extracting an asynchronous path: extracting an asynchronous time sequence path between an asynchronous sending register and an asynchronous receiving register based on a test case of an asynchronous interactive simulation circuit;
determining the maximum time delay: determining the maximum delay period of an asynchronous time sequence path between an asynchronous sending register and an asynchronous receiving register based on an asynchronous time sequence path constraint rule;
the determining the maximum delay further comprises:
determining the minimum clock cycle of the asynchronous time sequence path based on the asynchronous time sequence path constraint rule in the time sequence constraint file SDC, and determining the minimum clock cycle as the maximum delay cycle;
the determining the maximum delay further comprises:
acquiring and comparing a clock cycle of an asynchronous transmitting register and a clock cycle of an asynchronous receiving register based on an asynchronous time sequence path, comparing the clock cycle of the asynchronous transmitting register and the clock cycle of the asynchronous receiving register through a clock cycle comparison function, determining the minimum clock cycle of the asynchronous transmitting register and the asynchronous receiving register, and determining the maximum time delay between an output port Q end of the asynchronous transmitting register and an input port D end of the asynchronous receiving register as the minimum clock cycle of the asynchronous transmitting register and the asynchronous receiving register;
the clock period comparison function is:
the DelaymaxIs the maximum delay period;
the DelaystartClock cycles for the asynchronous transmit register;
the DelayendIs the clock cycle of the asynchronous receive register.
2. The asynchronous path extraction method of claim 1, wherein extracting the asynchronous path further comprises:
extracting an asynchronous sending register: extracting any asynchronous sending register in a test case of the asynchronous interactive simulation circuit, and determining the asynchronous sending register as an asynchronous sending register;
extracting an asynchronous receiving register: based on the asynchronous sending register, determining any asynchronous receiving register according to the connection relation between the output port of the asynchronous sending register and the asynchronous receiving register, and determining the asynchronous receiving register as an asynchronous receiving register;
the determination is as follows: and determining the connection relation of the asynchronous sending register and the asynchronous receiving register as an asynchronous timing path.
3. The asynchronous path extraction method as defined in claim 2, wherein said extracting an asynchronous send register further comprises:
first fetch asynchronous send register cycle:
establishing a whole register set comprising all register units;
converting all register sets into asynchronous sending register sets according to the fan-out relation characteristics of the asynchronous sending registers;
and extracting any asynchronous sending register in the asynchronous sending register set and determining the asynchronous sending register.
4. The asynchronous path extraction method as defined in claim 3, wherein said extracting the asynchronous transmit register further comprises:
if the connection relation does not exist between the registers, closing an asynchronous time sequence path of an unconstrained rule in the time sequence constraint file SDC;
and if the connection relation exists between the registers but the constraint rule does not exist, opening the asynchronous time sequence path of the unconstrained rule in the time sequence constraint file SDC.
5. The asynchronous path extraction method of claim 2, wherein said extracting an asynchronous receive register further comprises:
second fetch asynchronous receive register loop:
based on the asynchronous send register;
converting the output relation of all external output pins of the asynchronous transmitting register into an asynchronous receiving register set through the connection of a D input port of a Q output port;
any asynchronous receiving register in the asynchronous receiving register set is extracted and determined as an asynchronous receiving register.
6. The asynchronous path extraction method of claim 2, wherein the determining to be an asynchronous path further comprises:
the third determination is an asynchronous path loop:
and acquiring an asynchronous time sequence path from an output port Q end of the asynchronous transmitting register to an input port D end of the asynchronous receiving register based on the determined asynchronous transmitting register and the determined asynchronous receiving register.
7. Asynchronous path extraction system based on back-end timing closure simulation, characterized in that, executing the asynchronous path extraction method based on back-end timing closure simulation as claimed in any of claims 1-6, the system comprises: an asynchronous path extraction module and a maximum delay determination module;
and an asynchronous path extraction module: for extracting an asynchronous path;
a maximum delay determining module: for determining a maximum delay;
the asynchronous path extracting module comprises an asynchronous transmitting register extracting submodule, an asynchronous receiving register extracting submodule and an asynchronous path determining submodule;
extracting an asynchronous sending register submodule: for extracting the asynchronous send register;
extracting an asynchronous receiving register submodule: for extracting an asynchronous receive register;
determining as an asynchronous path submodule: for determining as an asynchronous path;
the maximum delay determining module comprises a maximum delay determining core submodule;
determining a maximum delay core submodule: for determining the maximum delay kernel.
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