WO2019033682A1

WO2019033682A1 - Clock signal analysis method

Info

Publication number: WO2019033682A1
Application number: PCT/CN2017/119624
Authority: WO
Inventors: 刘法志
Original assignee: 郑州云海信息技术有限公司
Priority date: 2017-08-15
Filing date: 2017-12-29
Publication date: 2019-02-21
Also published as: CN107480376A; CN107480376B

Abstract

Disclosed is a clock signal analysis method. The method comprises: S1, acquiring link structures where a clock signal is located; S2, extracting topological structures of all the link structures; S3, calculating, based on the obtained topological structures, the longest and shortest flight time of the clock signal; and S4, substituting the data obtained in step S3 into a formula about a setup time and a holding time, and determining, according to a calculation result, whether a problem exists in the clock signal of a system. According to the method, the clock signal is analysed from a design stage of a circuit board in order to ensure that a design scheme that is as sound as possible is obtained at the design stage, thereby preventing resource losses and reducing design costs.

Description

[Correct according to Rule 26 09.02.2018] A method of analyzing clock signals

The present application claims priority to Chinese Patent Application No. 200910695574.9, entitled "A Method for Analyzing Clock Signals", filed on August 15, 2017, the entire contents of which is incorporated herein by reference. .

Technical field

[Correct according to Rule 26 09.02.2018]
The embodiments of the present application relate to the technical field of circuit board design, and in particular, to a method for analyzing a clock signal.

Background technique

In the board, the clock signal is an integral part of every board and is used to control the timing of the entire system. The clock signal is usually generated by a crystal oscillator, which is a crystal that converts electrical energy and mechanical energy into a resonant state to provide stable, accurate single-frequency oscillation.

In practical applications, the environmental factors that affect the operation of the clock signal are electromagnetic interference (EMI), mechanical shock and shock, humidity and temperature. These factors increase the output frequency, increase instability, and in some cases, It will also cause the crystal to stop vibrating.

Since the clock signal performance is affected by environmental conditions and circuit component selection, in order to ensure the stability of the clock signal, the component selection and circuit board layout of the clock circuit must be taken seriously. At present, the analysis and research of the clock signal basically starts to measure the clock signal after the printed circuit board is completed. If a problem is found, the board needs to be scrapped and redesigned. This retirement process may be Repeated several times, resulting in resource loss and increased design costs.

Summary of the invention

[Correct according to Rule 26 09.02.2018]
In order to solve the above problems, an embodiment of a method for analyzing a clock signal is provided. The method embodiment analyzes a clock signal from a design stage of a circuit board to ensure that a design scheme that is as complete as possible is obtained during the design phase, thereby avoiding resource loss and reducing Design cost.

[Correct according to Rule 26 09.02.2018]
An embodiment of the present invention provides a method for analyzing a clock signal, where the method includes:

[Correct according to Rule 26 09.02.2018]
S1: acquiring a link structure where the clock signal is located;

S2: extracting the topology of all link structures;

[Correct according to Rule 26 09.02.2018]
S3: calculating a maximum and minimum flight time of the clock signal based on the obtained topology;

[Correct according to Rule 26 09.02.2018]
S4: Bring the data obtained in step S3 into the formula of the setup time and the hold time, and judge whether the clock signal of the system has a problem according to the calculation result.

Further, the specific implementation process of the step S1 is:

S11: determining a clock signal source and a target electronic component in the entire clock system;

[Correct according to Rule 26 09.02.2018]
S12: extracting all clock signal wirings between the clock signal source and the target electronic component;

[Correct according to Rule 26 09.02.2018]
S13: Among all the wirings obtained in step S12, two wirings having the longest length and the shortest length are selected as the link structure in which the clock signal is located.

Further, the specific implementation process in the step S2 is:

S21: Import the link structure acquired in step S1 into the signal simulation software;

S22: Extract the corresponding topology from the imported link structure by using signal simulation software.

Further, the specific implementation process of the step S3 is:

S31: Obtain a maximum and minimum flight time of the clock source clock signal;

S32: Obtain the maximum and minimum flight time of the target electronic component clock signal.

Further, the specific implementation process of step S31 is:

[Correct according to Rule 26 09.02.2018]
In the signal simulation software, first set the clock signal source as the signal transmitting end, set the target electronic component as the signal receiving end, then set the cutoff frequency and measurement period of the whole signal transmission, and thirdly, apply a standard to the signal transmitting end. Pulse waveform, obtain the simulation waveform of the clock signal at the signal input end and the signal output end. Finally, extract the corresponding abscissa at the value of the peak value of the simulated waveform wave 2/3 as the maximum flight time of the clock signal source clock signal, and extract the simulation waveform trough The corresponding abscissa at the value of 2/3 is used as the minimum time of flight of the clock source clock signal.

Further, the specific implementation process of the step S32 is:

Using signal simulation software, the minimum flight time and maximum flight time of the target electronic component clock signal are measured multiple times, and then enter the measurement module to extract the minimum number of minimum flight times as the minimum flight time of the target electronic component clock signal. The maximum number of maximum flight times is extracted as the maximum flight time of the target electronic component clock signal.

Further, the specific implementation process of step S4 is:

[Correct according to Rule 26 09.02.2018]
Calculate the setup time of the entire clock system, and determine whether the calculation result is positive. If yes, go to the next step. If no, it indicates that there is a problem with the clock signal;

[Correct according to Rule 26 09.02.2018]
Calculate the hold time of the entire clock system to determine whether the calculation result is positive. If yes, the clock signal meets the requirements. If not, the clock signal has a problem.

The effects provided in the Summary of the Invention are merely the effects of the embodiments, and not all of the effects of the invention. One of the above technical solutions has the following advantages or benefits:

In the embodiment of the present invention, the entire link structure of the clock system is extracted, and the longest and shortest paths are intercepted as analysis objects, and the simulation software is used to simulate the actual running state, and the maximum and minimum clock signals of the clock signal source and the target electronic component are obtained. The flight time data is then verified by the obtained data whether the value of the whole clock system setup time and hold time is positive, which enables accurate analysis of the clock system wiring design, ensuring the best possible design in the design phase, avoiding resource loss. , reduce design costs.

DRAWINGS

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments of the present application or the description of the prior art will be briefly described below. Obviously, the drawings in the following description These are merely some of the illustrative embodiments of the present application, and other drawings may be obtained from those of ordinary skill in the art without departing from the scope of the invention.

1 is a flow chart of a method according to an embodiment of the present invention;

2 is a schematic diagram of circuit board wiring in an embodiment of the present invention.

Detailed ways

In order to clearly illustrate the technical features of the present solution, the present invention will be described in detail below through the specific embodiments and the accompanying drawings. The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and arrangements of the specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of simplicity and clarity, and is not in the nature of the description of the various embodiments and/or arrangements discussed. It is noted that the components illustrated in the drawings are not necessarily drawn to scale. The description of the known components and processing techniques and processes is omitted to avoid unnecessarily limiting the present invention.

Example

[Correct according to Rule 26 09.02.2018]
As shown in FIG. 1, an embodiment of a method for analyzing a clock signal is provided. The method embodiment includes:

[Correct according to Rule 26 09.02.2018]
S1: Obtain the link structure where the clock signal is located. The specific steps are as follows:

As shown in FIG. 2, a common PCIe bus is provided. The PCIe bus is composed of a south bridge chip U49 with three PCI slots, a PCI chip U9, and a clock driver U39. The system clock is clocked by the clock driver U39 to generate a 33 MHz clock that provides synchronized clock signals for each device on the PCI bus. CLK_33M_SB, CLK_33M_VGA, PCI_LO0_AD14, and PCI_LO0_AD25 represent wirings for connecting electronic components, respectively. Among them, U39 is the clock signal source, U9 and U49 are the target electronic components, CLK_33M_SB, CLK_33M_VGA, PCI_LO0_AD14, PCI_LO0_AD25 four wirings represent the wiring of the entire clock system.

S2: Extract the topology of all link structures. The specific steps are as follows:

S22: Extract the corresponding topology structure from the imported link structure by using signal simulation software.

In practice, the topology can be extracted by the signal manipulation function in the SigXplorer simulation software.

[Correct according to Rule 26 09.02.2018]
S3: Calculate the maximum and minimum flight time of the clock signal based on the obtained topology, and the specific implementation process is:

S31: Obtain the maximum and minimum flight time of the clock source clock signal, and the specific implementation process is:

[Correct according to Rule 26 09.02.2018]
In the signal simulation software, based on the link topology obtained in step S2, first, the clock signal source is set as the signal transmitting end, and the target electronic component is set as the signal receiving end. Then set the cutoff frequency and measurement period of the entire signal transmission. For example, the Default Cutoff Frequency is set to 10 GHz and the Measurement Cycle is 5-8 (s). Third, a standard pulse waveform is applied to the signal transmitting end, and a simulated waveform of the clock signal is obtained at the signal input end and the signal output end. Finally, extract the corresponding abscissa at the value of the peak value of the simulated waveform wave 2/3 as the maximum flight time of the clock signal source clock signal, and extract the corresponding abscissa at the value of the simulated waveform trough value 2/3 as the clock source clock signal. Minimum flight time.

S32: Obtain the maximum and minimum flight time of the target electronic component clock signal, and the specific implementation process is: using the signal simulation software to perform multiple measurements on the minimum flight time and the maximum flight time of the target electronic component clock signal, and then enter the measurement module. For the SigXplorer simulation software, it is the measurement window, extracting the minimum value in the minimum flight time as the minimum flight time of the target electronic component clock signal, and extracting the maximum value in the maximum flight time as the maximum flight time of the target electronic component clock signal. .

[Correct according to Rule 26 09.02.2018]
S4: Bring the data obtained in step S3 into the formula of the setup time and the hold time, and judge whether the clock signal of the system has a problem according to the calculation result. The specific implementation process is:

Take the clock system shown in Figure 2 as an example:

It is assumed that a simulation waveform is obtained through step S31, and the maximum flight time T _{flt_data_max} = 1.98217 ns of the clock source clock signal is obtained, and the minimum flight time T _{flt_data_min} = 1.63186 ns of the clock source clock signal is obtained. In addition, the minimum time-of-flight Switch Delay of the south bridge chip clock signal obtained by the CLK_33M_VGA measurement window is 1.77586 ns and the maximum flight time Settle Delay is 2.13682 ns. Similarly, the minimum Switch Delay and the maximum Settle Delay flight time of the clock signal of the PCI chip U9 can be obtained from the measurement window to be 1.46884 ns and 1.85385 ns, respectively.

The calculation process is as follows:

The maximum clock difference is:

T _{PCB_skew_max} =T _{flt_clkB} -T _{flt_clkA} =2.13682-1.46884=0.66798ns;

Where T _{flt_clkB} is the maximum flight time of the south bridge chip clock signal, and T _{flt_clkA} is the minimum flight time of the clock signal of the PCI chip.

The smallest clock difference is:

T _{PCB_skew_min} =T _{flt_clkB} -T _{flt_clkA} =1.77586-1.85385=-0.07799ns;

Where T _{flt_clkB} is the minimum flight time of the south bridge chip clock signal, and T _{flt_clkA} is the maximum flight time of the clock signal of the PCI chip.

The setup time of the entire clock system is:

Wherein, T _cycle is a clock cycle.

For the clock chip parameters, T _fitter is the clock jitter, T _{CO_drive_max} is the maximum value of the south bridge chip timing parameter, and T _setup is the PCI chip setup time timing parameter.

The hold time of the entire clock system is:

Among them, T _{CO_drive_min} South Bridge chip timing parameter minimum,

For the clock chip parameters, T _hold is the PCI chip hold time timing parameter.

After the simulation results and theoretical calculations, the establishment and maintenance timing margin of the PCI bus designed in this paper are all positive and meet the requirements.

It should be noted that the above calculation process is only for the clock system shown in FIG. 2, and the calculation formula of the clock system setup time and the hold time is the prior art, and the technician can flexibly apply the clock system according to the analysis.

While the invention has been described in detail with reference to the embodiments of the embodiments of the present invention, it is understood that the invention may be modified or equivalently substituted without departing from the spirit and scope of the invention. The technical solutions and their improvements are all covered by the scope of protection of the patents of the present invention.

Claims

[Correct according to Rule 26 09.02.2018]

A method for analyzing a clock signal, characterized in that: the method comprises:

S1: acquiring a link structure where the clock signal is located;

S2: extracting the topology of all link structures;

S3: calculating a maximum and minimum flight time of the clock signal based on the obtained topology;

S4: Bring the data obtained in step S3 into the formula of the setup time and the hold time, and judge whether the clock signal of the system has a problem according to the calculation result.
[Correct according to Rule 26 09.02.2018]

A method for analyzing a clock signal according to claim 1, wherein the specific implementation process of the step S1 is:

S11: determining a clock signal source and a target electronic component in the entire clock system;

S12: extracting all clock signal wirings between the clock signal source and the target electronic component;

S13: Among all the wirings obtained in step S12, two wirings having the longest length and the shortest length are selected as the link structure in which the clock signal is located.
[Correct according to Rule 26 09.02.2018]

A method for analyzing a clock signal according to claim 2, wherein the specific implementation process in the step S2 is:

S21: Import the link structure acquired in step S1 into the signal simulation software;

S22: Extract the corresponding topology from the imported link structure by using signal simulation software.
[Correct according to Rule 26 09.02.2018]

The method for analyzing a clock signal according to claim 3, wherein the specific implementation process of the step S3 is:

S31: Obtain a maximum and minimum flight time of the clock source clock signal;

S32: Obtain the maximum and minimum flight time of the target electronic component clock signal.
[Correct according to Rule 26 09.02.2018]

A method for analyzing a clock signal according to claim 4, wherein the specific implementation process of step S31 is:

In the signal simulation software, first set the clock signal source as the signal transmitting end, set the target electronic component as the signal receiving end, then set the cutoff frequency and measurement period of the whole signal transmission, and thirdly, apply a standard to the signal transmitting end. Pulse waveform, obtain the simulation waveform of the clock signal at the signal input end and the signal output end. Finally, extract the corresponding abscissa at the value of the peak value of the simulated waveform wave 2/3 as the maximum flight time of the clock signal source clock signal, and extract the simulation waveform trough The corresponding abscissa at the value of 2/3 is used as the minimum time of flight of the clock source clock signal.
[Correct according to Rule 26 09.02.2018]

The method for analyzing a clock signal according to claim 4, wherein the specific implementation process of the step S32 is:

Using signal simulation software, the minimum flight time and maximum flight time of the target electronic component clock signal are measured multiple times, and then enter the measurement module to extract the minimum number of minimum flight times as the minimum flight time of the target electronic component clock signal. The maximum number of maximum flight times is extracted as the maximum flight time of the target electronic component clock signal.
[Correct according to Rule 26 09.02.2018]

A method for analyzing a clock signal according to claim 4, wherein the specific implementation process of step S4 is:

Calculate the setup time of the entire clock system, and determine whether the calculation result is positive. If yes, go to the next step. If no, it indicates that there is a problem with the clock signal;

Calculate the hold time of the entire clock system to determine whether the calculation result is positive. If yes, the clock signal meets the requirements. If not, the clock signal has a problem.