CN108614206B - Chip testing device, chip testing method and chip testing board - Google Patents
Chip testing device, chip testing method and chip testing board Download PDFInfo
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- CN108614206B CN108614206B CN201810298527.5A CN201810298527A CN108614206B CN 108614206 B CN108614206 B CN 108614206B CN 201810298527 A CN201810298527 A CN 201810298527A CN 108614206 B CN108614206 B CN 108614206B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
Abstract
The invention provides a chip testing device, a chip testing method and a chip testing board, wherein the chip testing device comprises a testing machine, a driving circuit and a driving circuit, wherein the testing machine is used for outputting a driving testing signal; the signal phase detection circuit compares the chip receiving signal with a standard signal to form a comparison result; the signal phase detection circuit outputs the comparison results to the tester and the latch respectively; when no phase difference signal exists between the chip receiving signal and the standard signal, the route selector outputs the chip receiving signal to the chip to be tested; if the phase difference signal exists, the testing machine performs phase adjustment output on the driving test signal according to the phase difference signal so as to form a chip receiving signal again and compare the chip receiving signal with the standard signal until the phase difference signal between the chip receiving signal and the standard signal is zero. The technical method has the beneficial effect of overcoming the problem that when the test board in the prior art carries out chip parallel test, the chip receiving signals of the chip to be tested have distortion due to different lengths of the transmission lines.
Description
Technical Field
The invention relates to the technical field of semiconductor chip testing, in particular to a chip testing device, a chip testing method and a chip testing board.
Background
In the prior art, when a chip to be tested is tested, a test structure provided by the prior art is shown in fig. 1, a test board a1 is provided with a plurality of sockets a2, each socket a2 is used for fixing and connecting the chip to be tested and is connected with an electrical connection structure A3 through a transmission line a4, the electrical connection structure is connected with a test device, and the test device provides clock driving test signals with corresponding frequencies to the chip to be tested, but as can be seen from fig. 1, the chips to be tested are distributed at different positions on the test board a1, and the lengths of the transmission lines A3 connected between each chip to be tested and the electrical connection structure A3 are different, so that the driving test signals received by the chips to be tested at different positions are synchronous in step, further, signals output by the chips are asynchronous, and misjudgment is caused on the test result of the chip to be tested.
Disclosure of Invention
Aiming at the problems that the chip to be tested receives the driving test signal in the prior art, the chip testing device, the chip testing method and the chip testing board are provided for solving the problem that the phase distortion of the received driving test signal is caused by the difference of the lengths of the transmission lines of the chip to be tested.
The specific technical scheme is as follows:
a chip testing device is applied to the regulation of chip receiving signals of a chip to be tested, and comprises a testing machine, a chip receiving unit and a chip receiving unit, wherein the testing machine is used for outputting a driving test signal;
the path selector comprises a first input end, a second input end, a first output end and a second output end, wherein the first input end is connected with the output end of the tester, the driving test signal forms a chip receiving signal through transmission delay, and the second output end of the path selector is connected with the input end of the chip to be tested;
the input end of the signal phase detection circuit is connected with the first output end of the route selector, and the output end of the signal phase detection circuit is connected with the input end of the tester; the route selector outputs the chip receiving signal to the signal phase detection circuit in an initial state;
the signal phase detection circuit compares the chip receiving signal with a standard signal to form a comparison result;
the input end of the latch is connected with the output end of the signal phase detection circuit, and the output end of the latch is connected with the second input end of the route selector;
the signal phase detection circuit outputs the comparison result to the tester and the latch respectively;
when the comparison result shows that no phase difference signal exists between the chip receiving signal and the standard signal, the latch sends a control signal to the route selector so that the chip receiving signal output by the route selector is output to the chip to be tested through the second output end;
and when the comparison result shows that a phase difference signal exists between the chip receiving signal and the standard signal, the testing machine performs phase adjustment output on the driving test signal according to the phase difference signal so as to form the chip receiving signal again and compare the chip receiving signal with the standard signal until the phase difference signal between the chip receiving signal and the standard signal is zero.
Preferably, the comparison result indicates whether the phase difference signal exists between the chip receiving signal and the standard signal;
the testing machine provides a preset algorithm, and after receiving the phase difference signal, the testing machine performs phase adjustment processing on the driving test signal through the preset algorithm according to the difference value of the phase difference signal to form adjusted driving test signal output.
Preferably, the router includes two channel operation states, and the control signal output by the latch includes a first state control signal and a second state control signal;
a first path working state, after the latch receives the comparison result, if the comparison result shows that a phase difference signal exists between the chip receiving signal and the standard signal, the latch sends the first state control signal to the route selector, and the route selector gates the first output end according to the first state control signal to output the chip receiving signal to the signal phase detection circuit
Preferably, the router includes two channel operation states, and the control signal output by the latch includes a first state control signal and a second state control signal;
and in a second channel working state, after receiving the comparison result, if the comparison result shows that no phase difference signal exists between the chip receiving signal and the standard signal, the latch sends the second state control signal to the route selector, and the route selector gates the second output end according to the second state control signal, so that the chip receiving signal is output to the chip to be tested.
The chip testing method is further included, wherein the chip testing device is applied, and the chip testing method comprises the following steps:
step S1, the test machine outputs the driving test signal and forms the chip receiving signal after transmission delay;
step S2, the router compares the chip received signal with the standard signal, and outputs the comparison result to the latch and the tester respectively;
step S3, whether the comparison result indicates that the phase difference signal exists between the chip received signal and the standard signal;
if yes, the tester performs phase adjustment output on the driving test signal according to the phase difference signal, and returns to the step S1;
if not, the latch sends a control signal to the route selector, so that the chip receiving signal output by the route selector is output to the chip to be tested through the second output end and exits.
Preferably, the comparison result indicates whether the phase difference signal exists between the chip receiving signal and the standard signal;
the testing machine provides a preset algorithm, and after receiving the phase difference signal, the testing machine performs phase adjustment processing on the driving test signal through the preset algorithm according to the difference value of the phase difference signal to form adjusted driving test signal output.
Preferably, the router includes two channel operation states, and the control signal output by the latch includes a first state control signal and a second state control signal;
a first path working state, after receiving the comparison result, if the comparison result indicates that a phase difference signal exists between the chip receiving signal and the standard signal, the latch sends the first state control signal to the route selector, and the route selector gates the first output end according to the first state control signal, so that the chip receiving signal is output to the signal phase detection circuit;
preferably, the router includes two channel operation states, and the control signal output by the latch includes a first state control signal and a second state control signal;
and in a second channel working state, after receiving the comparison result, if the comparison result shows that no phase difference signal exists between the chip receiving signal and the standard signal, the latch sends the second state control signal to the route selector, and the route selector gates the second output end according to the second state control signal, so that the chip receiving signal is output to the chip to be tested.
Further comprising a test board, wherein the chip testing device as claimed in claim 1 is provided on the test board, the test board comprising:
a plate body;
the plurality of sockets are used for fixing and connecting the chip to be tested;
each socket is connected with the electric connection through a transmission line, and the electric connection is connected with the tester;
the route selector is connected between the transmission line of the chip to be tested and the chip to be tested.
Preferably, the electrical connection structure is a gold finger structure arranged on the board body.
The technical scheme has the following advantages or beneficial effects: the chip detection device can adjust the phase of the chip receiving signal with signal delay, so that the finally output chip receiving signal is consistent with the standard signal, and the problem that the chip receiving signal of the chip to be detected has distortion due to different lengths of transmission lines when the test board in the prior art carries out chip parallel test is solved.
Drawings
Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. The drawings are, however, to be regarded as illustrative and explanatory only and are not restrictive of the scope of the invention.
FIG. 1 is a schematic diagram of a part of a test board according to the background art of the present invention;
FIG. 2 is a schematic structural diagram of an embodiment of a chip testing apparatus according to the present invention;
FIG. 3 is a flowchart illustrating a method for testing a chip according to an embodiment of the present invention.
The reference numerals denote:
1. a testing machine; 2. a route selector; 3. a signal phase detection circuit; 4. a chip to be tested; 5. a latch.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
The technical scheme of the invention comprises a chip testing device.
As shown in fig. 2, an embodiment of a chip testing apparatus, applied to adjust a chip receiving signal of a chip 4 to be tested, includes a tester 1 for outputting a driving test signal;
the path selector 2 comprises a first input end, a second input end, a first output end and a second output end, the first input end is connected with the output end of the tester 1, the driving test signal forms a chip receiving signal through transmission delay, and the second output end of the path selector 2 is connected with the input end of the chip 4 to be tested;
the input end of the signal phase detection circuit 3 is connected with the first output end of the route selector 2, and the output end of the signal phase detection circuit 3 is connected with the input end of the testing machine 1; the route selector 2 outputs the chip receiving signal to the signal phase detection circuit 3 in an initial state;
the signal phase detection circuit 3 compares the chip receiving signal with a standard signal to form a comparison result;
the input end of the latch 5 is connected with the output end of the signal phase detection circuit 3, and the output end of the latch 5 is connected with the second input end of the route selector 2;
the signal phase detection circuit 3 outputs the comparison results to the tester 1 and the latch 5, respectively;
when the comparison result shows that no phase difference signal exists between the chip receiving signal and the standard signal, the latch 5 sends a control signal to the route selector 2 so that the chip receiving signal output by the route selector 2 is output to the chip 4 to be tested through the second output end;
when the comparison result indicates that a phase difference signal exists between the chip receiving signal and the standard signal, the tester 1 performs phase adjustment output on the driving test signal according to the phase difference signal to form a chip receiving signal again and compare the chip receiving signal with the standard signal until the phase difference signal between the chip receiving signal and the standard signal is zero.
The problem that in the prior art, when the test board tests the chips 4 to be tested, due to different lengths of transmission lines between the chips 4 to be tested and the electric connection structures, asynchronism exists between chip receiving signals of the chips 4 to be tested in the parallel detection process is solved.
In the invention, a chip receiving signal of a chip 4 to be tested is compared with a standard signal (the standard signal refers to the chip receiving signal without a delay signal, the standard signal is obtained by selecting from a test result after the chip 4 to be tested is tested by a testing machine 1) in real time to judge whether a phase difference signal exists between the current chip receiving signal and the standard signal, and if the phase difference signal does not exist, the chip receiving signal is directly output to the chip 4 to be tested for testing;
if the phase difference signal exists, the phase adjustment output is carried out on the output driving test signal through the testing machine 1, then a chip output signal is formed after transmission delay processing, the chip output signal is compared with the standard signal again, if the phase difference signal does not exist between the chip receiving signal and the standard signal at the moment, the current chip receiving signal is output to the chip, otherwise, the driving test signal is continuously adjusted through the testing machine 1, the judgment is repeated until the phase difference signal does not exist between the adjusted chip receiving signal and the standard signal, and the driving test signal is directly output to the chip 4 to be tested.
In a preferred embodiment, the comparison result represents a phase difference signal between the chip receive signal and the standard signal;
the test machine 1 provides a preset algorithm, and after receiving the phase difference signal, performs phase adjustment processing on the driving test signal through the preset algorithm according to the difference value of the phase difference signal to form an adjusted driving test signal output.
In the above technical solution, the preset algorithm is specifically that the test machine 1 performs high-frequency sampling analysis on the signal output by the signal phase detection circuit 3 to obtain a start time t1 and an end time t2 of the signal, and a phase difference Δ t is t2-t1, and then changes the original driving test signal by Δ t to generate a new driving test signal, that is, an adjusted driving test signal.
In a preferred embodiment, the router 2 comprises two channel operation states, and the control signal output by the latch 5 comprises a first state control signal and a second state control signal;
after the latch 5 receives the comparison result, if the comparison result indicates that a phase difference signal exists between the chip received signal and the standard signal, the latch 5 sends a first state control signal to the route selector 2, and the route selector 2 gates a first output end according to the first state control signal, so that the chip received signal is output to the signal phase detection circuit 3.
In a preferred embodiment, the router 2 comprises two channel operation states, and the control signal output by the latch 5 comprises a first state control signal and a second state control signal;
and in the second channel working state, after the latch 5 receives the comparison result, if the comparison result shows that no phase difference signal exists between the chip receiving signal and the standard signal, the latch 5 sends a second state control signal to the route selector 2, and the route selector 2 gates a second output end according to the second state control signal, so that the chip receiving signal is output to the chip 4 to be tested.
The technical scheme of the invention also comprises a chip testing method.
An embodiment of a chip testing method, wherein the chip testing apparatus of claim 1 is applied, as shown in fig. 3, comprises the following steps:
step S1, the test machine 1 outputs the driving test signal to form a chip receiving signal after transmission delay;
step S2, the route selector 2 compares the chip received signal with the standard signal, and outputs the comparison result to the latch 5 and the tester 1 respectively;
step S3, whether the comparison result shows that there is a phase difference signal between the chip receiving signal and the standard signal;
if yes, the test machine 1 performs phase adjustment output on the driving test signal according to the phase difference signal, and returns to step S1;
if not, the latch 5 sends a control signal to the path selector 2, so that the chip receiving signal output by the path selector 2 is output to the chip 4 to be tested through the second output end and exits.
In a preferred embodiment, the comparison result indicates whether a phase difference signal exists between the chip received signal and the standard signal;
the test machine 1 provides a preset algorithm, and after receiving the phase difference signal, performs phase adjustment processing on the driving test signal through the preset algorithm according to the difference value of the phase difference signal to form an adjusted driving test signal output.
In a preferred embodiment, the router 2 comprises two channel operation states, and the control signal output by the latch 5 comprises a first state control signal and a second state control signal;
after the latch 5 receives the comparison result, if the comparison result indicates that a phase difference signal exists between the chip received signal and the standard signal, the latch 5 sends a first state control signal to the route selector 2, and the route selector 2 gates a first output end according to the first state control signal, so that the chip received signal is output to the signal phase detection circuit 3;
in a preferred embodiment, the router 2 comprises two channel operation states, and the control signal output by the latch 5 comprises a first state control signal and a second state control signal;
and in the second channel working state, after the latch 5 receives the comparison result, if the comparison result shows that no phase difference signal exists between the chip receiving signal and the standard signal, the latch 5 sends a second state control signal to the route selector 2, and the route selector 2 gates a second output end according to the second state control signal, so that the chip receiving signal is output to the chip 4 to be tested.
In the chip testing method of the above technology, each time the chip receiving signal is compared with the standard signal by the detection mode of the feedback loop, if there is a phase difference signal between the chip receiving signal and the standard signal, the tester 1 needs to perform phase adjustment on the driving test signal by using a preset algorithm according to the phase difference signal, then outputs the adjusted driving test signal to form a chip receiving signal in transmission, and compares the chip receiving signal with the standard signal again until the phase difference signal between the chip receiving signal and the standard signal is zero, that is, there is no phase difference signal, and the route selector 2 outputs the current chip receiving signal to the chip 4 to be tested.
The technical scheme of the invention also comprises a test board.
An embodiment of a test board for testing a device for chips thereon, the test board comprising:
a plate body;
a plurality of sockets for fixing and connecting the chip 4 to be tested;
each socket is connected with the electric connection through a transmission line and is electrically connected with the receiving and connecting test machine 1;
the route selector 2 is connected between the transmission line of the chip 4 to be tested and the chip 4 to be tested.
In a preferred embodiment, the electrical connection structure is a gold finger structure disposed on the board body.
In the technical scheme, the chip testing device is arranged on the testing board, and the phase adjustment can be carried out on the chip receiving signals with signal delay through the detection mode of the feedback loop adopted by the chip testing device, so that the finally output chip receiving signals are consistent with the standard signals, and the problem that the chip receiving signals of the chips to be tested have distortion due to different lengths of transmission lines when the testing board carries out parallel testing on the chips 4 in the prior art is solved.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (10)
1. A chip testing device is applied to the regulation of chip receiving signals of a chip to be tested and is characterized by comprising,
the tester is used for outputting a driving test signal;
the path selector comprises a first input end, a second input end, a first output end and a second output end, wherein the first input end is connected with the output end of the tester, the driving test signal forms a chip receiving signal through transmission delay, and the second output end of the path selector is connected with the input end of the chip to be tested;
the input end of the signal phase detection circuit is connected with the first output end of the route selector, and the output end of the signal phase detection circuit is connected with the input end of the tester; the route selector outputs the chip receiving signal to the signal phase detection circuit in an initial state;
the signal phase detection circuit compares the chip receiving signal with a standard signal to form a comparison result;
the input end of the latch is connected with the output end of the signal phase detection circuit, and the output end of the latch is connected with the second input end of the route selector;
the signal phase detection circuit outputs the comparison result to the tester and the latch respectively;
when the comparison result shows that no phase difference signal exists between the chip receiving signal and the standard signal, the latch sends a control signal to the route selector so that the chip receiving signal output by the route selector is output to the chip to be tested through the second output end;
and when the comparison result shows that the phase difference signal exists between the chip receiving signal and the standard signal, the tester performs phase adjustment output on the driving test signal according to the phase difference signal so as to form the chip receiving signal again and compare the chip receiving signal with the standard signal until the phase difference signal between the chip receiving signal and the standard signal is zero.
2. The chip test apparatus according to claim 1, wherein the comparison result indicates whether the phase difference signal exists between the chip reception signal and the standard signal;
the testing machine provides a preset algorithm, and after receiving the phase difference signal, the testing machine performs phase adjustment processing on the driving test signal through the preset algorithm according to the difference value of the phase difference signal to form adjusted driving test signal output.
3. The chip testing apparatus according to claim 1, wherein the router includes two channel operation states, and the control signal output by the latch includes a first state control signal and a second state control signal;
and after receiving the comparison result, if the comparison result shows that a phase difference signal exists between the chip receiving signal and the standard signal, the latch sends the first state control signal to the route selector, and the route selector gates the first output end according to the first state control signal, so that the chip receiving signal is output to the signal phase detection circuit.
4. The chip testing apparatus according to claim 3, wherein the router includes two channel operation states, the control signal output by the latch includes a first state control signal and a second state control signal;
and in a second channel working state, after receiving the comparison result, if the comparison result shows that no phase difference signal exists between the chip receiving signal and the standard signal, the latch sends the second state control signal to the route selector, and the route selector gates the second output end according to the second state control signal, so that the chip receiving signal is output to the chip to be tested.
5. A chip testing method, characterized in that the chip testing device as claimed in claim 1 is applied, comprising the steps of:
step S1, the test machine outputs the driving test signal and forms the chip receiving signal after transmission delay;
step S2, the signal phase detection circuit compares the chip received signal with the standard signal, and outputs the comparison result to the latch and the tester, respectively;
step S3, whether the comparison result indicates that the phase difference signal exists between the chip received signal and the standard signal;
if yes, the tester performs phase adjustment output on the driving test signal according to the phase difference signal, and returns to the step S1;
if not, the latch sends a control signal to the route selector, so that the chip receiving signal output by the route selector is output to the chip to be tested through the second output end and exits.
6. The chip test method according to claim 5, wherein the comparison result indicates whether the phase difference signal exists between the chip reception signal and the standard signal;
the testing machine provides a preset algorithm, and after receiving the phase difference signal, the testing machine performs phase adjustment processing on the driving test signal through the preset algorithm according to the difference value of the phase difference signal to form adjusted driving test signal output.
7. The chip testing method according to claim 5, wherein the router includes two channel operation states, the control signal output by the latch includes a first state control signal and a second state control signal;
and after receiving the comparison result, if the comparison result shows that a phase difference signal exists between the chip receiving signal and the standard signal, the latch sends the first state control signal to the route selector, and the route selector gates the first output end according to the first state control signal, so that the chip receiving signal is output to the signal phase detection circuit.
8. The chip testing method according to claim 7, wherein the router includes two channel operation states, the control signal output by the latch includes a first state control signal and a second state control signal;
and in a second channel working state, after receiving the comparison result, if the comparison result shows that no phase difference signal exists between the chip receiving signal and the standard signal, the latch sends the second state control signal to the route selector, and the route selector gates the second output end according to the second state control signal, so that the chip receiving signal is output to the chip to be tested.
9. A test board on which a chip testing device as claimed in claim 1 is provided, the test board comprising:
a plate body;
the plurality of sockets are used for fixing and connecting the chip to be tested;
each socket is connected with the electric connection structure through a transmission line, and the electric connection structure is connected with the testing machine;
the route selector is connected between the transmission line of the chip to be tested and the chip to be tested.
10. The test board according to claim 9, wherein the electrical connection structures are gold finger structures disposed on the board body.
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