CN109815619A - A method of asynchronous circuit is converted by synchronous circuit - Google Patents
A method of asynchronous circuit is converted by synchronous circuit Download PDFInfo
- Publication number
- CN109815619A CN109815619A CN201910123501.1A CN201910123501A CN109815619A CN 109815619 A CN109815619 A CN 109815619A CN 201910123501 A CN201910123501 A CN 201910123501A CN 109815619 A CN109815619 A CN 109815619A
- Authority
- CN
- China
- Prior art keywords
- circuit
- click
- asynchronous
- click unit
- asynchronous circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The present invention, which can be realized, is automatically converted to pipeline synchronization circuit the binding data asynchronous circuit based on Click unit.Firstly, difference of this method by comparing pipeline synchronization and the binding data asynchronous circuit based on Click unit, converts synchronous Verilog code to by Tcl script the Verilog code of the binding data asynchronous circuit based on Click unit.Then asynchronous circuit is integrated by Synopsys Design Compiler (DC) tool.The present invention, which can be fast implemented, converts the binding data asynchronous circuit based on Click for pipeline synchronization circuit, substantially reduces the period of Asynchronous circuit design and reduces Asynchronous circuit design difficulty.
Description
Technical field
The invention belongs to IC design technical fields, in particular to a kind of to convert asynchronous circuit for synchronous circuit
Method.
Background technique
With the continuous improvement of integrated circuit fabrication process, asynchronous circuit has following significant spy compared with synchronous circuit
Point.
1, low-power consumption: asynchronous circuit is only in the time of needs and the place consumption power consumption needed
2, at high speed: the delay of asynchronous circuit depends on part delay rather than the longest delay path of integrated circuit
3, without clock distribution problem: asynchronous circuit does not have global clock, so should not clock tree synthesis
However, the design of asynchronous circuit is relatively difficult.Since asynchronous circuit is not used by industry widely, institute
The design of asynchronous circuit is supported with unmature business eda tool.In addition, since numerous Integrated circuit digital engineers connects
What is received is all therefore the training that synchronous circuit designs there is set from synchronous circuit Design Thinking to asynchronous circuit in design
The transfer problem in thinking is counted, this just increases the difficulty of Asynchronous circuit design.Finally, the type of asynchronous circuit is more, it is different
There is also differences in design method for the asynchronous circuit of type, this also improves the threshold of Asynchronous circuit design to a certain extent.
Summary of the invention
In order to overcome the disadvantages of the above prior art, reduce the difficulty of Asynchronous circuit design, it is an object of the invention to mention
For a kind of method for converting asynchronous circuit for synchronous circuit, using closest based on Click unit with synchronous circuit
Data asynchronous circuit structure is bundled, can be designed by mature eda tool.
To achieve the goals above, the technical solution adopted by the present invention is that:
A method of asynchronous circuit being converted by synchronous circuit, is included the following steps:
Step 1, compare the difference of pipeline synchronization circuit Yu the binding data asynchronous circuit based on Click unit；
Step 2, it is converted the Verilog code of pipeline synchronization circuit to based on Click unit by Tcl script
Bundle the Verilog code of data asynchronous circuit；
Step 3, asynchronous circuit is integrated by Synopsys Design Compiler (DC) tool.
The pipeline synchronization circuit and the difference of the binding data asynchronous circuit based on Click unit are:
1), pipeline synchronization circuit drives d type flip flop, and binding data based on Click unit using global clock clk
Asynchronous circuit drives d type flip flop using the pulse signal that Click unit generates；
2), need additional Click unit that can drive D to generate based on the binding data asynchronous circuit of Click unit
The pulse of trigger, and pipeline synchronization circuit should not.
3, the method for converting asynchronous circuit for synchronous circuit according to claim 1, which is characterized in that Click
Unit carries out example, and netlist is as follows:
Click unit after exampleization prevents it to be changed during synthesis using set_dont_touch order.
The step 2 specifically includes:
Step 2.1: finding the pipeline series of pipeline synchronization circuit；
Step 2.2: the posedge clk in pipeline synchronization circuit code being replaced with into posedge fire, and in generation
The example of Click unit is added in code；
Step 2.3: the port clock in pipeline synchronization circuit code being replaced with into in_req, and is added in code
Other ports of Click unit.
In the step 2.1, it is labeled in pipeline synchronization circuit code by mode as follows, is then led to
It crosses Tcl script and finds the number of mark to find the series of assembly line:
In the step 2.2, the number of Click unit is added according to the series of assembly line, and by the posedge of every level-one
Clk is successively replaced with posedge fire1, posedge fire2, and so on, i.e. the posedge clk replacement of the first order
As posedge fire1, the posedge clk of the second level is replaced with posedge fire2, N grades of posedge clk
It is replaced with posedge fireN.Wherein the series of assembly line is equal with Click unit number.
In the step 2.3, the in_req, in_ack, out_ of Click unit are added in the statement part of code port
The port req, out_ack.
In the step 3, carrying out synthesis to asynchronous circuit by Synopsys Design Compiler (DC) tool is
Asynchronous pipeline code is converted by pipeline synchronization code, then to Click unit set_dont_touch, then to fire
Signal creation clock, to realize to circuit synthesis.
Compared with prior art, the present invention can directly convert pipeline synchronization circuit to the binding data based on Click
Asynchronous circuit greatly reduces the difficulty of Asynchronous circuit design.
Detailed description of the invention
Fig. 1 is the Click unit that the present invention uses.
Fig. 2 is the waveform diagram for the Click unit that the present invention uses.
Fig. 3 is the binding data asynchronous circuit basic framework figure based on Click unit.
Fig. 4 is present invention pipeline synchronization circuit diagram to be transformed.
Fig. 5 is the binding data asynchronous circuit signal based on Click unit that Fig. 4 pipeline synchronization circuit converts
Figure.
Specific embodiment
The embodiment that the present invention will be described in detail with reference to the accompanying drawings and examples.
The circuit diagram of Click unit is as shown in Figure 1:
It can be seen that containing d type flip flop in Click unit, and there is loop in circuit, therefore it is not a combination
Logic circuit.Such circuit if only describe its logical relation by Verilog, be can not by DC tool it is comprehensive go out
Desired circuit.Therefore, it is necessary to by solving this problem to the direct example of Click unit.Example is carried out to Click unit
The netlist of change is as shown in table 1.Click unit after exampleization needs that it is prevented to be changed during synthesis using order.
1 Click netlist of table
The waveform diagram of Click unit is as shown in Figure 2.Click unit uses two phase place Handshake Protocol, i.e. request signal
Overturning each time all represent primary request, and Click unit can all generate a pulse.This pulse can be considered as
Clock, for capturing and storaging data.In this way, can actually pulse caused by the Click control unit asynchronous circuit
Signal thus can create clock in comprehensive script for these pulse signals as being clock, then allow DC tool into
Row synthesis.
Binding data asynchronous circuit based on Click unit is one kind of existing asynchronous circuit, basic framework such as Fig. 3 institute
Show, according to the structure of Click, when being flipped the request signal (i_r1) of Click, a fire letter will be generated
Number for carrying out data capture or storage.And request signal can pass to the request signal that next stage serves as next stage
(i_r2)." binding data " refer to that data-signal using Boolean type numerical value, requests (request) and response (acknowledge)
Line is separated from each other and together with data-bound.
Convert pipeline synchronization circuit shown in Fig. 4 in the schematic diagram of the binding data asynchronous circuit based on Click unit
As shown in Figure 5.As can be seen that pipeline synchronization circuit and the asynchronous electricity of binding data based on Click unit from Fig. 4 and Fig. 5
Difference between road is:
1, synchronous circuit drives d type flip flop, and the arteries and veins that asynchronous circuit is generated using Click unit using global clock clk
Signal is rushed to drive d type flip flop.
2, asynchronous circuit needs additional Click unit to generate the pulse that can drive d type flip flop, and synchronous circuit is not
It wants.
Based on above-mentioned difference, can be converted the pipeline synchronization circuit described with Verilog to by following steps
Binding data asynchronous circuit based on Click unit.
Step 1: finding the series of assembly line.This can be by being marked in synchronizing code by mode shown in table 2
Note, can then find the series of assembly line by Tcl script.
2 pipeline series of table mark
Step 2: the posedge clk in synchronizing code being replaced with into posedge fire, and Click is added in code
The example of unit.Click unit is added according to the series of assembly line in the series for having been able to find assembly line inside step 1
Number, and be replaced with posedge fire1, posedge fire2 for the posedge clk of every level-one, and so on.
Step 3: the port clock in synchronizing code being replaced with into in_req, and is added in code some other
Other ports of Click.
It is asynchronous that the binding data based on Click are converted by the flow line circuit that above mode can be achieved with to synchronize
Circuit.
Claims (8)
1. a kind of method for converting asynchronous circuit for synchronous circuit, which comprises the steps of:
Step 1, compare the difference of pipeline synchronization circuit Yu the binding data asynchronous circuit based on Click unit；
Step 2, the binding number based on Click unit is converted for the Verilog code of pipeline synchronization circuit by Tcl script
According to the Verilog code of asynchronous circuit；
Step 3, asynchronous circuit is integrated by Synopsys Design Compiler (DC) tool.
2. the method for converting asynchronous circuit for synchronous circuit according to claim 1, which is characterized in that the synchronous flowing water
Line circuit and the difference of the binding data asynchronous circuit based on Click unit are:
1), pipeline synchronization circuit drives d type flip flop using global clock clk, and the binding data based on Click unit are asynchronous
Circuit drives d type flip flop using the pulse signal that Click unit generates；
2), additional Click unit is needed D to be driven to trigger to generate based on the binding data asynchronous circuit of Click unit
The pulse of device, and pipeline synchronization circuit should not.
3. the method for converting asynchronous circuit for synchronous circuit according to claim 1, which is characterized in that Click unit
Example is carried out, netlist is as follows:
1 //Click element
2 module click(in_req,in_ack,out_req,out_ack,fire,rst)；
3 input in_req,out_ack,rst；
4 output in_ack,out_req,fire；
5 wire left,right,qq,q,n1,n2,n3；
6 assign out_req=n1；
7 XOR2X1U1(.A(in_req),.B(in_ack),.Y(left))；
8 XNOR2X1U2(.A(n1),.B(out_ack),.Y(right))；
9 AND2X1U3(.A(left),.B(right),.Y(fire))；
10 INVX12U4(.A(n1),.Y(qq))；
11 DFFRHQX1U5(.D(qq),.CK(fire),.RN(rst),.Q(q))；
12 BUFX3buffer3(.A(n1),.Y(in_ack))；
13 BUFX3buffer1(.A(n2),.Y(n1))；
14 DLY1X1U6(.A(n3),.Y(n2))；
15 DLY3X1U7(.A(q),.Y(n3))；
16 endmodule
Click unit after exampleization prevents it to be changed during synthesis using set_dont_touch order.
4. the method for converting asynchronous circuit for synchronous circuit according to claim 1, which is characterized in that step 2 tool
Body includes:
Step 2.1: finding the pipeline series of pipeline synchronization circuit；
Step 2.2: the posedge clk in pipeline synchronization circuit code being replaced with into posedge fire, and in code
The example of Click unit is added；
Step 2.3: the port clock in pipeline synchronization circuit code being replaced with into in_req, and adds Click in code
Other ports of unit.
5. the method for converting asynchronous circuit for synchronous circuit according to claim 4, which is characterized in that the step 2.1
In, it is labeled in pipeline synchronization circuit code by mode as follows, mark is then found by Tcl script
Number is to find the series of assembly line:
6. the method for converting asynchronous circuit for synchronous circuit according to claim 4, which is characterized in that the step 2.2
In, the number of Click unit is added according to the series of assembly line, and the posedge clk of every level-one is successively replaced with
Posedge fire1, posedge fire2, and so on, wherein the series of assembly line is equal with Click unit number.
7. the method for converting asynchronous circuit for synchronous circuit according to claim 4, which is characterized in that the step 2.3
In, the in_req, in_ack, out_req of Click unit, the port out_ack are added in the statement part of code port.
8. the method for converting asynchronous circuit for synchronous circuit according to claim 1, which is characterized in that in the step 3,
Carrying out synthesis to asynchronous circuit by Synopsys Design Compiler (DC) tool is to convert pipeline synchronization code
For asynchronous pipeline code, then to Click unit set_dont_touch, then to fire signal creation clock, to realize
To circuit synthesis.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910123501.1A CN109815619B (en) | 2019-02-18 | 2019-02-18 | Method for converting synchronous circuit into asynchronous circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910123501.1A CN109815619B (en) | 2019-02-18 | 2019-02-18 | Method for converting synchronous circuit into asynchronous circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109815619A true CN109815619A (en) | 2019-05-28 |
| CN109815619B CN109815619B (en) | 2021-02-09 |
Family
ID=66606890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910123501.1A Active CN109815619B (en) | 2019-02-18 | 2019-02-18 | Method for converting synchronous circuit into asynchronous circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109815619B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112347722A (en) * | 2020-11-12 | 2021-02-09 | 盛科网络（苏州）有限公司 | Method and device for efficiently evaluating chip Feed-through flow stage number |
| CN112908379A (en) * | 2021-01-26 | 2021-06-04 | 北京航空航天大学 | Asynchronous circuit and system |
| CN113407239A (en) * | 2021-06-09 | 2021-09-17 | 中山大学 | Assembly line processor based on asynchronous single track |
| CN113407467A (en) * | 2021-07-19 | 2021-09-17 | 北京中科芯蕊科技有限公司 | Synchronous and asynchronous conversion interface and device based on Mousetrap |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101303643A (en) * | 2008-06-06 | 2008-11-12 | 清华大学 | Arithmetic logic unit using asynchronous circuit to implement |
| CN101593221A (en) * | 2008-05-28 | 2009-12-02 | 北京中电华大电子设计有限责任公司 | A kind of foreign lands' clock that prevents dynamically switches the Method and circuits of burr |
| CN102565665A (en) * | 2010-12-17 | 2012-07-11 | 炬力集成电路设计有限公司 | Circuit detection device and circuit detection method |
| US20150295579A1 (en) * | 2014-04-09 | 2015-10-15 | Altera Corporation | System Reset Controller Replacing Individual Asynchronous Resets |
| CN106250577A (en) * | 2015-06-03 | 2016-12-21 | 阿尔特拉公司 | The method of the depositor weight fixed cycle operator of the retaining zone between performing about the circuit in different clock zone associations |
| CN108537331A (en) * | 2018-04-04 | 2018-09-14 | 清华大学 | A kind of restructural convolutional neural networks accelerating circuit based on asynchronous logic |
-
2019
- 2019-02-18 CN CN201910123501.1A patent/CN109815619B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101593221A (en) * | 2008-05-28 | 2009-12-02 | 北京中电华大电子设计有限责任公司 | A kind of foreign lands' clock that prevents dynamically switches the Method and circuits of burr |
| CN101303643A (en) * | 2008-06-06 | 2008-11-12 | 清华大学 | Arithmetic logic unit using asynchronous circuit to implement |
| CN102565665A (en) * | 2010-12-17 | 2012-07-11 | 炬力集成电路设计有限公司 | Circuit detection device and circuit detection method |
| US20150295579A1 (en) * | 2014-04-09 | 2015-10-15 | Altera Corporation | System Reset Controller Replacing Individual Asynchronous Resets |
| CN106250577A (en) * | 2015-06-03 | 2016-12-21 | 阿尔特拉公司 | The method of the depositor weight fixed cycle operator of the retaining zone between performing about the circuit in different clock zone associations |
| CN108537331A (en) * | 2018-04-04 | 2018-09-14 | 清华大学 | A kind of restructural convolutional neural networks accelerating circuit based on asynchronous logic |
Non-Patent Citations (2)
| Title |
|---|
| 何安平等: "基于约束数据捆绑两相握手协议的8位异步Booth乘法器设计", 《电子学报》 * |
| 王友瑞等: "基于同步EDA工具的异步电路设计流程", 《计算机研究与发展》 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112347722A (en) * | 2020-11-12 | 2021-02-09 | 盛科网络（苏州）有限公司 | Method and device for efficiently evaluating chip Feed-through flow stage number |
| CN112347722B (en) * | 2020-11-12 | 2023-12-26 | 苏州盛科通信股份有限公司 | Method and device for efficiently evaluating chip Feed-through flow number of stages |
| CN112908379A (en) * | 2021-01-26 | 2021-06-04 | 北京航空航天大学 | Asynchronous circuit and system |
| CN113407239A (en) * | 2021-06-09 | 2021-09-17 | 中山大学 | Assembly line processor based on asynchronous single track |
| CN113407239B (en) * | 2021-06-09 | 2023-06-13 | 中山大学 | Pipeline processor based on asynchronous monorail |
| CN113407467A (en) * | 2021-07-19 | 2021-09-17 | 北京中科芯蕊科技有限公司 | Synchronous and asynchronous conversion interface and device based on Mousetrap |
| CN113407467B (en) * | 2021-07-19 | 2023-05-30 | 北京中科芯蕊科技有限公司 | Synchronous-asynchronous conversion interface and device based on Mouserap |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109815619B (en) | 2021-02-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109815619A (en) | A method of asynchronous circuit is converted by synchronous circuit | |
| Nowick et al. | Asynchronous design—Part 1: Overview and recent advances | |
| Yakovlev et al. | Advances in asynchronous logic: From principles to GALS & NoC, recent industry applications, and commercial CAD tools | |
| Sjogren et al. | Interfacing synchronous and asynchronous modules within a high-speed pipeline | |
| US8669779B2 (en) | Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits | |
| CN106663078A (en) | Delay circuits and related systems and methods | |
| US20150023458A1 (en) | Clock and data recovery using dual manchester encoded data streams | |
| US20150089108A1 (en) | Clock signals for dynamic reconfiguration of communication link bundles | |
| US20120306893A1 (en) | Pre-emphasis control circuit | |
| US8578074B2 (en) | First in first out device and method thereof | |
| US8466816B2 (en) | Method and apparatus for serializing bits | |
| Soderquist | Globally updated mesochronous design style | |
| CN104184456A (en) | Low-frequency multiphase differential clock tree type serializer with high speed and low power consumption for IO interface | |
| CN109871611A (en) | A kind of matched method of asynchronous circuit automatically delaying | |
| CN116318601A (en) | Frame alignment recovery for high speed signaling interconnect | |
| Mekie et al. | Interface design for rationally clocked GALS systems | |
| Wu et al. | A method to transform synchronous pipeline circuits to bundled-data asynchronous circuits using commercial EDA tools | |
| EP3173895B1 (en) | Clock tree implementation method, system-on-chip and computer storage medium | |
| Ferretti | Single-track asynchronous pipeline template | |
| US8351489B2 (en) | Two-phase return-to-zero asynchronous transceiver | |
| CN106201950B (en) | Method for SOC asynchronous clock domain signal interface | |
| CN101860359A (en) | Clock generation system and clock frequency division module | |
| CN101295970B (en) | Trigger and shifting register | |
| CN105958982B (en) | The circuit and method of clock useful signal in advance | |
| Zhou | Investigation of asynchronous pipeline circuits based on bundled-data encoding: Implementation styles, behavioral modeling, and timing analysis |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |