CN112908379A - Asynchronous circuit and system - Google Patents

Asynchronous circuit and system Download PDF

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CN112908379A
CN112908379A CN202110102087.3A CN202110102087A CN112908379A CN 112908379 A CN112908379 A CN 112908379A CN 202110102087 A CN202110102087 A CN 202110102087A CN 112908379 A CN112908379 A CN 112908379A
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circuit
mtj
state
asynchronous
write
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CN112908379B (en
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邓尔雅
魏少芊
赵巍胜
康旺
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Beihang University
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1693—Timing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mram Or Spin Memory Techniques (AREA)

Abstract

The invention provides an asynchronous circuit and a system, which adopt a plurality of nonvolatile memory cells and a plurality of completion detection cells; each completion detection unit performs data interaction with an adjacent previous nonvolatile memory unit and an adjacent next nonvolatile memory unit, wherein the data interaction includes: after the calculation unit in the next adjacent nonvolatile memory unit finishes the memory calculation, the nonvolatile memory unit sends a completion response signal to the completion detection unit, and after the completion detection unit processes the request signal, the completion detection unit sends a register response signal to the previous adjacent nonvolatile memory unit.

Description

Asynchronous circuit and system
Technical Field
The present invention relates to the field of semiconductors, and more particularly, to an asynchronous circuit and system.
Background
In the current large scale integrated circuit chip, the clock control is mainly synchronous clock control, that is, all operations are operated under the control of the same clock signal or wait for operation. In the circuit, in order to optimize a clock signal, the clock signal is constructed into a clock tree through a plurality of buffer units to control different circuit units. As the scale of the chip circuit becomes larger, the scale of the clock tree becomes larger. The influence of clock delay, clock skew and other problems brought by the clock tree on the circuit operation is gradually not negligible. And the clock power consumption is also increasing in proportion to the total circuit power consumption.
In order to solve the above problems, circuit designers propose asynchronous circuits, in which different circuit operation units are controlled by different clock signals to form a Delay Insensitive (DI) circuit, and a feedback signal (handshake signal: K) is established between the circuit unitsoAnd Ki) And each circuit unit can complete operation in sequence.
Even though the idea of asynchronous circuits can save a part of the clock power consumption, the static power consumption due to CMOS leakage currents is unavoidable for all CMOS based circuits. To solve the problem of static power consumption of CMOS circuits, researchers have proposed many new technologies, such as spintronic devices. The patent applies the spinning electronic device to an asynchronous circuit to realize a nonvolatile asynchronous circuit production line. The asynchronous circuit assembly line can solve the problem of clock power consumption and the problem of static power consumption, and greatly saves the power consumption of the circuit.
Disclosure of Invention
To solve at least one of the above problems, a first aspect of the present invention provides an asynchronous circuit comprising: a plurality of nonvolatile memory cells and a plurality of completion detection cells; each completion detection unit performs data interaction with an adjacent previous nonvolatile memory unit and an adjacent next nonvolatile memory unit, wherein the data interaction includes:
after the calculation unit in the next adjacent nonvolatile storage unit finishes the memory calculation, the nonvolatile storage unit sends a completion response signal to the completion detection unit, and after the completion detection unit processes the response signal, the completion detection unit sends a register response signal to the previous adjacent nonvolatile storage unit.
In a preferred embodiment, the non-volatile memory cells comprise at least one group of MRAM non-volatile memory cells.
In a preferred embodiment, the MRAM nonvolatile memory cell comprises:
the differential amplification reading circuit is used for reliably reading the stored data;
a write completion detection circuit for controlling the write circuit to close;
an MTJ write circuit for changing the state of the MTJ device and writing input data into the MTJ device;
a pair of MTJ cells connected in parallel, the MTJ cells coupled with the differential amplification read circuit and the MTJ write circuit.
In a preferred embodiment, the MRAM nonvolatile memory cell comprises:
the pre-charging reading circuit is used for reliably reading the stored data;
a write completion detection circuit for controlling the write circuit to close;
an MTJ write circuit for changing the state of the MTJ device and writing input data into the MTJ device;
a pair of MTJ cells connected in parallel, the MTJ cells coupled with the precharge read circuit and the MTJ write circuit.
In a preferred embodiment, the MTJ cell comprises: the transistor comprises a pair of MTJ magnetic tunnel junctions connected in parallel and a transistor coupled with each MTJ magnetic tunnel junction, wherein the MTJ magnetic tunnel junctions comprise a reference layer, a tunneling layer and a free layer which are arranged in sequence, the drain terminal of the transistor coupled with the MTJ magnetic tunnel junctions is coupled with the pre-charge reading circuit, and the control terminal of the transistor is coupled with the MTJ writing circuit.
In a preferred embodiment, the write completion detection circuit is specifically configured to detect whether the state of the MTJ is completely inverted, and turn off the MTJ write circuit if the state of the MTJ is consistent with the state required by the input data.
In a preferred embodiment, further comprising: a combinational logic cell comprising a threshold gate for logical computation of input data within four variables.
In a preferred embodiment, the threshold gate state comprises a first state and a second state, wherein when the number of "1" in the input signal is higher than the threshold gate threshold, the threshold gate is set to the first state; when all the input signals are '0', the threshold gate is set to be in a second state; otherwise the threshold gate maintains the previous state.
In a preferred embodiment, the non-volatile memory unit includes two groups of MRAM non-volatile memory units, and the combinational logic unit determines the data stored in each bit according to a two-dimensional array output by the two groups of MRAM non-volatile memory units.
In a second aspect, an embodiment of the present invention provides an asynchronous device, including: the asynchronous circuit of any preceding embodiment.
The invention has the beneficial effects that:
the invention provides an asynchronous circuit, which adopts a plurality of nonvolatile memory cells and a plurality of completion detection cells; each completion detection unit performs data interaction with an adjacent previous nonvolatile memory unit and an adjacent next nonvolatile memory unit, wherein the data interaction includes: after the calculation unit in the next adjacent nonvolatile storage unit finishes the memory calculation, the nonvolatile storage unit sends a completion response signal to the completion detection unit, and after the completion detection unit processes the request signal, the completion detection unit sends a register response signal to the previous adjacent nonvolatile storage unit. The addition of the write completion detection unit and the asynchronous circuit control the data transmission mode among all units by using handshake signals, thereby solving the problem of random write of MTJ and improving the reliability of the circuit. In general, this non-volatile asynchronous pipeline architecture can provide ultra-low power and high reliability storage, while non-volatile storage can quickly recover data in the event of a sudden power loss.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of an asynchronous circuit according to an embodiment of the present invention;
FIG. 2 is a signal flow diagram of an asynchronous circuit according to an embodiment of the present invention;
fig. 3 is a waveform diagram of an asynchronous circuit signal flow simulation according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present invention may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element (or other) component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
In the current large scale integrated circuit chip, the clock control is mainly synchronous clock control, that is, all operations are operated under the control of the same clock signal or wait for operation. In the circuit, in order to optimize a clock signal, the clock signal is constructed into a clock tree through a plurality of buffer units to control different circuit units. As the scale of the chip circuit becomes larger, the scale of the clock tree becomes larger. The influence of clock delay, clock skew and other problems brought by the clock tree on the circuit operation is gradually not negligible. And the clock power consumption is also increasing in proportion to the total circuit power consumption.
In order to solve the above problems, circuit designers propose asynchronous circuits, in which different circuit operation units are controlled by different clock signals to form a Delay Insensitive (DI) circuit, and a feedback signal (handshake signal: K) is established between the circuit unitsoAnd Ki) And each circuit unit can complete operation in sequence.
Even though the idea of asynchronous circuits can save a part of the clock power consumption, the static power consumption due to CMOS leakage currents is unavoidable for all CMOS based circuits.
In order to solve the above problem, a first aspect of the present invention provides an asynchronous circuit, as shown in fig. 1, including: a plurality of nonvolatile memory cells and a plurality of completion detection cells; each completion detection unit performs data interaction with an adjacent previous nonvolatile memory unit and an adjacent next nonvolatile memory unit, wherein the data interaction includes:
after the calculation unit in the next adjacent nonvolatile storage unit finishes the memory calculation, the nonvolatile storage unit sends a completion response signal to the completion detection unit, and after the completion detection unit processes the request signal, the completion detection unit sends a register response signal to the previous adjacent nonvolatile storage unit.
The invention adopts the nonvolatile memory unit to replace a register unit and a calculating unit in an asynchronous circuit, and the nonvolatile memory unit provides static power consumption which is approximately 0 for an asynchronous pipeline system. The addition of the write completion detection unit and the asynchronous circuit control the data transmission mode among all units by using handshake signals, thereby solving the problem of random write of MTJ and improving the reliability of the circuit. In general, this non-volatile asynchronous pipeline architecture can provide ultra-low power and high reliability storage, while non-volatile storage can quickly recover data in the event of a sudden power loss. It will be appreciated that the signal K is requested via a registeriDetermine if the unit needs to compute when KiWhen the signal is effective, the MRAM nonvolatile memory cell reads and calculates data; storing data through an MTJ array in an MRAM nonvolatile memory cell, and completing data calculation through the state of a calculation unit transistor in a configuration circuit; the computing unit returns K after completing the data computationoSignal to completion detection unit, completion detection unit complete to KoAfter the signal processing, the MRAM unit of the previous stage receives the response signal of the current stage.
In some preferred embodiments, the non-volatile memory cells include at least one group of MRAM non-volatile memory cells.
In particular, the present invention may employ a set of MRAM nonvolatile memory cells. The MRAM nonvolatile memory cell stores either a logic '0' or '1'.
In a preferred embodiment, the MRAM nonvolatile memory cell comprises:
the differential amplification reading circuit is used for reliably reading the stored data;
a write completion detection circuit for controlling the write circuit to close;
an MTJ write circuit for changing the state of the MTJ device and writing input data into the MTJ device;
a pair of MTJ cells connected in parallel, the MTJ cells coupled with the differential amplification read circuit and the MTJ write circuit.
In a preferred embodiment, the MRAM nonvolatile memory cell comprises: the pre-charging reading circuit is used for reliably reading the stored data; a write completion detection circuit for controlling the write circuit to close; an MTJ write circuit for changing the state of the MTJ device and writing input data into the MTJ device; a pair of MTJ cells connected in parallel, the MTJ cells coupled with the precharge read circuit and the MTJ write circuit. The present embodiment reads data in the MTJ using a precharge read circuit. The precharge read circuit can save the life of the MTJ device compared to other differential amplification read circuits.
In a preferred embodiment, the MTJ cell comprises: the transistor comprises a pair of MTJ magnetic tunnel junctions connected in parallel and a transistor coupled with each MTJ magnetic tunnel junction, wherein the MTJ magnetic tunnel junctions comprise a reference layer, a tunneling layer and a free layer which are arranged in sequence, the drain terminal of the transistor coupled with the MTJ magnetic tunnel junctions is coupled with the pre-charge reading circuit, and the control terminal of the transistor is coupled with the MTJ writing circuit.
In a preferred embodiment, the write completion detection circuit is specifically configured to detect whether the state of the MTJ is completely inverted, and turn off the MTJ write circuit if the state of the MTJ is consistent with the state required by the input data. The completion detection circuit is used for detecting whether the state of the MTJ is completely turned or not in time, once the state of the MTJ is consistent with the state required by input data, the MTJ writing circuit can be closed in time by using a completion detection signal, and the purpose of saving writing power consumption is achieved.
In a preferred embodiment, further comprising: a combinational logic cell comprising a threshold gate for logical computation of input data within four variables.
In a preferred embodiment, the threshold gate state comprises a first state and a second state, wherein when the number of "1" in the input signal is higher than the threshold gate threshold, the threshold gate is set to the first state; when all the input signals are '0', the threshold gate is set to be in a second state; otherwise the threshold gate maintains the previous state.
In a preferred embodiment, the non-volatile memory unit includes two groups of MRAM non-volatile memory units, and the combinational logic unit determines the data stored in each bit according to a two-dimensional array output by the two groups of MRAM non-volatile memory units. In this embodiment, the non-volatile memory unit includes two groups of MRAM non-volatile memory units, and the combination control unit determines that each bit stores '0' or '1' according to the two-dimensional array output by the two groups of MRAM non-volatile memory units. The two groups of MRAM nonvolatile memory cells are independent of each other.
In some preferred embodiments, as shown in fig. 3, the present invention may employ a dual-rail signal to represent either '0' or '1', as follows: when D is present0、D1Respectively '0' and '1', representing a logical '0'; when D is present0、D1Respectively '1' and '0', representing logic 1; when D is present0、D1Respectively '0' and '0', indicating a NULL state (NULL state); d0And D1Not allowed to be '1' at the same time.
Specifically, the invention provides a nonvolatile asynchronous circuit structure which adopts a plurality of nonvolatile memory cells, a logic operation unit and a plurality of completion detection units. And the two adjacent nonvolatile storage units realize the interaction of control signals by completing the detection unit. The data of the memory cell enters the combinational logic unit under the control of the control signal. The asynchronous pipeline system adopts a nonvolatile storage unit built by MTJ, the stored data is nonvolatile, and the power failure is easy to recover. And because the asynchronous system distributes time according to the actual running time of each unit, the problem of random write-in of the MTJ is solved, and the reliability of the circuit is improved.
In some embodiments, the MTJ cell comprises: the transistor comprises a pair of MTJ magnetic tunnel junctions connected in parallel and a transistor coupled with each MTJ magnetic tunnel junction, wherein the MTJ magnetic tunnel junctions comprise a reference layer, a tunneling layer and a free layer which are arranged in sequence, the drain terminal of the transistor coupled with the MTJ magnetic tunnel junctions is coupled with the pre-charge reading circuit, and the control terminal of the transistor is coupled with the MTJ writing circuit.
Further comprising: a combinational logic cell, the combinational logic cell being entirely composed of basic logic gates in non-conventional logic: a threshold gate component. The combinational logic unit is used for logic calculation of input data within four variables.
The combinational logic unit includes: a plurality of threshold gates.
The threshold gate outputs a result of the response according to the number of input high levels. When the number of input high levels (i.e. the number of input '1') is greater than the threshold required by the threshold gate, the threshold gate outputs '1'; when the inputs are all low level (namely '0'), the threshold gate outputs '0'; when the number of input high levels is between 0 and the threshold gate threshold, the threshold gate remains unchanged from the previous state.
In this embodiment, the non-volatile memory unit includes two groups of MRAM non-volatile memory units, and the combinational logic unit determines that each bit stores '0' or '1' according to a two-dimensional array output by the two groups of MRAM non-volatile memory units. In this example, the following table shows:
double-track signal comparison table
DATA‘0’ DATA‘1’ NULL Illegal
D
0 1 0 0 1
D 1 0 1 0 1
D0，D1Is a dual rail input signal (i.e., 1-bit data is represented by two lines);
when (D)0，D1) When (1, 0), it represents logic '0' (DATA '0'); others are available in the same way.
As shown in fig. 2, the signal flow of the present invention is as follows:
control circuit according to D0、D1And KiCalculating a write enable signal WE according to the value of the write enable signal WE; the write circuit being responsive to D under control of the WE signal0And D1The value of (1) is configured to enable currents in different directions to flow through the MTJ, and data is written into the MTJ; after the write operation is completed, the write detection circuit detects the change, the write detection circuit changes the value of the WC signal and controls the write circuit to close; control logic circuit based on WC and KiThe signal calculates a read enable signal RE to control the PCSA circuit to read the data stored in the MTJ.
Out0、Out1Is an output signal;
Kois a response signal
D0、D1Is input intoA signal;
Kiis a request signal;
WC is a finished detection signal;
RE is a read enable signal;
WE is a write enable signal;
PCSA: a precharge read circuit;
control Logic: a control logic module;
write Completion Detector: a write-out completion detection circuit;
write Driver: a write circuit;
it can be seen that in the present invention, the main advantages of the present structure are: the non-volatile memory unit provides a static power consumption of approximately 0 for the asynchronous pipeline system. The addition of the write completion detection unit and the asynchronous circuit control the data transmission mode among all units by using handshake signals, thereby solving the problem of random write of MTJ and improving the reliability of the circuit. In general, this non-volatile asynchronous pipeline architecture can provide ultra-low power and high reliability storage, while non-volatile storage can quickly recover data in the event of a sudden power loss.
Further, the present invention also provides an asynchronous device, which includes the asynchronous circuit as described in the above embodiments.
The asynchronous device has the advantages that: the non-volatile memory unit provides a static power consumption of approximately 0 for the asynchronous pipeline system. The addition of the write completion detection unit and the asynchronous circuit control the data transmission mode among all units by using handshake signals, thereby solving the problem of random write of MTJ and improving the reliability of the circuit. In general, this non-volatile asynchronous pipeline architecture can provide ultra-low power and high reliability storage, while non-volatile storage can quickly recover data in the event of a sudden power loss.
Further, the present invention also provides an asynchronous system, which includes the asynchronous circuit as described in the above embodiments.
The asynchronous system has the advantages that: the non-volatile memory unit provides a static power consumption of approximately 0 for the asynchronous pipeline system. The addition of the write completion detection unit and the asynchronous circuit control the data transmission mode among all units by using handshake signals, thereby solving the problem of random write of MTJ and improving the reliability of the circuit. In general, this non-volatile asynchronous pipeline architecture can provide ultra-low power and high reliability storage, while non-volatile storage can quickly recover data in the event of a sudden power loss.
In the description of the present specification, reference to the description of the terms "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present specification. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example.
Furthermore, the various embodiments or examples and features of the various embodiments or examples described in this specification can be combined and combined by those skilled in the art without contradiction. The above description is only an embodiment of the present disclosure, and is not intended to limit the present disclosure. Various modifications and changes may occur to those skilled in the art to which the embodiments of the present disclosure pertain. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present specification should be included in the scope of the claims of the embodiments of the present specification.

Claims (10)

1. An asynchronous circuit, comprising: a plurality of nonvolatile memory cells and a plurality of completion detection cells; each completion detection unit performs data interaction with an adjacent previous nonvolatile memory unit and an adjacent next nonvolatile memory unit, wherein the data interaction includes:
after the calculation unit in the next adjacent nonvolatile storage unit finishes the memory calculation, the nonvolatile storage unit sends a completion response signal to the completion detection unit, and after the completion detection unit processes the response signal, the completion detection unit sends a register response signal to the previous adjacent nonvolatile storage unit.
2. The asynchronous circuit of claim 1, wherein the non-volatile memory cells comprise at least one group of MRAM non-volatile memory cells.
3. The asynchronous circuit of claim 2, wherein the MRAM nonvolatile storage cell comprises:
the differential amplification reading circuit is used for reliably reading the stored data;
a write completion detection circuit for controlling the write circuit to close;
an MTJ write circuit for changing the state of the MTJ device and writing input data into the MTJ device;
a pair of MTJ cells connected in parallel, the MTJ cells coupled with the differential amplification read circuit and the MTJ write circuit.
4. The asynchronous circuit of claim 2, wherein the MRAM nonvolatile storage cell comprises:
the pre-charging reading circuit is used for reliably reading the stored data;
a write completion detection circuit for controlling the write circuit to close;
an MTJ write circuit for changing the state of the MTJ device and writing input data into the MTJ device;
a pair of MTJ cells connected in parallel, the MTJ cells coupled with the precharge read circuit and the MTJ write circuit.
5. The asynchronous circuit of claim 4, wherein the MTJ cell comprises: the transistor comprises a pair of MTJ magnetic tunnel junctions connected in parallel and a transistor coupled with each MTJ magnetic tunnel junction, wherein the MTJ magnetic tunnel junctions comprise a reference layer, a tunneling layer and a free layer which are arranged in sequence, the drain terminal of the transistor coupled with the MTJ magnetic tunnel junctions is coupled with the pre-charge reading circuit, and the control terminal of the transistor is coupled with the MTJ writing circuit.
6. The asynchronous circuit of claim 4, wherein the write completion detection circuit is configured to detect whether the MTJ state has been flipped, and to turn off the MTJ write circuit if the MTJ state matches a state required by the input data.
7. The asynchronous circuit of claim 1, further comprising: a combinational logic cell comprising a threshold gate for logical computation of input data within four variables.
8. The asynchronous circuit of claim 7, wherein the threshold gate state comprises a first state and a second state, wherein the threshold gate is set to the first state when the number of "1" s in the input signal is greater than the threshold gate threshold; when all the input signals are '0', the threshold gate is set to be in a second state; otherwise the threshold gate maintains the previous state.
9. The asynchronous circuit of claim 7, wherein the non-volatile memory cells comprise two groups of MRAM non-volatile memory cells, and wherein the combinational logic unit determines the data stored by each bit based on a two-dimensional array of outputs from the two groups of MRAM non-volatile memory cells.
10. An asynchronous system, comprising: an asynchronous circuit as claimed in any one of claims 1 to 9.
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