CN110098897B - Serial communication method, device, computer equipment and storage medium - Google Patents
Serial communication method, device, computer equipment and storage medium Download PDFInfo
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- CN110098897B CN110098897B CN201910340606.2A CN201910340606A CN110098897B CN 110098897 B CN110098897 B CN 110098897B CN 201910340606 A CN201910340606 A CN 201910340606A CN 110098897 B CN110098897 B CN 110098897B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0033—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the transmitter
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0036—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the receiver
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
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Abstract
The application relates to a serial communication method, a serial communication device, a computer device and a storage medium. The method comprises the following steps: a receiving end acquires current filtering data output by a filter; when a preset state in the current filtering data is detected, obtaining effective data after the preset state in the current filtering data; when the receiving of the effective data is finished and the receiving delay time is waited, the receiving end obtains the next filtering data output by the filter; and taking the next filtering data as the current filtering data, and when the preset state in the current filtering data is detected, acquiring effective data after the preset state in the current filtering data. The data is filtered through the filter, the receiving end only needs to capture the current filtering data output by the filter, when the preset state in the current filtering data is detected, the effective data can be obtained, the time length for the receiving end to receive the data is prolonged, namely delayed receiving is carried out, and therefore the accuracy of the data received by the receiving end can be ensured.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a serial communication method, an apparatus, a computer device, and a storage medium.
Background
In the industrial field, serial communication is widely used, and commonly used serial communication modes include communication modes such as RS232, RS485, RS422, CAN and the like. The main control chip for serial communication comprises a singlechip, an ARM, a DSP, an FPGA and the like. The single chip microcomputer, the ARM and the DSP generally comprise a hard core serial processing module inside, the hard core serial processing module receives data and then informs a CPU to receive the data, or after the CPU sends the data to the serial processing module, the serial processing module can be responsible for sending the data out in sequence. The FPGA generally does not have the serial hardmac processing module, and a user needs to write a program by himself to realize the functions of the serial receiving and sending module. The serial data typically includes a start bit, 5 to 8 bits of data, and 1, 1.5, or 2 bits of a stop bit. As shown in fig. 1.
In general, after capturing the falling edge of the start bit, the FPGA starts calculation, collects one bit of data every baud rate period, stops collection until the stop bit, and waits for the next frame of data. Normally, the FPGA can normally acquire the falling edge of the start bit, but since the serial communication is asynchronous, the sending end sends first, the receiving end may start capturing in the data area, and capture the falling edge of the data segment, so that the wrong data may be received and the wrong reception may be kept all the time.
Disclosure of Invention
In view of the above, it is necessary to provide a serial communication method, apparatus, computer device and storage medium for solving the above technical problems.
A method of serial communication, the method comprising:
a receiving end acquires current filtering data output by a filter;
when a preset state in the current filtering data is detected, obtaining effective data after the preset state in the current filtering data, wherein the preset state is a falling edge state;
when the receiving end waits for the receiving delay time after the effective data is received, the receiving end acquires the next filtering data output by the filter;
taking the next filtering data as the current filtering data;
the obtaining, by the receiving end, current filtering data output by the filter includes:
the receiving end acquires the current filtering data after the IO state of the current filtering data is acquired by the filter with the Baud rate set as a preset multiple and is filtered in a counter counting mode;
when the counter is smaller than or equal to the preset multiple and the IO port state is a high level state, increasing the value of the counter by a preset specific value;
when the counter is larger than 0 and the IO port state is a low level state, the value of the counter is decreased by the preset specific value;
when the numerical value of the counter is smaller than a preset threshold value, the output signal of the filter is a first state signal;
and when the numerical value of the counter is greater than the difference value between the preset multiple and the preset threshold value, the output signal of the filter is a second state signal.
A serial communication apparatus, the apparatus comprising a receiving end, the receiving end comprising:
the filtering module is used for acquiring current filtering data output by the filter;
the data receiving module is used for acquiring effective data after a preset state in the current filtering data when the preset state in the current filtering data is detected, wherein the preset state is a falling edge state; when the receiving end waits for the receiving delay time after the effective data is received, the receiving end acquires the next filtering data output by the filter; taking the next filtering data as the current filtering data;
the filtering module is specifically used for acquiring current filtering data output after an IO state of the current filtering data is acquired by a filter with a baud rate set as a preset multiple and is filtered in a counter counting mode, when the counter is smaller than or equal to the preset multiple and the IO port state is a high level state, the value of the counter is increased by a preset specific value, and when the counter is larger than 0 and the IO port state is a low level state, the value of the counter is decreased by the preset specific value;
the filtering module is further specifically configured to, when the value of the counter is smaller than a preset threshold, output signals of the filter are first state signals, and when the value of the counter is larger than a difference between the preset multiple and the preset threshold, output signals of the filter are second state signals.
A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the following steps when executing the computer program:
a receiving end acquires current filtering data output by a filter;
when a preset state in the current filtering data is detected, obtaining effective data after the preset state in the current filtering data, wherein the preset state is a falling edge state;
when the receiving end waits for the receiving delay time after the effective data is received, the receiving end acquires the next filtering data output by the filter;
taking the next filtering data as the current filtering data;
the obtaining, by the receiving end, current filtering data output by the filter includes:
the receiving end acquires the current filtering data after the IO state of the current filtering data is acquired by the filter with the Baud rate set as a preset multiple and is filtered in a counter counting mode;
when the counter is smaller than or equal to the preset multiple and the IO port state is a high level state, increasing the value of the counter by a preset specific value;
when the counter is larger than 0 and the IO port state is a low level state, the value of the counter is decreased by the preset specific value;
when the numerical value of the counter is smaller than a preset threshold value, the output signal of the filter is a first state signal;
and when the numerical value of the counter is greater than the difference value between the preset multiple and the preset threshold value, the output signal of the filter is a second state signal.
A computer-readable storage medium, on which a computer program is stored which, when executed by a processor, carries out the steps of:
a receiving end acquires current filtering data output by a filter;
when a preset state in the current filtering data is detected, obtaining effective data after the preset state in the current filtering data, wherein the preset state is a falling edge state;
when the receiving end waits for the receiving delay time after the effective data is received, the receiving end acquires the next filtering data output by the filter;
taking the next filtering data as the current filtering data;
the obtaining, by the receiving end, current filtering data output by the filter includes:
the receiving end acquires the current filtering data after the IO state of the current filtering data is acquired by the filter with the Baud rate set as a preset multiple and is filtered in a counter counting mode;
when the counter is smaller than or equal to the preset multiple and the IO port state is a high level state, increasing the value of the counter by a preset specific value;
when the counter is larger than 0 and the IO port state is a low level state, the value of the counter is decreased by the preset specific value;
when the numerical value of the counter is smaller than a preset threshold value, the output signal of the filter is a first state signal;
and when the numerical value of the counter is greater than the difference value between the preset multiple and the preset threshold value, the output signal of the filter is a second state signal.
The serial communication method, the serial communication device, the computer equipment and the storage medium are provided. The method comprises the following steps: a receiving end acquires current filtering data output by a filter; when a preset state in the current filtering data is detected, obtaining effective data after the preset state in the current filtering data; when the receiving end waits for the receiving delay time after the effective data is received, the receiving end acquires the next filtering data output by the filter; and taking the next filtering data as the current filtering data, and when a preset state in the current filtering data is detected, obtaining effective data after the preset state in the current filtering data. The data is filtered through the filter, the receiving end only needs to capture the current filtering data output by the filter, when a preset state in the current filtering data is detected, effective data in the current filtering data can be obtained, the time length for the receiving end to receive the data is prolonged, namely delayed receiving is carried out, and under the condition that the receiving end and the sending end are not synchronous, even if the first frame data received by the receiving end is wrong, correct receiving of the next frame data of the receiving end can be guaranteed through a delayed receiving mode, so that the accuracy of the data received by the receiving end can be guaranteed.
Drawings
FIG. 1 is a diagram illustrating a serial communication method according to a conventional technique according to an embodiment;
FIG. 2 is a diagram of an exemplary serial communication method;
FIG. 3 is a flow diagram illustrating a serial communication method in one embodiment;
fig. 4 is a schematic flowchart illustrating a process of sending data by a sending end in an embodiment;
FIG. 5 is a flow chart illustrating a receiving end receiving data according to an embodiment;
FIG. 6 is a block diagram showing the structure of a serial communication apparatus according to an embodiment;
FIG. 7 is a diagram illustrating an internal structure of a computer device according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The serial communication method provided by the application can be applied to the application environment shown in fig. 2. Wherein the transmitting end 202 communicates with the receiving end 204. The sending end 202 may send data to be sent to the receiving end 204, a filter in the receiving end 204 may receive the data sent by the sending end 202 and perform filtering processing, and output the filtered data to the receiving end 204, and the receiving end 204 sequentially receives the data sent by the sending end 202.
In one embodiment, as shown in fig. 3, there is provided a serial communication method including the steps of:
The sending end can send data, and after the filter acquires the data sent by the sending end, the filter can filter the data sent by the sending end.
In one embodiment, the receiving end obtains current filtering data output by the filter, including: the receiving end acquires the current filtering data after the IO state of the current filtering data is acquired by the filter with the Baud rate set as the preset multiple and is filtered in a counter counting mode.
The input signal of the pre-designed digital filter has an IO port state signal, and the high-frequency clock outputs the filtered IO signal. The baud rate is expressed by the number of the code element symbols transmitted every second, is an index for measuring the data transmission rate, is expressed by the number of times of the change of the carrier modulation state in unit time, can set the baud rate of the filter as a preset multiple N, collects the IO state of the data transmitted by the transmitting end through the high frequency with the baud rate being N times, and can count through a counter.
In one embodiment, the serial communication method further includes: when the counter is smaller than or equal to the preset multiple and the IO port state is a high level state, increasing the value of the counter by a preset specific value; when the counter is larger than 0 and the IO port state is a low level state, the value of the counter is decreased by a preset specific value.
When the data sent by the sending end is filtered through the filter with the baud rate being the preset multiple N, the filter also collects the IO state of the data sent by the sending end, counts the IO state and carries out filtering processing in a counting mode. Specifically, when the counter is less than or equal to the preset multiple and the IO port state is the high level state, the value of the counter is increased by a preset specific value, and when the counter is greater than 0 and the IO port state is the low level state, the value of the counter is decreased by the preset specific value. Assuming that the preset multiple N is 256, the preset specific value is 1, and the value of the counter is num, when num is less than or equal to N and the input IO port is in the high level state, the value of num may be increased by one, and when num is greater than 0 and the IO port is in the low level state, the value of num may be decreased by one.
In one embodiment, the serial communication method further includes: when the value of the counter is smaller than a preset threshold value, the output signal of the filter is a first state signal; when the value of the counter is larger than the difference value between the preset multiple and the preset threshold value, the output signal of the filter is a second state signal.
When the counter is smaller than or equal to the preset multiple and the IO port state is a high level state, increasing the value of the counter by a preset specific value; when the counter is greater than 0 and the IO port state is a low level state, after the value of the counter is determined by decreasing the value of the counter by the preset specific value, the output signal can be determined to be a first state signal or a second state signal according to the magnitude relation between the value and the preset threshold, where the first state signal is 0 and the second state signal is 1. The preset threshold value is N, when the numerical value num of the counter is smaller than N, the output signal of the filter is 0, when num is larger than (N-N), the input signal of the filter is 1, and in this way, the data sent by the sending end is filtered to eliminate the interference signal.
Step 303, when the receiving end waits for the receiving delay time after the valid data is received, the receiving end obtains the next filtering data output by the filter.
Step 304, taking the next filtering data as the current filtering data, and when detecting the preset state in the current filtering data, obtaining the effective data after the preset state in the current filtering data.
After the data sent by the sending end is filtered by the filter, signals which can interfere the data sent by the sending end can be eliminated, so that the anti-interference capability of serial communication can be improved. The receiving end can obtain current filtering data filtered by the filter, and when a preset state in the current filtering data is detected, the receiving end can obtain effective data after the preset state in the current filtering data. The preset state may be a falling edge state, that is, after the receiving end detects a falling edge in the current filtered data, the receiving end may start receiving the current filtered data. Valid data refers to data for a period of time after a falling edge is detected.
After the receiving end finishes receiving the effective data, the receiving end can wait for the receiving delay time to obtain the next filtering data output by the filter, the next filtering data can be used as the current filtering data, and the step of obtaining the effective data after the preset state in the current filtering data when the preset state in the current filtering data is detected is carried out, so that the data are circularly received.
In one embodiment, before the receiving end obtains the current filtered data output by the filter, the method further includes: the sending end sends the current data to be filtered, the filter filters the current data to be filtered to obtain the current filtered data, and the sending end sends the next data to be filtered after the current data to be filtered is finished and waits for the sending delay time.
When sending data, the sending end sends the data to be transmitted in sequence, for example, the sending end may send the data frame by frame. After the sending of one frame of data is finished, the sending end sends the second frame of data after waiting for the sending delay time, and sends the third frame of data after the sending is finished, so that the sending end sends all the data needing to be sent. The sending delay time is a time preset by a technician, and can be correspondingly changed according to actual needs. That is, the currently transmitted data may be used as the first frame data each time, and the next frame data of the first frame data may be used as the second frame data, so that the first frame data is transmitted first each time when data transmission is performed, and the second frame data is transmitted after waiting for the transmission delay time until all data transmission is completed. Therefore, when receiving data, the filter also acquires the first frame data sent by the sending end first, and after the first frame data is acquired, waits for the sending delay time period, and then acquires the next frame data sent by the sending end. The delay of sending by the sending end and the delay of receiving by the filter will also result in the delay of receiving by the receiving end, thus achieving the effect of synchronization of the sending end and the receiving end.
In one embodiment, the method further comprises: when the receiving end captures a falling edge, the receiving end receives first frame data; and the receiving end waits for the receiving delay time after receiving the second frame data.
After the sending end sends the first frame data, the receiving end can start to prepare for receiving the data. When the receiving end captures a falling edge, it indicates that data transmission is started, the receiving end can start to prepare for receiving data, after the receiving end receives first frame data sent by the sending end, the receiving end can wait for a receiving delay time first and then start to prepare for receiving second frame data, namely after the receiving end receives data once, the receiving end can wait for the receiving delay time first and then receive the next data. The receiving delay time is the same as the sending delay time, and both belong to preset set time of technicians, and can be set according to actual needs.
This has the advantage that when the sending device and the receiving device are powered on at different times or when the initialization time is different, the sending terminal and the receiving terminal are not synchronized, and the captured falling edge is not necessarily the start bit. The effect of synchronization of the sending end and the receiving end is achieved through delayed sending and delayed receiving.
In one embodiment, the transmission delay duration and the reception delay duration are longer than the duration of any frame data, and the transmission delay duration is longer than the reception delay duration.
When the sending end delays sending, in order that the receiving end can correctly receive, the delay time required by the sending end can be controlled by controlling the timing, so that the delay time of the receiving end is set to be longer than the time of one frame of data, namely the delay time of the receiving end is longer than the time of the first frame of data which is sent currently, and if the data which is sent currently is the second frame of data, the delay time of the receiving end is longer than the time of the second frame of data. Similarly, the sending end should be longer than the duration of one frame of data, that is, the sending delay duration is longer than the duration of the currently sent first frame of data, and if the currently sent data is the second frame of data, the sending delay duration should be longer than the duration of the second frame of data. In addition, the sending end may be set to be one clock cycle greater than the delay of the receiving end, where the clock cycle refers to a duration of the receiving end changing from the delay state to the data receiving state. Therefore, the transmission delay time period is actually longer than the reception delay time period.
In one embodiment, before the sending end sends data, the method further includes: the sending end is connected with a power supply, initialization operation is carried out, and a data preparation sending stage is started.
Before the sending end starts sending data, the sending end can be connected with a power supply, namely, equipment of the sending end is powered on, the sending end is initialized, and after the initialization is finished, the sending end enters a data preparation sending stage and can prepare for starting sending of data.
In one embodiment, before the receiving end receives the first frame data when the receiving end captures the falling edge, the method further includes: the receiving end is connected with a power supply to carry out initialization operation and enter a data preparation receiving stage.
Before the receiving end starts to receive data, the receiving end can be connected with a power supply, namely, equipment of the receiving end is powered on, the receiving end is initialized, and after the initialization is finished, the receiving end enters a data preparation receiving stage to prepare for starting to receive data.
According to the serial communication method, the data is filtered through the filter, the receiving end only needs to capture the current filtering data output by the filter, when the preset state in the current filtering data is detected, the effective data can be obtained, the time length for the receiving end to receive the data is prolonged, namely delayed receiving is carried out, and under the condition that the receiving end and the sending end are not synchronous, even if the first frame data received by the receiving end is wrong, the correct receiving of the next frame data of the receiving end can be guaranteed through a delayed receiving mode, so that the accuracy of the data received by the receiving end can be guaranteed.
In one embodiment, a serial communication method includes transmission, filtering, and reception of data. First, a transmitting end may transmit data. As shown in fig. 4, the device at the sending end may be powered on and initialized, and after the initialization is completed, the sending end may start to prepare to send data. And the sending start is low level, after the sending end sends the first frame data, the sending end waits for the sending delay time length in a delayed mode, the next frame data of the first frame data is used as second frame data, the sending end sends the second frame data, the second frame data is high level, and the process is repeated until all the data are sent.
The filter may acquire data sent by the sending end and perform filtering processing. The data sent by the sending end can be filtered by designing a simple digital filtering module. Specifically, the simple filtering module has an IO port state signal as an input signal, a high-frequency clock, and a filtered IO signal as an output. Because the baud rate of serial communication is far less than the highest frequency and the internal execution frequency captured by the IO port of the FPGA, the IO state of the data sent by the sending end can be collected and counted by the high frequency with the baud rate being N times of the preset multiple. Assuming that N is 256, namely the acquisition clock is 256 times of the serial communication baud rate, the value of the counter is num, and num +1 when num is not more than N and the input IO port is in a high level state; and num-1 when num is greater than 0 and the IO port is collected to be low level. A preset threshold may also be set. Assuming that the preset threshold is n, the filter output signal is '0' when num < n, and is '1' when num > (256-n).
When the preset threshold is set, the preset threshold is set according to the ratio of the acquired frequency to the baud rate of communication, so that different filtering effects can be achieved through setting, and the setting is similar to the relationship between a large capacitor and a small capacitor. The design of the filtering module is expected to achieve the effect of average filtering, if the high level is always high level, the threshold value of the output high level can be added, the high level is naturally output, if the high level has jitter, if the high level is originally high level, the low level appears, if num is changed from the original value 220 to 219, and if the threshold value of the high level output is 200, 219 or more than 200, the high level is output, the high level is not influenced, namely the jitter is filtered, so that the jitter of the interference can be removed, and the effect of average filtering is achieved.
After the data sent by the sending end is filtered by the filtering module, the receiving end can acquire the output signal of the filter. As shown in fig. 5, the device at the receiving end may be powered on and perform an initialization operation, and after the initialization, the receiving end enters a ready-to-receive state, that is, the receiving end may start to prepare to receive data. When the receiving end captures the falling edge, the receiving end indicates that data comes, and the receiving end can start receiving the data. When the receiving end receives data each time, the receiving end captures a falling edge first, and after the falling edge is captured, the receiving end can enter a data preparation receiving stage. If the data is 8 bits of data, the acquisition is completed within the transmission time of the 8 bits of data. When the counter counts to 8 bits, the receiving is completed. And after receiving one frame of data, the receiving end enters a waiting state, waits for the receiving delay time, then enters a ready-to-receive state, and the process is repeated. When the power-on time or the initialization time of the transmitting device and the receiving device are different, the transmitting end and the receiving end are not synchronous, and the captured falling edge is not necessarily a start bit. Therefore, the effect of synchronization of the sending end and the receiving end can be achieved by delayed sending and delayed receiving.
The time delay of the sending end is to correctly receive by the receiving end, and the time required to be prolonged by the sending end is controlled by controlling the timing. The delay of the receiving end is longer than the time of one frame of data, and then the data is received. The sending time is also longer than the time of one frame of data, the sending end is longer than the delay time of the receiving end by more than one clock period, and the clock period refers to the time of the receiving end converted from the delay state to the receiving state. The synchronization starts from the first low level counter, because in the conventional communication method, when the transmitting end transmits the first low level, the receiving end can substantially simultaneously receive the first low level. However, if the processing is performed in this way, the first data received by the receiving end may not be the first data sent by the sending end, so that in the scheme, by delaying and resetting the sending end and the receiving end, it can be ensured that the receiving end is the first data sent by the sending end when receiving the first data, thereby ensuring the accuracy of data reception.
Therefore, by adopting the serial communication method, under the condition that the receiving end and the sending end are not synchronous, even if the first frame data is received incorrectly, the next frame data can be ensured to be correctly received, and the anti-interference capability of serial communication can be improved by utilizing the high-speed IO port and the internal parallel processing capability of the FPGA and designing a simple digital filter, so that the accuracy of the received data is further ensured. The serial communication mode can also be applied to the field of machine tool control, interference is large, and all the plates run asynchronously, so that the serial communication scheme finished by the FPGA can be used, and the serial communication mode can also be applied to key technical research projects of a control system of an all-electric injection molding machine.
It should be understood that although the various steps in the flow charts of fig. 3-5 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 3-5 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.
In one embodiment, as shown in fig. 6, there is provided a serial communication apparatus including:
on the receiving end, the transmitting end includes a filtering module 401 and a data receiving module 402.
And a filtering module 401, configured to obtain current filtering data output by the filter.
A data receiving module 402, configured to, when a preset state in the current filtered data is detected, obtain valid data after the preset state in the current filtered data; when the receiving end waits for the receiving delay time after the effective data is received, the receiving end acquires the next filtering data output by the filter; and taking the next filtering data as the current filtering data, and when a preset state in the current filtering data is detected, obtaining effective data after the preset state in the current filtering data.
In one embodiment, the serial communication apparatus further includes: and the sending end comprises a data sending module.
And the data sending module is used for sending the current data to be filtered, the filter is used for filtering the current data to be filtered to obtain the current filtered data, and the sending end is used for sending the next data to be filtered after the current data to be filtered is finished and waits for the sending delay time.
In one embodiment, the transmission delay duration of the transmitting end and the receiving delay duration of the receiving end are greater than the duration of any frame data, and the transmission delay duration is greater than the receiving delay duration.
In an embodiment, the sending end further includes: a send preparation module.
And the sending preparation module is used for connecting a power supply, carrying out initialization operation and entering a data preparation sending stage.
In one embodiment, the receiving end further includes a receiving preparation module.
And the receiving preparation module is used for connecting a power supply, carrying out initialization operation and entering a data preparation receiving stage.
In an embodiment, the filtering module is further configured to acquire current filtering data output by a filter with a baud rate set as a preset multiple, and after the IO state of the current filtering data is acquired and filtered in a counter counting manner.
In an embodiment, the filtering module is further configured to increase a value of the counter by a preset specific value when the counter is less than or equal to a preset multiple and the IO port state is a high level state; when the counter is larger than 0 and the IO port state is a low level state, the value of the counter is decreased by a preset specific value.
In an embodiment, the filtering module 401 is further configured to output a first state signal when the value of the counter is smaller than a preset threshold; when the value of the counter is smaller than the preset threshold value, the output signal of the filtering module is a second state signal.
For specific limitations of the serial communication apparatus, reference may be made to the above limitations of the serial communication method, which are not described herein again. The various modules in the serial communication device described above may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as shown in fig. 7. The computer device comprises a processor, a memory and a network interface which are connected through a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a serial communication method.
Those skilled in the art will appreciate that the architecture shown in fig. 7 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the following steps when executing the computer program: acquiring current filtering data output by a filter; when a preset state in the current filtering data is detected, obtaining effective data after the preset state in the current filtering data; after the effective data is received, waiting for the receiving delay time length to obtain the next filtering data output by the filter; and taking the next filtering data as the current filtering data, and when the preset state in the current filtering data is detected, acquiring effective data after the preset state in the current filtering data.
In one embodiment, obtaining current filtered data output by the filter comprises: and acquiring current filtering data output after the IO state of the current filtering data is acquired by the filter with the Baud rate set as a preset multiple and is filtered in a counting mode of a counter.
In one embodiment, the transmission delay duration and the reception delay duration are longer than the duration of any frame data, and the transmission delay duration is longer than the reception delay duration.
In one embodiment, before the sending end sends the data to be filtered, the processor executes the computer program to further implement the following steps: connecting a power supply, performing initialization operation, and entering a data preparation sending stage.
In one embodiment, the processor when executing the computer program further performs the following steps before receiving the filtered data when the receiving end captures a falling edge: connecting a power supply, performing initialization operation, and entering a data preparation receiving stage.
In one embodiment, the processor, when executing the computer program, further performs the steps of: when the counter is smaller than or equal to the preset multiple and the IO port state is a high level state, increasing the value of the counter by a preset specific value; when the counter is larger than 0 and the IO port state is a low level state, the value of the counter is decreased by a preset specific value.
In one embodiment, the processor, when executing the computer program, further performs the steps of: when the numerical value of the counter is smaller than a preset threshold value, the input signal of the filtering module is a first state signal; and when the value of the counter is smaller than the preset threshold value, the input signal of the filtering module is a second state signal.
In one embodiment, before the receiving end obtains the current filtered data output by the filter, the processor executes the computer program to further implement the following steps: sending current data to be filtered, and filtering the current data to be filtered by a filter to obtain current filtering data; and when the current data to be filtered is finished and waits for the sending delay time, sending the next data to be filtered.
In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of: acquiring current filtering data output by a filter; when a preset state in the current filtering data is detected, obtaining effective data after the preset state in the current filtering data; after the effective data is received, waiting for the receiving delay time length to obtain the next filtering data output by the filter; and taking the next filtering data as the current filtering data, and when the preset state in the current filtering data is detected, acquiring effective data after the preset state in the current filtering data.
In one embodiment, obtaining current filtered data output by the filter comprises: and acquiring current filtering data output after the IO state of the current filtering data is acquired by the filter with the Baud rate set as a preset multiple and is filtered in a counting mode of a counter.
In one embodiment, the transmission delay duration and the reception delay duration are greater than the duration of the first frame data, and the transmission delay duration is greater than the reception delay duration.
In one embodiment, before the sender sends the data to be filtered, the computer program when executed by the processor further performs the steps of: connecting a power supply, performing initialization operation, and entering a data preparation sending stage.
In one embodiment, the computer program when executed by the processor further performs the following steps before receiving the filtered data when a falling edge is captured at the receiving end: connecting a power supply, performing initialization operation, and entering a data preparation receiving stage.
In one embodiment, the computer program when executed by the processor further performs the steps of: when the counter is smaller than or equal to the preset multiple and the IO port state is a high level state, increasing the value of the counter by a preset specific value; when the counter is larger than 0 and the IO port state is a low level state, the value of the counter is decreased by a preset specific value.
In one embodiment, the computer program when executed by the processor further performs the steps of, prior to obtaining current filtered data output by the filter: and sending the current data to be filtered, filtering the current data to be filtered by the filter to obtain the current filtered data, and sending the next data to be filtered after waiting for sending the delay time after the current data to be filtered is finished.
In one embodiment, the computer program when executed by the processor further performs the steps of: when the value of the counter is smaller than a preset threshold value, the filtering module outputs a signal as a first state signal; when the value of the counter is smaller than the preset threshold value, the output signal of the filtering module is a second state signal.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (7)
1. A method of serial communication, the method comprising:
a receiving end acquires current filtering data output by a filter;
when a preset state in the current filtering data is detected, obtaining effective data after the preset state in the current filtering data, wherein the preset state is a falling edge state;
when the receiving end waits for the receiving delay time after the effective data is received, the receiving end acquires the next filtering data output by the filter;
taking the next filtering data as the current filtering data;
the obtaining, by the receiving end, current filtering data output by the filter includes:
the receiving end acquires the current filtering data after the IO state of the current filtering data is acquired by the filter with the Baud rate set as a preset multiple and is filtered in a counter counting mode;
when the counter is smaller than or equal to the preset multiple and the IO state is a high level state, increasing the value of the counter by a preset specific value;
when the counter is larger than 0 and the IO state is a low level state, the value of the counter is decreased by the preset specific value;
when the numerical value of the counter is smaller than a preset threshold value, the output signal of the filter is a first state signal;
and when the numerical value of the counter is greater than the difference value between the preset multiple and the preset threshold value, the output signal of the filter is a second state signal.
2. The method of claim 1, wherein before the receiving end obtains the current filtered data output by the filter, the method further comprises:
a sending end sends current data to be filtered, and the filter filters the current data to be filtered to obtain the current filtering data;
and when the current data to be filtered is sent and the sending end waits for the sending delay time, the sending end sends the next data to be filtered.
3. The method of claim 2, wherein the transmission delay duration and the reception delay duration are both greater than a duration of any frame data, and wherein the transmission delay duration is greater than the reception delay duration.
4. A serial communication apparatus, the apparatus comprising a receiving end, the receiving end comprising:
the filtering module is used for acquiring current filtering data output by the filter;
the data receiving module is used for acquiring effective data after a preset state in the current filtering data when the preset state in the current filtering data is detected, wherein the preset state is a falling edge state; when the receiving end waits for the receiving delay time after the effective data is received, the receiving end acquires the next filtering data output by the filter; taking the next filtering data as the current filtering data;
the filtering module is specifically used for acquiring current filtering data output after an IO state of the current filtering data is acquired by a filter with a baud rate set as a preset multiple and is filtered in a counter counting mode, when the counter is smaller than or equal to the preset multiple and the IO state is a high level state, the value of the counter is increased by a preset specific value, and when the counter is larger than 0 and the IO state is a low level state, the value of the counter is decreased by the preset specific value;
the filtering module is further specifically configured to, when the value of the counter is smaller than a preset threshold, output signals of the filter are first state signals, and when the value of the counter is larger than a difference between the preset multiple and the preset threshold, output signals of the filter are second state signals.
5. The apparatus of claim 4, wherein the apparatus further comprises a transmitting end, and wherein the transmitting end comprises:
and the data sending module is used for sending the current data to be filtered, the current data to be filtered is obtained after the current data to be filtered is filtered by the filter, and the sending end sends the next data to be filtered after the current data to be filtered is sent and waiting for the sending delay time.
6. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method of any of claims 1 to 3 are implemented when the computer program is executed by the processor.
7. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 3.
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| CN112260814B (en) * | 2020-12-18 | 2021-03-30 | 杭州长川科技股份有限公司 | Data phase correction method for high-speed serial communication, electronic device, and storage medium |
| CN112491510A (en) * | 2021-02-08 | 2021-03-12 | 南京神鹏机械设备有限公司 | Signal processing method |
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