CN112463671A - Data delay system, method and device, computer equipment and storage medium - Google Patents
Data delay system, method and device, computer equipment and storage medium Download PDFInfo
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Abstract
The invention relates to the field of signal processing, in particular to a data delay system, a method, a device, computer equipment and a storage medium, wherein the system comprises: the data interface module is used for receiving data to be transmitted and the delay time of the data to be transmitted and sending the data to be transmitted and the delay time to the controller module; the first storage module and the second storage module are used for receiving, storing and transmitting the data to be transmitted under the control of the controller module; and the controller module controls the first storage module and the second storage module to perform delay transmission on the data to be transmitted according to the delay time. According to the invention, the first storage module and the second storage module are used for delaying data in a large range and in high precision respectively, and the processing module is used for reasonably and respectively delaying time, so that the data has a large delay range and high precision, the delay range and the delay precision can be adjusted, and the application range is wide.
Description
Technical Field
The present invention relates to the field of signal processing, and in particular, to a data delay system, method, apparatus, computer device, and storage medium.
Background
The data delay is a very key technology and has very important application in various scenes such as electronic instruments, radars, aerospace signal simulators and the like.
The existing data delay method realizes data delay through the operation of interpolation, filtering or decimation on data, or realizes data delay through the delay of a clock cycle through an FPGA chip, but the data delay realized by the delay method has a too small range or too low precision, is higher in hardware requirement, and cannot realize data delay with large range and high precision simultaneously.
In summary, the existing data delay method cannot realize data delay with large range and high precision at the same time, and has high requirement on hardware, and improvement is urgently needed.
Disclosure of Invention
In view of the foregoing, there is a need to provide a data delay system, method, apparatus, computer device and storage medium.
In one embodiment, the present invention provides a data delay system, comprising:
the data interface module is used for receiving data to be transmitted and the delay time of the data to be transmitted and sending the data to be transmitted and the delay time to the controller module;
the first storage module is used for receiving, storing and sending the data to be transmitted under the control of the controller module;
the second storage module is used for receiving, storing and outputting the data to be transmitted under the control of the controller module; and
the controller module is used for receiving the delay time and the data to be transmitted and comparing the delay time with the clock period of the first storage module; when the delay time is greater than the clock cycle, splitting the delay time into integral multiple delay time of one clock cycle and decimal multiple delay time of one clock cycle according to the clock cycle; sending the integral multiple delay time to the first storage module so that the first storage module receives and stores the data to be transmitted, and sending the data to be transmitted to a second storage module after delaying the integral multiple delay time; and sending the decimal time delay to the second storage module so that the second storage module receives the data to be transmitted and outputs the data to be transmitted after delaying the decimal time delay.
In one embodiment, the present invention provides a data delay method, which is applied to the data delay system described in the above embodiment, and the method includes:
receiving data to be transmitted and delay time of the data to be transmitted;
comparing the delay time with a clock period of a first storage module;
when the delay time is greater than the clock cycle of the first storage module, splitting the delay time into integral multiple delay time of one clock cycle and decimal multiple delay time of one clock cycle according to the clock cycle;
sending the integral multiple delay time to the first storage module so that the first storage module receives and stores the data to be transmitted, and sending the data to be transmitted to a second storage module after delaying the integral cycle time;
and sending the decimal time delay to the second storage module so that the second storage module receives and stores the data to be transmitted, and outputting the data to be transmitted after delaying the decimal time delay.
In one embodiment, the present invention further provides a data delay apparatus, including:
the data receiving unit is used for receiving the data to be transmitted and the delay time of the data to be transmitted;
the data processing unit is used for comparing the delay time with the clock period of the first storage module; when the delay time is greater than the clock cycle, splitting the delay time into integral multiple delay time of one clock cycle and decimal multiple delay time of one clock cycle according to the clock cycle;
the data output unit is used for sending the integral multiple delay time to the first storage module so as to enable the first storage module to receive and store the data to be transmitted, and sending the data to be transmitted to the second storage module after delaying the integral multiple delay time; and sending the decimal time delay to the second storage module so that the second storage module receives and stores the data to be transmitted, and outputting the data to be transmitted after delaying the decimal time delay.
In one embodiment, the present invention also provides a computer apparatus, comprising: a memory and a processor, wherein the memory stores a computer program, and the computer program, when executed by the processor, causes the processor to execute the data delay method of the above embodiment.
In one embodiment, the present invention further provides a storage medium having a computer program stored thereon, where the computer program, when executed by a processor, causes the processor to execute the data delay method according to the above embodiment.
According to the data delay system, the data delay method, the data delay device, the computer equipment and the storage medium, the processor reasonably splits the delay time according to the clock period of the first storage module, controls the first storage module to delay data in a large range, and controls the second storage module to delay data in a high precision, so that the range and precision of data delay are improved, the range and precision of data delay can be adjusted by adjusting the first storage module and the second storage module, and the application range is wide.
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Fig. 1 is a schematic structural diagram of a data delay system provided in an embodiment;
FIG. 2 is a block diagram of another embodiment of a data delay system;
FIG. 3 is a block diagram of another embodiment of a data delay system;
fig. 4 is a schematic structural diagram of a variable fractional delay filtering module provided in an embodiment;
FIG. 5 is a diagram of an implementation environment of a data delay method provided in one embodiment;
FIG. 6 is a diagram of the steps of a data delay method provided in one embodiment;
FIG. 7 is a block diagram of a data delay apparatus according to an embodiment;
fig. 8 is a schematic diagram of an internal structure of a computer provided in an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms unless otherwise specified. These terms are only used to distinguish one element from another. For example, a first xx unit may be referred to as a second xx unit, and similarly, a second xx unit may be referred to as a first xx unit, without departing from the scope of the present application.
Fig. 1 is a schematic structural diagram of a data delay system provided in an embodiment, which is described in detail below.
The data delay system provided by the embodiment of the invention comprises a data interface module 101, a controller module 104 and a data transmission module, wherein the data interface module 101 is used for receiving data to be transmitted and delay time of the data to be transmitted and sending the data to be transmitted and the delay time to a controller module; a first storage module 102, configured to receive, store, and send the data to be transmitted under the control of the controller module 104; the second storage module 103 is configured to receive, store, and output the data to be transmitted under the control of the controller module 104; the controller module 104 is configured to receive the delay time and the data to be transmitted, and compare the delay time with a clock cycle of the first storage module 102; when the delay time is greater than the clock cycle, splitting the delay time into integral multiple delay time of one clock cycle and decimal multiple delay time of one clock cycle according to the clock cycle; sending the integral multiple delay time to the first storage module 102, so that the first storage module 102 receives and stores the data to be transmitted, and sending the data to be transmitted to the second storage module 103 after delaying the integral multiple delay time; sending the decimal time delay to the second storage module 103, so that the second storage module 103 receives the data to be transmitted, delays the decimal time delay and outputs the data to be transmitted
In the embodiment of the present invention, the data interface module 101 may be a USB interface, or other data interfaces such as RS232, RS485, network card, etc., and is configured to receive data to be transmitted and delay time of the data to be transmitted, and transmit the data to the controller module 104; the controller module 104 may be a processor, or other controllers such as a single chip microcomputer and an FPGA, and is configured to receive a delay time of data to be transmitted sent by the data interface module 101, where the data interface module 101 is connected to the controller module 104 through a data transmission line, the controller module 104 controls the first storage module 102 and the second storage module 103, and the first storage module 102 and the second storage module 103 are storage devices having a storage function, and can write and read data in a delayed manner under the control of the controller 104.
As an embodiment of the present invention, after receiving data to be transmitted and a delay time T of the data to be transmitted, a data interface module sends both the data to be transmitted and the delay time T of the data to be transmitted to a controller module 104, and the controller module 104 splits and allocates the delay time, wherein the maximum delay time of the first storage module 102 is
Wherein N is the storage capacity of the first storage module, W is the data bit width, and V is the data rate; for example, when the storage capacity of the first memory module is 2GB, the data bit width is 16, and the rate is 250MHz, the maximum delay time is
Approximately 1.073741824 seconds, a first memory module of greater memory capacity may be selected when a greater range of latency is required. When the memory module 104 splits the delay time T, the delay time T is split into an integral multiple of T according to the clock period T of the first memory module1And a decimal time delay T2Then T is added1Sending T to the first storage module2And sending the data to the second storage module. As a preferred embodiment of the present invention, if the clock period T of the first storage module is 4ns and the delay time T of the data to be transmitted is 890789753.33ns, the delay time T needs to have 222697438.3325 periods relative to the first storage module, and then T is equal to 4ns1＝4*222697438＝890789752ns，T20.3325 × 4 × 1.33 ns. The control module allocates the delay time T to the first storage module1And a delay time T to be allocated to the second memory module2After calculating, T1The data to be transmitted is sent to the first storage module while being configured to the first storage module, and the data transmission interface of the first storage module is opened, so that the first storage module receives the data to be transmitted, and the time delay T is carried out1After the time, the data to be transmitted are sent to a second storage module; at the controller module, T1When configured to the first memory module, also configure T2Configuring the data interface to a second storage module, opening the data interface of the second storage module, and delaying T after the second storage module receives the data to be transmitted sent by the first storage module2And outputting the data to be transmitted by the time.
According to the embodiment of the invention, the processor reasonably splits the delay time according to the clock period of the first storage module, controls the first storage module to delay data in a large range, and controls the second storage module to delay data in a high precision, so that the range and precision of data delay are improved, and the range and precision of data delay can be adjusted by adjusting the first storage module and the second storage module, so that the application range is wide.
The data delay system provided by the embodiment of the invention further comprises a controller module, wherein when the delay time is less than the clock cycle, the controller module directly sends the delay time and the data to be transmitted to the second storage module, so that the second storage module receives and stores the data to be transmitted, and outputs the data to be transmitted after delaying the delay time.
In the embodiment of the invention, the delay time of the data to be transmitted is limited by external conditions and may be very short, so that the delay time is shorter than the clock cycle of the first storage module, and when the delay time of the data to be transmitted is smaller than the clock cycle of the first storage module, the controller module directly sends the delay time to the second storage module, controls the second storage module to receive the data to be transmitted, and directly outputs the data to be transmitted after delaying the delay time.
As an embodiment of the present invention, a clock period T of a first storage module is 4ns, a delay time T of data to be transmitted is 3.33ns, after receiving the delay time T, a controller module compares the delay time T with the clock period T of the first storage module to obtain a conclusion that the delay time T is less than the clock period T, and directly configures the delay time T to a second storage module, and simultaneously opens a data interface of the second storage module to transmit the data to be transmitted to the second storage module, so that the second storage module outputs the data to be output after delaying the delay time.
According to the embodiment of the invention, when the delay time of the data is less than the clock period of the first storage module, the delay time is directly configured to the second storage module, and meanwhile, the data to be transmitted is sent to the second storage module, so that the realization of ultra-short delay can be ensured.
Fig. 2 is a schematic structural diagram of another data delay system according to an embodiment, which is described in detail below.
The data delay system provided by the embodiment of the invention further comprises a first data conversion module, a second data conversion module and a data processing module, wherein the first data conversion module is used for converting the format of the data to be transmitted into the storage format of the first storage module before the first storage module receives the data to be transmitted by the data interface module; and the second data conversion module is used for converting the data format into the storage format of the second storage module before the second storage module receives the data to be transmitted.
In the embodiment of the present invention, the first data conversion module 105 is disposed between the controller module 104 and the first storage module 102, and is configured to convert a format of data to be transmitted into a data storage format of the first storage module 105 after receiving the data to be transmitted sent by the controller module; the input end of the second data conversion module 106 is connected to the controller module 104 and the first storage module 102, and the output end is connected to the second storage module 103, and is configured to convert data to be transmitted, which is sent by the first storage module or the controller module, into a data storage format of the second storage module.
As an embodiment of the present invention, the first data conversion module 105 and the second data processing module 106 refer to a modular structure having a data format conversion function, and are capable of converting data to be transmitted in different formats into storage formats of the first storage module and the second storage module. As a preferred embodiment of the present invention, the first data conversion module may receive data to be transmitted in any format, and only may output data in a format that the first storage module can store; the second data conversion module can accept data in any format and only can output data in a format which can be stored by the second storage module.
According to the embodiment of the invention, the first data conversion module and the second data conversion module are used for converting the data format, so that the smooth transmission and the transmission speed of data among the modules are ensured.
Fig. 3 is a schematic structural diagram of another data delay system according to an embodiment, which is described in detail below.
The data delay system provided by the embodiment of the invention further comprises that the first storage module comprises: the external memory is used for storing the data to be transmitted; and the external memory interface control module is used for receiving the integral multiple delay time and reading and writing data in the external memory delay time according to the integral multiple delay time.
In the embodiment of the present invention, the external memory refers to a storage device having data writing and reading functions, and may be a hard disk, a floppy disk, an optical disk, and a usb disk, and the memory chips such as DDR3, DDR4, and SRAM are used to store data to be transmitted; the external memory interface control module is used for controlling the external memory to realize the data writing and reading functions, and is controlled by the controller module.
As an embodiment of the present invention, the first storage module includes an external memory 107 and an external memory interface control module 108, the external memory interface control module 108 is connected to the first data conversion module 105 and the second data conversion module 106, and can control read and write functions of the external memory 107, when the controller module 104 sends the data to be transmitted and the delay time to the first storage module through the first data conversion module 105, the external memory interface control module 108 controls the data interface of the external memory 107, writes the data to be transmitted, starts timing, and when the delay time reaches, controls the data interface of the external memory 107, reads the data to be transmitted, and sends the data to be transmitted to the second data conversion module 106.
The embodiment of the invention controls the reading and writing functions of the data of the external memory through the external memory interface control module, and transmits the data to be transmitted in a delayed manner, thereby realizing the function of delaying in a large range.
Fig. 4 is a schematic structural diagram of a variable fractional delay filter module according to an embodiment, which is described in detail below.
The data delay system provided by the embodiment of the invention further comprises that the second storage module comprises: the data cache module is used for receiving and caching the data to be transmitted and sending the data to be transmitted to the variable fractional delay filter module; the variable decimal time delay filter module is used for receiving the decimal time delay time and the data to be transmitted, delaying the decimal time delay time and then outputting the data to be transmitted.
In the embodiment of the present invention, the data caching module refers to a caching device that can cache data, and cannot store the data for a long time, such as a memory; the variable decimal time delay filter is a filter bank capable of adjusting time delay time, and ultra-high precision data time delay is realized through combination of the time delay time of a plurality of filters.
As an embodiment of the present invention, the fractional delay filter module 110 is connected to the second data conversion module 106 and the data buffer module 109, the controller module 104 sends the fractional delay time to the fractional delay filter module, and after the buffer module receives the data to be transmitted, the fractional delay filter module starts timing, where there are multiple filters, and the delay time of each filter can be adjusted. As a preferred embodiment of the present invention, the variable fractional delay filter module adopts a FARROW filter structure, as shown in fig. 4, the filter is composed of M groups of filters, the delay time of each group of filters is the same, p is a delay time adjustment parameter, the delay time of a single filter is adjusted by adjusting the value of p, and then the delay times are accumulated to realize the delay of fractional times of the delay time; assuming that the operating clock period of the filter system is Ts, p can take any value in the range (-1/2,1/2) Ts. If the operating clock of the filter system is 250MHz (i.e., Ts ═ 4ns), the p value can be any value in the range of (-1/2,1/2) × 4 ns. Selecting a proper filter can make the delay precision very high, and selecting a proper p value, the filter can realize very small delay, for example, if p of the first filter is 0.025, the delay value is 0.025 × 4ns — 0.1 ns. In the M groups of filters, the p value of each filter can be changed, and the delay time multiplied by a small number is divided, so that the accurate delay time can be obtained.
The embodiment of the invention adjusts the delay time parameter of a single filter by adopting a plurality of groups of filters, so that the delay time of the single filter can be changed, and then the delay times of a plurality of filters are accumulated to realize the delay of the delay time which is multiplied by a decimal number.
Fig. 5 is a diagram of an application environment of the data delay method provided in an embodiment, as shown in fig. 5, in the application environment, including a data network 510 and a computer device 50.
The computer device 520 may be an independent physical server or terminal, may also be a server cluster formed by a plurality of physical servers, and may be a cloud server providing basic cloud computing services such as a cloud server, a cloud database, a cloud storage, and a CDN (Content Delivery Network).
Fig. 6 is a flowchart illustrating steps of a data delay method according to an embodiment, which will now be described in detail with reference to the computer device 520.
In step S601, data to be transmitted and the delay time of the data to be transmitted are received.
As an embodiment of the present invention, the receiving of the data to be transmitted may be receiving network data through a network interface, or reading data in a storage device through a data transmission interface and then transmitting the data.
In step S602, the delay time is compared with a clock period of the first storage module.
As an embodiment of the present invention, after the controller module receives the data to be transmitted and the delay time of the data to be transmitted, the delay time is compared with the clock cycle of the first storage module.
In step S603, when the delay time is greater than the clock cycle of the first storage module, the delay time is divided into an integral multiple of the clock cycle and a fractional multiple of the clock cycle according to the clock cycle.
In the embodiment of the present invention, after comparing the delay time with the clock cycle of the first storage module, the controller module splits the delay time into an integral multiple of the clock cycle and a decimal multiple of the clock cycle according to the clock cycle when the delay time is greater than the clock cycle of the first storage module according to the comparison result
As an embodiment of the present invention, the maximum latency of the first storage module 102
Wherein N is the storage capacity of the first storage module and W is a numberAccording to the bit width, V is the data rate; for example, when the storage capacity of the first memory module is 2GB, the data bit width is 16, and the rate is 250MHz, the maximum delay time is
Approximately 1.073741824 seconds, a first memory module of greater memory capacity may be selected when a greater range of latency is required. As a preferred embodiment of the present invention, if the clock period T of the first storage module is 4ns and the delay time T of the data to be transmitted is 890789753.33ns, the delay time T needs to have 222697438.3325 periods relative to the first storage module, and then T is equal to 4ns1＝4*222697438＝890789752ns，T2＝0.3325*4＝1.33ns。
In step S604, the integral multiple delay time is sent to the first storage module, so that the first storage module receives and stores the data to be transmitted, and sends the data to be transmitted to the second storage module after delaying the integral cycle time.
As an embodiment of the invention, the control module allocates the delay time T to the first storage module1And a delay time T to be allocated to the second memory module2After calculating, T1The data to be transmitted is sent to the first storage module while being configured to the first storage module, and the data transmission interface of the first storage module is opened, so that the first storage module receives the data to be transmitted, and the time delay T is carried out1And sending the data to be transmitted to the second storage module after the time.
In step S605, the decimal time delay is sent to the second storage module, so that the second storage module receives and stores the data to be transmitted, and outputs the data to be transmitted after delaying the decimal time delay.
As an embodiment of the invention, T is set at the controller module1When configured to the first memory module, also configure T2Configuring the data interface to a second storage module, opening the data interface of the second storage module, and delaying the data transmission when the second storage module receives the data to be transmitted sent by the first storage moduleT2And outputting the data to be transmitted by the time.
According to the invention, the processor reasonably splits the delay time according to the clock period of the first storage module, controls the first storage module to delay data in a large range, and controls the second storage module to delay data in a high precision, so as to improve the range and precision of data delay.
The data delay method provided by the embodiment of the invention further comprises the step of directly sending the delay time to the second storage module when the delay time is less than or equal to the clock period, so that the second storage module receives and stores the data to be transmitted, and outputs the data to be transmitted after delaying the delay time.
In the embodiment of the invention, the delay time of the data to be transmitted is limited by external conditions and may be very short, so that the delay time is shorter than the clock cycle of the first storage module, and when the delay time of the data to be transmitted is smaller than the clock cycle of the first storage module, the controller module directly sends the delay time to the second storage module, controls the second storage module to receive the data to be transmitted, and directly outputs the data to be transmitted after delaying the delay time.
As an embodiment of the present invention, a clock period T of a first storage module is 4ns, a delay time T of data to be transmitted is 3.33ns, after receiving the delay time T, a controller module compares the delay time T with the clock period T of the first storage module to obtain a conclusion that the delay time T is less than the clock period T, and directly configures the delay time T to a second storage module, and simultaneously opens a data interface of the second storage module to transmit the data to be transmitted to the second storage module, so that the second storage module outputs the data to be output after delaying the delay time.
According to the embodiment of the invention, when the delay time of the data is less than the clock period of the first storage module, the delay time is directly configured to the second storage module, and meanwhile, the data to be transmitted is sent to the second storage module, so that the realization of ultra-short delay can be ensured.
Fig. 7 is a diagram of a data delay apparatus according to an embodiment, which is described in detail below.
In a data delay apparatus provided in an embodiment of the present invention, the apparatus includes:
the data receiving unit 710 is configured to receive data to be transmitted and a delay time of the data to be transmitted.
As an embodiment of the present invention, the receiving of the data to be transmitted may be receiving network data through a network interface, or reading data in a storage device through a data transmission interface and then transmitting the data.
A data processing unit 720, configured to compare the delay time with a clock period of the first storage module; when the delay time is larger than the clock period, dividing the delay time into integral multiple delay time of one clock period and decimal multiple delay time of one clock period according to the clock period.
In the embodiment of the present invention, after comparing the delay time with the clock cycle of the first storage module, the controller module splits the delay time into an integral multiple of the clock cycle and a decimal multiple of the clock cycle according to the clock cycle when the delay time is greater than the clock cycle of the first storage module according to the comparison result
As an embodiment of the present invention, the maximum latency of the first storage module 102
Wherein N is the storage capacity of the first storage module, W is the data bit width, and V is the data rate; for example, when the storage capacity of the first memory module is 2GB, the data bit width is 16, and the rate is 250MHz, the maximum delay time is
About 1.073741824 seconds, when a larger delay range is required, a first storage mode with larger storage capacity can be selectedAnd (5) blocking. As a preferred embodiment of the present invention, if the clock period T of the first storage module is 4ns and the delay time T of the data to be transmitted is 890789753.33ns, the delay time T needs to have 222697438.3325 periods relative to the first storage module, and then T is equal to 4ns1＝4*222697438＝890789752ns，T2＝0.3325*4＝1.33ns。
The data output unit 730 is configured to send the integral multiple delay time to the first storage module, so that the first storage module receives and stores the data to be transmitted, and sends the data to be transmitted to the second storage module after delaying the integral multiple delay time; and sending the decimal time delay to the second storage module so that the second storage module receives and stores the data to be transmitted, and outputting the data to be transmitted after delaying the decimal time delay.
As an embodiment of the invention, the control module allocates the delay time T to the first storage module1And a delay time T to be allocated to the second memory module2After calculating, T1The data to be transmitted is sent to the first storage module while being configured to the first storage module, and the data transmission interface of the first storage module is opened, so that the first storage module receives the data to be transmitted, and the time delay T is carried out1Sending the data to be transmitted to a second storage module after the time
As an embodiment of the invention, T is set at the controller module1When configured to the first memory module, also configure T2Configuring the data interface to a second storage module, opening the data interface of the second storage module, and delaying T after the second storage module receives the data to be transmitted sent by the first storage module2And outputting the data to be transmitted by the time.
According to the invention, the processor reasonably splits the delay time according to the clock period of the first storage module, controls the first storage module to delay data in a large range, and controls the second storage module to delay data in a high precision, so as to improve the range and precision of data delay.
As shown in fig. 8, which is a block diagram of a computer device according to an embodiment of the present invention, the computer device according to an embodiment of the present invention includes a memory 801, a processor 802, a communication module 803, and a user interface 804.
The memory 801 stores therein an operating system 805 for processing various basic system services and programs for executing hardware-related tasks; application software 806 is also stored for implementing the steps of the data delay method in the embodiments of the present invention.
In embodiments of the present invention, the memory 801 may be a high-speed random access memory such as DRAM, SRAM, DDR, RAM, or other random access solid state memory device, or a non-volatile memory such as one or more hard disk storage devices, optical disk storage devices, memory devices, or the like.
In an embodiment of the present invention, the processor 802 may receive and transmit data through the communication module 803 to implement blockchain network communication or local communication.
The user interface 804 may include one or more input devices 807 such as a keyboard, mouse, touch screen display, and the user interface 804 may also include one or more output devices 808 such as a display, microphone, and the like.
In addition, an embodiment of the present invention further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the processor is enabled to execute the steps of the data delay method.
It should be understood that, although the steps in the flowcharts of the embodiments of the present invention are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in various embodiments may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a non-volatile computer-readable storage medium, and can include the processes of the embodiments of the methods described above when the program is executed. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A data delay system, the system comprising:
the data interface module is used for receiving data to be transmitted and the delay time of the data to be transmitted and sending the data to be transmitted and the delay time to the controller module;
the first storage module is used for receiving, storing and sending the data to be transmitted under the control of the controller module;
the second storage module is used for receiving, storing and outputting the data to be transmitted under the control of the controller module; and
the controller module is used for receiving the delay time and the data to be transmitted and comparing the delay time with the clock period of the first storage module; when the delay time is greater than the clock cycle, splitting the delay time into integral multiple delay time of one clock cycle and decimal multiple delay time of one clock cycle according to the clock cycle; sending the integral multiple delay time to the first storage module so that the first storage module receives and stores the data to be transmitted, and sending the data to be transmitted to a second storage module after delaying the integral multiple delay time; and sending the decimal time delay to the second storage module so that the second storage module receives the data to be transmitted and outputs the data to be transmitted after delaying the decimal time delay.
2. The system of claim 1, comprising:
when the delay time is less than the clock period, the controller module directly sends the delay time and the data to be transmitted to the second storage module, so that the second storage module receives and stores the data to be transmitted, and outputs the data to be transmitted after delaying the delay time.
3. The system of claim 1, further comprising:
the first data conversion module is used for converting the format of the data to be transmitted into the storage format of the first storage module before the first storage module receives the data to be transmitted by the data interface module;
and the second data conversion module is used for converting the data format into the storage format of the second storage module before the second storage module receives the data to be transmitted.
4. The system of claim 1, wherein the first storage module comprises:
the external memory is used for storing the data to be transmitted;
and the external memory interface control module is used for receiving the integral multiple delay time and reading and writing data in the external memory delay time according to the integral multiple delay time.
5. The system of claim 1, wherein the second storage module comprises:
the data cache module is used for receiving and caching the data to be transmitted and sending the data to be transmitted to the variable fractional delay filter module;
the variable decimal time delay filter module is used for receiving the decimal time delay time and the data to be transmitted, delaying the decimal time delay time and then outputting the data to be transmitted.
6. A data delay method applied to the data delay system of any one of claims 1 to 5, the method comprising:
receiving data to be transmitted and delay time of the data to be transmitted;
comparing the delay time with a clock period of a first storage module;
when the delay time is greater than the clock cycle of the first storage module, splitting the delay time into integral multiple delay time of one clock cycle and decimal multiple delay time of one clock cycle according to the clock cycle;
sending the integral multiple delay time to the first storage module so that the first storage module receives and stores the data to be transmitted, and sending the data to be transmitted to a second storage module after delaying the integral cycle time;
and sending the decimal time delay to the second storage module so that the second storage module receives and stores the data to be transmitted, and outputting the data to be transmitted after delaying the decimal time delay.
7. The method of claim 6, comprising:
and when the delay time is less than or equal to the clock period, directly sending the delay time to the second storage module so that the second storage module receives and stores the data to be transmitted, and outputting the data to be transmitted after delaying the delay time.
8. A data delay apparatus, the apparatus comprising:
the data receiving unit is used for receiving the data to be transmitted and the delay time of the data to be transmitted;
the data processing unit is used for comparing the delay time with the clock period of the first storage module; when the delay time is greater than the clock cycle, splitting the delay time into integral multiple delay time of one clock cycle and decimal multiple delay time of one clock cycle according to the clock cycle;
the data output unit is used for sending the integral multiple delay time to the first storage module so as to enable the first storage module to receive and store the data to be transmitted, and sending the data to be transmitted to the second storage module after delaying the integral multiple delay time; and sending the decimal time delay to the second storage module so that the second storage module receives and stores the data to be transmitted, and outputting the data to be transmitted after delaying the decimal time delay.
9. A computer arrangement comprising a memory and a processor, the memory having stored thereon a computer program that, when executed by the processor, causes the processor to carry out the steps of a data delay method as claimed in any one of claims 6 to 7.
10. A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, causes the processor to carry out the steps of a data delay method as claimed in any one of claims 6 to 7.
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