CN101836193A - A kind of synchronous data bus device and data transmission method - Google Patents
A kind of synchronous data bus device and data transmission method Download PDFInfo
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- CN101836193A CN101836193A CN200880111329A CN200880111329A CN101836193A CN 101836193 A CN101836193 A CN 101836193A CN 200880111329 A CN200880111329 A CN 200880111329A CN 200880111329 A CN200880111329 A CN 200880111329A CN 101836193 A CN101836193 A CN 101836193A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
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Abstract
The embodiment of the invention discloses a kind of storage system, controlled in the time of two intermodules transmission data in this system, so that total time-delay of described storage system remains unchanged.And each paths on the multi-line bus of the present invention can independently manage, and Frame is handled at data receiving terminal, has saved the operation of going deviation at intermediate node.In addition, the present invention adopts speed on module be the rate controlled data channel of the factor of data bus serial data rate, reduced propagation delay by described module transmission data, at this, described module is carried out route by switch to the data of transmission and is handled, and the present invention carries out choose reasonable to the sampled point that receives data, makes system's tolerable temperature change or the aging delay inequality that causes.
Description
Technical field
The present invention relates to the management of distributed clock in the storage system.
Background technology
In computer system, central processing unit (CPU, central processor) is used for visiting the program information and the data that are stored in storage system.The current memory system that various different levels are arranged, in size, can select in the Computer System Design stage for the Computer System Design personnel on the speed and on the ability, these memory systems can comprise cache memory, primary storage and supplementary storage.Cache memory has low delay, high bandwidth, and expensive characteristics, and it can be integrated among the CPU.Cache memory can be semiconductor devices simultaneously, such as can be static random-access memory (SRAM, static randomaccess memory).Primary memory also is a semiconductor devices, and such as can be dynamic RAM (DRAM, dynamic random access memory), primary memory is mainly used in little data of memory access probability and program.At present, PC can comprise the DRAM of the highest 4GB, and high-end server can comprise general 16GB or bigger DRAM.Propose at present by using a large amount of Memory Controller Hub and computer inner core to visit the strategy of the mass data among the DRAM; But, since the travel-time, bus load, and reasons such as power consumption make computer bus system that specific upper limit must be arranged.In addition, mass data also may be stored in the massage storage; Such as, magneto-optic disk, each signal disk can comprise the internal memory of GB (TB) in magneto-optic disk, and for another example, the FLASH storer (sometimes is called as solid-state drive-SDD), perhaps use the disk of cluster.Data institute's time spent in the visit magneto-optic disk is obviously long than the time of the data in the visit primary memory.
As the patent No. is 11/405,083, and the applying date is that the United States Patent (USP) in April 17 in 2006 is described, can comprise a large amount of DRAM or other storeies (such as FLASH) in the memory device.Further, big storage array closes on traditional master controller, can think that therefore described storage array and primary memory are basic identical, and this big storage array can supply the fast access mass data, described mass data should be kept in the massage storage, in the spinning disk medium.
Data are reaching between other equipment and are transmitting in processor by data bus between the storer, described data bus has a plurality of forms, such as can be parallel bus, universal serial bus, point-to-point, daisy chain, many stumps etc.
When the clock frequency that transmits and receive data all equated at all node places of system, data bus was operated under the method for synchronization, like this at data receiver, had a known phase relation between the data bit.But if between two adjacent nodes, data are transmitted by parallel bus, and owing to the relation of time delay, the phase relation of the data bit that transmits in the different circuits changes like this.Underway low speed data transmission, and the path of transmission more in short-term, it is acceptable that phase relation between data bit changes, but when carrying out high speed data transfer, data bit will be received in the out of phase of system clock, and the reception of data bit bit at interval may be greater than a clock period, to lead to errors like this, and maybe need to remove the deviation line phase of going forward side by side and regulate, and when removing deviation and carrying out phase adjusted, need all need to carry out usually at each memory node place.
The above-mentioned problem of mentioning can be passed through while transfer clock and data in each circuit, and the scheme of the clock of transmission being recovered at specific node place reduces.Here delay time between clock of mentioning and the system clock, online and line and have nothing in common with each other.In addition, when clock and data were together transmitted, system need comprise data-transmission mode or comprise idle data patterns at least, keeps synchronously with the clock of guaranteeing to transmit on each bar circuit.
Perhaps, data can be recovered at each node, concrete, can each node will receive from the data storage of different circuits in impact damper, but determine the time delay adjustment amount of offset data deviation, and (data described herein are interpreted as command messages in the described data of each node rebuild before data are further handled, described order comprises reads, and writes and similarly order, perhaps can comprise Indication message, such as writing, or from storer, read).Be the offset data deviation, the data volume that is buffered in the impact damper should be identical with the clock cycle deviation that produces on the data bus.Total time-delay by data bus transmission data is the summation of per two internodal maximum delay on the circuit.Herein, data bus can be the FB-DIMM (fully buffered DIMM) that adopts the JEDEC standard.
Data bus also can be used as multi-point bus and uses, and is transferred to target memory module (such as the 3rd memory module that is connected on the linear bus) in data on the multi-point bus from transmitting terminal (such as Memory Controller Hub).Described memory module can be DIMM (DIMM, dual-in-line memory module), and as previously mentioned, the maximum delay on the multi-point bus is the time delay with bus of longer transmission time delay.The reason that produces propagation delay time is because the line length difference of each independent data circuit, the length that described line length comprises the lead-in wire on the mainboard and comprises the lead-in wire on the circuit board of described target memory module.Total departure is with the length and the signaling rate of restricting data bus.
As application number is 11/405, the disclosed content of 083 United States Patent (USP), the circuit of bus (such as, the point-to-point series connection, point is connected with the branch of putting) between time-delay can reduce by the logical channel of appropriate change bus transfer data, therefore when data transmission arrived receiving end, the deviation between data had been reduced to minimum, and is perhaps known or controlled.Therefore, at receiving end, the calibrator quantity that is used for the data deviation is calibrated reduces, and the complexity of simultaneity factor and power consumption reduce.
Summary of the invention
The invention discloses a kind of interconnection system, comprise first node and the Section Point of communicating by letter with described first node.First clock is provided for described first node and described Section Point; Based on the first clock generating second clock, there are the first integral relation in described second clock and described first clock, and there is time-delay with respect to adjusted first clock, so that the transmission time of bit between first node output and Section Point output keeps constant substantially.
The invention discloses a kind of data transmission system, described system comprises at least two modules that connected by data bus.Each module comprises transmitting element, is used to send serial data, comprises receiving element, is used to receive serial data.One conventional clock provides clock signal for described module, and a clock generator is used to each module that internal clocking is provided, and described internal clocking is derived by described conventional clock and produced.One clock data recovery circuit is used to generate and receives data clock and keep bit synchronous with described serial data, and a calibration impact damper, is used to set up and the bit that keeps described serial data and described internal clocking synchronous.One switch, the serial data route that is used for receiving is given arbitrary outside or internal port.Described module can comprise a plurality of internal ports and outside port.
In addition, the present invention also provides a kind of storage system, comprises a plurality of modules that connected by circuit, has at least a module to comprise data-carrier store in described a plurality of modules.One system clock sends at least two described modules, and data depend on described system clock fully in the data clock frequency that intermodule transmits.Comprise an impact damper on the described module, be used for keeping the bit and the previous already present bit synchronous of the character data that receives.
In addition, the present invention also comprises a data-interface, comprises a clock data recovery circuit; One clock phase alignment impact damper, and a data transmission circuit.The clock that described clock data recovery circuit is used for recovering to use with data transmission circuit has the clock of same frequency, and described phase alignment impact damper is used for the offset data time delay.
In addition, the present invention also comprises a memory module, comprises a Data Receiving unit; Clock data recovery circuit, a routing switch, a memory interface, and a data transmission unit.The clock that described clock data recovery circuit is used for recovering to use with data transmission circuit has the clock of same frequency, and described phase alignment impact damper is used for the offset data time delay.
In addition, the present invention also comprises the node of an interconnection system, comprises a data receiver circuit; One data transmit circuit; One is connected the switch between described data receiver circuit and the data transmit circuit.One circuit, circuit, first bit that can keep a certain character in the character that comprises a plurality of bits of sampling time and reception is in stable relations; And an Input Data Buffer, be used for described first bit is sampled again, so that the overall delay between the bit of corresponding sampling again remains unchanged substantially in described sampling bits again and another module.
The present invention also comprises a data transmission method, and this method comprises: at least two modules are provided, and described module comprises receiving element, transmitting element, clock data recovery circuit, phase alignment impact damper and routing switch.Described module is connected to each other by circuit.One character of frame data is put into first circuit.Preset owing to be positioned at described first circuit of receiving end, therefore when transmission character changes with the time delay that receives character, first bit of described character will be sampled so that calibrate the sampling time of described first bit.
The present invention also comprises a kind of management method of interconnection system, and described interconnection system comprises the node of a plurality of mutual communication.Described method comprises: the character that will include in the data of a plurality of bits is transferred to Section Point from first node; Receive described character at described Section Point; Recovered clock and adjustment are to the sampling time of described character from the data of described reception; And, the clock frequency that with frequency is the factor of described clock frequency is sampled to the data of sampling again, and adjust described phase place or the time-delay of carrying out again sampling clock, so that the overall delay between the character on the character of first node transmission and the same passage that transmits from Section Point is constant substantially.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the block diagram that includes the computer system of memory module of the present invention;
Fig. 2 (a) and (b) enumerated the protocol command standard of logical OR physical feature of the present invention;
Fig. 3 is the simplified structure block diagram of memory module of the present invention;
Fig. 4 is the refined structure block diagram of the memory module among Fig. 3;
Fig. 5 shows Bit data at the input port of reorganization circuit and the logic distribution plan of output port;
Fig. 6 shows the framework of the functional module in the switch of memory module;
The time that Fig. 7 (a) is relevant with synchronous operation with (b) distributes.
Embodiment
Can better understand embodiments of the invention in conjunction with the accompanying drawings, but described embodiment can not be used to limit scope of the present invention.Label identical in the identical or different accompanying drawings is represented identical implication.Parts can be represented or represent with abbreviation with numbering, or adopt the two to represent simultaneously, and adopt which kind of mode to represent that parts are just for clearer, if therefore parts are adopted numbering, and same parts abbreviation represented or adopts alphanumeric representation, these such parts to be interpreted as to be identical parts.
For a person skilled in the art, can know clearly very that method of the present invention and device can be configured to or insert and can pass through in the operational order of running software or hardware operation.Described operational order can start equipment such as digital processing unit, and described digital processing unit moves described operational order to realize operation of the present invention.Perhaps, operation of the present invention can be carried out by specific hardware, described hardware comprises hardware circuit logical OR firmware instructions, and perhaps, operation of the present invention can be by including logical circuit and combining computer program component and the assembly of the nextport hardware component NextPort of customization is carried out.Such as, microprocessor, field programmable gate array (FPGA, field programmable gate array) or special IC (ASIC, application specificintegrated circuit).These circuit are integrated in the storer, or with storer carry out related, with the instruction or the data of storing any needs.
Method of the present invention can all or part ofly be put into machine readable media, stores the instruction that may command computing machine (or other electronic installations) is carried out method of the present invention in the described machine readable media.For realizing this purpose, described machine readable media is interpreted as any one instruction or data of can be used for storing or encoding and can be carried out by computing machine or specialized hardware, and can impel described computing machine or specialized hardware operation the present invention program's medium.Described machine readable media should include, but not limited to solid-state memory, magneto-optic disk, and disk, CD, and carrier signal etc.Described carrier signal is understood to include electron device and instruction, and described instruction is used for producing or receiving the electronic signal that comprises instruction or data (instruction that the present invention need carry out or data), no matter described carrier signal is emission or radiation.
As an example, described machine readable media can comprise ROM (read-only memory) (ROM, read-only memory); Any type of random access storage device (RAM, random access memory) (such as, SRAM, DRAM); Programmable read only memory (PROM, programmable read only memory); The light random access storage device; CD; The flash storer; And the signal that passes through electricity, light, sound or the transmission of other forms.
Further, software field in different ways (such as, program, process, application software, computing or logic) to carry out a certain action or obtain certain result be very common thing.Adopting these modes only is to explain the execution to software of computer equipment or its equivalent apparatus for convenience, makes the processor of computing machine or its equivalent apparatus can carry out action or obtain the result.
When describing specific embodiment, described embodiment can comprise not being specific feature, structure or the characteristics that each embodiment has.When understanding, short of spelling out can not be in conjunction with, the Partial Feature between the so different embodiment, and structure or characteristics can make up.That is to say that when specific feature, when structure or characteristics were described at some embodiment, instant those skilled in the art should be able to determine these features under the situation that does not offer some clarification on, structure or characteristics can be used for other embodiment equally.
For purpose clearly, the present invention does not list all conventional func of all embodiment.Certainly be to be understood that when any actual embodiment of research and development, must make many concrete enforcements decisions, for example observe system and professional relevant regulation for the objectives that reach research and development, and these targets meetings because of the difference of embodiment difference.And, be to be understood that such R﹠D work may be complicated and consuming time, but still be the routine work of enjoying those skilled in the art of the disclosure content interests.
Connector of the present invention or connecting interface such as the memory module connecting interface, are not defined as the physical separation interface that comprises positive interface and negative interface.It also comprises any physical interface or connector, such as, be used for lead-in wire, tin ball or connector that the memory module circuit is electrically connected with other memory module circuit or circuit board.For example, piling up technical field, a large amount of integrated circuit (IC) chip (such as, memory device, buffer device etc.) pile up each other and pile up by ball grid array or other connected modes with substrate, be formed into memory module, Memory Controller Hub, or the interface of processor.For another example, can interconnect each other by tape or interface interconnection mode flexibly between memory device and the buffer device, be connected to Memory Controller Hub by ball grid array or physical separation interface again.Connected mode of the present invention should comprise the connected mode of integrated circuit, the interconnecting lead on substrate or the printed circuit board (PCB).
The present invention has enumerated a plurality of embodiment of memory module in the computer system, and these descriptions also are not intended to limit the scope of the invention.Device of the present invention or technology also can comprise a plurality of separate, stored modules, and adopt in the data communication system of communication.Similar, memory module also can be as on the substrate that intercoms mutually.In the specific implementation, adopt product what kind of physical composition is arranged, mainly depend on the technical foundation and the economic base in product design stage.
Fig. 1 and Fig. 2 have enumerated symbol and term that the embodiment of the invention may be used.Doing like this is for convenience, clear, consistance and succinct purpose, and those skilled in the art the present invention has as can be known used the more close term of a lot of meanings.But the present invention should be limited to definition of the present invention to the understanding of these terms.But the present invention to the definition of term can not limit these akin terms through after be used to represent identical implication in the development.
Fig. 1 illustrates an example structure figure of system of the present invention, comprise a CPU (central processing unit) (CPU, centralprocessing unit), one Memory Controller Hub (MC, memory controller) and a plurality of memory module (MM, memory module) and a system clock (SYSC, system clock).Other of computing machine are formed structures, external interface for example, and massage storage, display, power supply or the like equipment also can comprise in embodiments of the present invention, but in these equipment drawings 1 and not shown.Except the cache memory that does not illustrate among Fig. 1, magnetic disk memory, outside the storer of tape memory and other types, system of the present invention for example also can comprise erasable or scratch pad memory not such as random access memory and flash memory, with programmed instruction and the data that realize that fast access is used by system program or controls.Storer of the present invention can connect by Memory Controller Hub and CPU, and storer of the present invention can comprise a plurality of memory modules.
Between a plurality of memory modules and can be between memory module and the Memory Controller Hub by being electrically connected, P.e.c. connects, and perhaps the circuit ways of connecting connects, above-mentioned being electrically connected, P.e.c. connects, and perhaps the circuit connection can be commonly referred to as bus, line or passage usually.In the present embodiment, be connected in series mutually between some memory module, such as the connection between memory module 1 and the memory module 2, other memory modules are connected respectively with other a plurality of modules, for example memory module 2 links to each other with memory module 3, and memory module 2 links to each other with memory module 4 simultaneously.
In synchro system, system clock is distributed in a plurality of modules in certain zone (such as, memory module) so that a plurality of memory modules in the memory module group have an opportunity to obtain to have the clock source of conventional frequency.Clock frequency by the derivative a large amount of clocks of system clock system may be the multiple of system clock frequency, perhaps factor.Therefore, be included in a plurality of clocks in the system that clock may be system clock multiple or factor, can have identical frequency, but have time delay or phase differential.This difference can represent with the difference in stage clock period, in other words, and when describing phase differential, 0,90,180, the phase differential of 270 degree can be described as differing 0 clock period respectively, differ 0.25 clock period, differ 0.5 clock period and differ 0.75 clock period.Because temperature or circuit are aging, phase differential will be followed the time and slowly be changed.Slowly variation described herein can be regarded as characters a large amount of before phase differential generation marked change and may be transmitted away, therefore need the compensation or the calibration of phase differential also be changed.
Because all clock frequencies of data are identical, or relevant with same clock, through after a plurality of modules, do not need the clock delay in each module to be compensated by filling character.Similar, when transmitting frame by frame, also can be without sync character.In other embodiments, because the clock frequency in a plurality of modules is identical, so the interval between data transmission or targeting sequencing sign indicating number all can be avoided.
As control timing, can carry out operations such as data processing and computing by various clocks, and obviously, aforesaid operations can be carried out in rising edge of clock signal, perhaps both carried out, also carry out at the negative edge of clock signal in rising edge of clock signal.The clock of the control a kind of operation in back is referred to as Double Data Rate (DDR, double-data-rate) clock usually.Be simplified illustration, the embodiment of the invention is illustrated with the running of rising edge clock, and those skilled in the art can know the mode of operation of the system that adopts DDR on basis of the present invention.In addition, in the specific implementation, also can adopt the clock of other type.
Fig. 2 defines the agreement in the circuit of equipment of being applied in and equipment room, and described circuit can be connecting line or bus, and it can be connected between two equipment, between two memory modules.Data can in the updrift side transmission or in the downstream direction transmission, so-called updrift side be meant that data flow includes a side of control port, and such as flowing to Memory Controller Hub or CPU end, downstream direction is then opposite.Data bus can be reconstructed usually, and updrift side and downstream direction just can exchange like this.In addition, except that adopting updrift side or downstream direction, also can define by the transmission direction of north-south to data.
Carrying out the equipment purpose of connecting by data bus, connecting line or passage is in order to transmit data, address and order at high speed.But the data channel type is various, and data channel includes one group of data circuit usually, and it can use one-way communication circuit, bidirectional line or differential signal technology.At present embodiment, data channel adopts differential line, and it is provided with pair of lead wires on mainboard, and this ends in the memory module in the differential signal circuit lead-in wire.(differential line is shown signal wire in the drawings).Current, this connected mode is used on the high speed interface.The connected mode of any kind, all can be used by the embodiment of the invention comprise that optical fiber connects or wireless connections etc.
In one embodiment, described data channel can comprise one group of one-way communication circuit.In embodiments of the present invention, can provide ten one-way communication circuits, wherein nine communication lines will be used always, and the tenth communication line can be used as extension wire.Certainly, one group of one-way communication circuit of the embodiment of the invention also can comprise more one-way communication circuits, and its extension wire that provides also can be more.Certainly, extension wire is also nonessential in practice.Data can be transmitted in data channel by the form of character, and the character of indication had in the clock period here can fixing length, and the bit number that comprises in the described character also can be relevant with the periodicity of clock.In the present embodiment, a character comprises 20 bits, and is relevant with 20 clock period.The character that transmits on many data circuits can further constitute a plurality of logic families and can claim that these logic families are frame.Shown in Fig. 2 a, a character in each active line may be relevant with a character on another active line, and the current character with other of described another character transmits in the lump.But, the character that transmits on each separate lines do not need to realize in time bit synchronously, and can differ transmission time of at least one bit in time, and described difference also can be a non-integer bit.
The control of the transmission of data from first module to second module can be carried out sending module, and so described receiver module can receive described data under synchronous clock frequency.
Similar passage may be deposited in the opposite direction.The propagation of signal can be discussed at downstream direction on this basis; , clearly signal also has similar characteristics in the propagation of updrift side.
The path of character from upstream equipment (such as Memory Controller Hub or memory module) to upstream device (such as memory module) can be described as a jumping.For describing more accurately, the ground that is without loss of generality can think that one jumps to be meant that data transmit between two memory modules.When being used for describing that physical connection between two memory modules of jumping concern, adopt circuit or sets of lines usually, and these sets of lines are generally, such as, the lead-in wire on the printed circuit board (PCB), additional devices such as connector, and send and the reception electrical interface.And passage is generally used for describing the assignment of logical of the character data in the frame.Operation by Memory Controller Hub or memory module and other similar devices thereof, each paths is assigned with (or binding) to passing through Memory Controller Hub, one circuit of memory module or other device control, and passage can be along with jumping the different of position or changing along with the different of time with this binding relationship of circuit.In the present invention, in case system finishes configuration, it is fixing that the binding of passage and circuit is then thought, but this binding relationship has nothing in common with each other in each memory module.That is to say that in each was jumped, the binding relationship of passage and circuit was established in early days system configuration, and keeps, in the time of perhaps will lasting till system's reconstruct next time in the whole service process of system.Jump in difference, passage can be tied on the different circuits, and the purpose of doing like this is in order to control or in order to reduce or to reduce, the time-delay of the character arrival object module in the frame.
If module initialization and test are all finished, the configuration of frame is also finished, and the passage of frame distributed to the circuit of module, can think that then the transmission channel of module and intermodule or transmission line set up.
One group of circuit of output is called the output subport from the module (this module connects by jumping with another module) of downstream direction, and the reorganization link tester is crossed the input subport and entered another module.Equally, also there is similar subport in updrift side.What link to each other with jumping between two equipment inputs or outputs subport and can be referred to as port.
Can comprise route data in the frame data, this shows needs address information that the data in the particular frame are routed to object module.Described particular frame can be the frame that is transmitting on the current circuit, the frame that transmits on another circuit or be follow-up frame with transmission on the current circuit.It is the data of mentioning in 11/405, No. 083 patent that described route data can be the patent No..In addition, the mode that data address is provided and carries out the data route of other known to those skilled in the art all can adopt in the present invention.Passage may not comprise routing channel, the command character that can comprise, address character or data character.
Fig. 2 b illustrates the physical interface of two intermodules, and described module can be memory module.Many groups of lead-in wires on the mainboard can connect by connector.Available one or more connector inserts mainboard to link to each other with the wiring of printed circuit board (PCB) with memory module.Other, such as power supply, power supply control, clock or p-wire etc. also can be connected on the mainboard, but Fig. 2 b does not illustrate.
Fig. 3 shows the simplified block diagram of a memory module, and downstream passage only is shown.Among Fig. 3, input end P
0Comprise the n circuit-switched data, be assumed to be 10 the tunnel at this.Suppose that the module among Fig. 3 can constitute binary tree, so output terminal P
1And P
2Should comprise 10 tunnel output signals respectively.According to the routing iinformation that comprises in the route data or according to other routing policies, P
0The data that the place receives can send to any storer in the memory module or can send to output terminal P
1Or P
2
But memory module associative storage, described storer can be integrated into described memory module inside or communicate with described memory module, and described storer can be in the aforementioned various storeies of mentioning any.Described storer is replaceable to be output port or additionally be connected with output port, this output port is used to connect other computing machines, communication facilities or other external units, therefore pass through memory address, can be from described memory module output data to display, equipment such as the network port, perhaps from display, or equipment such as network port input data are to described memory module.
The equipment that is used to carry out route and other correlation functions can be described as configurable switch element (CSE, configurable switching element).Fig. 4 illustrates the modular construction of CSE.At present embodiment, the memory module circuit may operate under a plurality of different clock frequencies.A plurality of clock frequencies offer convenience for the operation of system; But electronic component still is necessary for system provides efficiently fast, and all operations of CSE all can carry out under the clock frequency of routine, and described clock frequency can be identical with the data transfer rate of bus.System clock can be distributed to the memory module of a plurality of these system clocks of needs.The bit clock rate of the serial data of transmitting in the speed of system clock and the circuit of each jumping can be inequality, and in addition, clock frequency frequency multiplier or frequency divider can be set at memory module or other places of system, so that derive from local clock.The clock of serial data can be the multiple or the approximate number of system clock, and the part-structure of memory module can be operated in different clock frequencies so: such as, be operated in switch clock frequency (SWC, switch clock rate).In the present embodiment, the data transfer rate clock frequency is 16 times of system clock, and the exchange clock frequency is 4 times of system clock.Other clock frequencies also can be applicable in the memory module.Other clocks that the present invention uses can be not relevant with system clock.
To being connected to the discussion of a circuit in the memory module, can be used as the representative of All other routes operation.Input end P
0Can connect a mimic channel and be used to provide impedance matching, comprise the bandwidth filtration and the unlike signal on the circuit is converted to electric signal so that follow-up data processing or control.As previously mentioned, suppose that memory module disposes according to other equipment of system in advance, comprises the adjustment of clock or the setting of clock skew; Like this, the configuration of system, error detection, error correction, and similarly flow process is no longer carefully stated at this.
As shown in Figure 4, the signal of receiving circuit (RX, receiver circuit) output is handled by clock and data recovery (CDR, clock data recovery) circuit.By deserializer (DES, deserializer) data are converted to parallel schema so that data can be handled by parallel from serial mode under lower SWC clock frequency environment, such as in on-off circuit (SW, switch circuity), carrying out parallel processing.Described clock data recovery circuit can be any in the known data recovery circuit, such as can be delay phase-locked loop (DLL, delay locked loop) or phase place phaselocked loop (PLL, phase locked loop) etc., use the purpose of clock data recovery circuit to be to set up a restore data clock (RDC, recovered data clock), there is fixing relation in the position of described restore data clock and data bit.Described restore data clock is used in data and the data of transmitting on the circuit is sampled when effective.Because the sampling time is calibrated, therefore the sampled data based on the described sampling time can not be the data at the data boundary place of distortions of transmitted data rate maximum.Described restore data clock can be calibrated by the border of character when system initialization.
Because system clock propagates into the travel path difference of different memory modules from the conventional system clock, the time delay difference that each memory module exists, and the difference between adjacent memory module is propagated the propagation delay difference of circuit, there is a phase differential (or having a bit mistiming at least) between restore data clock and the local clock (DC, locally generated data clock) that produces.
The difference of propagation delay can be described as time-delay deviation between memory module, and described time-delay deviation can comprise variable and constant.Simultaneously, the extra propagation delay difference on each memory module circuit also should be included in the time-delay deviation, and time-delay deviation is generally used for describing the summation of all delay inequalities, except the special circumstances.Such as, travel-time between memory module can comprise that signal is the travel-time on the lead-in wire of mainboard (velocity of propagation of signal on lead-in wire is greater than 1/2nd of the light velocity), also can comprise the propagation delay in the filtrator of receiver of filtrator in the transmitter of a memory module and current memory module, also can comprise propagation delay in the digit buffer etc.In addition, mimic channel comprises limited bandwidth, when mimic channel work near bandwidth in limited time, in signal processing, also can produce extra propagation delay.
Propagation delay can be understood that phase delay or time time delay.Mimic channel may comprise clock period sequence time delay, described time delay may since the parameter of element cause, such as may be because due to the temperature factor.After the long time, catabiosis may take place in system equipment in experience.Therefore, first bit of the character of reception can not obtain in advance with phase place and time relation between corresponding memory module clock border.When travel-time in describing a stable circuit and mistiming, a very long time express time difference continues time in a certain clock frequency greater than a bit of character.
At configuration phase, can calibrate clock and data, and be character or frame boundaries on every circuit with the character after the calibration, signal keeps window, and the restore data clock is set up incidence relation.Keep the incidence relation of described foundation by DLL or PLL, and described restore data clock also can be used for controlling DES.Described DLL or PLL can upgrade by ce circuit, even the propagation delay of circuit changes like this, sampled point can remain in the effective data window.Here the factor that changes of the propagation delay of circuit may be that the change of environment causes, such as the change of temperature.That is to say that even the propagation delay of circuit changes, the relation on specific clock bit among the RDC and the circuit between 0 bit of character can not change all the time.Because the change of the propagation delay of circuit is slower for frame or character rate, therefore, DLL or PLL can upgrade in real time.According to the design of system, if data do not have to transmit on the consistently online road, then need regularly to carry out synchronous transmission and come RDC is adjusted, to keep system synchronization.
Fig. 5 shows the conversion synoptic diagram that serial data stream (bit of character is arranged with straight line) is converted to parallel data stream, character (comprising 20 bits in the present embodiment) after handling under the restore data clock frequency, is respectively 1/2nd and four/for the moment being sent in the module of data rate of circuit in clock frequency in DES.Further, the interplanar logical relation of data bit and switching logic is also shown in Figure 5, and wherein, each plane is operated in the switch clock frequency.Other logical data allocations modes can be accepted equally.In the present embodiment, in the process of transformation from serial to parallel, character is not fully by unserializing.Just, adopt four inner passages (plane A-D) to carry out parallel transmission in the present embodiment, so data are not converted to parallel data fully.Equally, if logistics is enough effective, the serial character that character can be complete is processed, and does not need to carry out serializing or unserializing.
If shown in the figure is the duration rather than the logical relation of bit, can know clearly that in the half rate zone, the time interval between the successive bits is the twice in full rate zone, and in 1/4th rate areas, the time interval between the successive bits is four times of full rate zone.The character of Jie Shouing is registered as even bit and odd bit in the present embodiment, and this expression mode only is used for being convenient to describe and can not be used to be limited to the type of the data that module transmits.
Phase alignment impact damper (PAB, phase alignment buffer) is used for by the internal switch clock data of deserializer output being calibrated.Input end and output terminal at switch are respectively equipped with switch clock SWC
1And SWC
11Be used for being input to respectively the phase alignment impact damper phase alignment impact damper 1 and the phase alignment impact damper 2 that lay respectively at switch input terminal and output terminal.And described switch clock SWC
1And SWC
11Can have identical clock frequency with switch clock SWC, but SWC
1And SWC
11All can and SWC between have metastable phase place or mistiming.
In one embodiment, the bit length that comprises in the phase alignment impact damper may be less than the length of a character, is disclosed routing policy in 11/405, No. 083 United States Patent (USP) if adopt the patent No. like this, at receiving end, routing iinformation may be received early than a complete character data.Concrete, the length of phase alignment impact damper can be lower than the length of 18 bits, and can be the length of 5 bits.
In the present embodiment, character is assigned in four packets and transmits, and each packet comprises five Bit datas in described four packets, and the clock frequency of switching rate clock is 1/4th of the local data clock that produces in the present embodiment.The phase alignment impact damper will be operated so that the 0th bit of the character of importing aimed at the reference position of switching rate clock.Like this, the bit of the continuous transmission in the described character (first bit, second bit and the 3rd is than top grade) can be aimed at (phase place that is respectively 90,180 and 270 degree) respectively with the respective phase of switching rate clock.
Above-mentioned packet can be handled in switch, so that can be routed in the storer, perhaps is routed to the output terminal P of memory module
1Or P
2To the route of data, can change according to the data character that receives.In addition, described switch also can divide into groups to shift, such as, will be in.Input end P
0Circuit 1 on grouping transfer to output terminal P
1Circuit 3 on.Relation between logic groups and physical circuit is static, the two is carried out related operation can be described as " binding ".In this case, the character of input can be routed to local storer in vain, or is routed to other modules.And be grouped into the allocation scheme of circuit, be used in the datum target receiving end and manage intercharacter deviation.Extension wire is used for description and is connected between the two-port, but is not used in the circuit of binding data grouping.
Interface class between switch and module storage is similar to the interface of module and intermodule, and described interface is used to receive data and sends to local storage or receive data from local storage.Described reception can comprise calibrates and transmitted frame is given storer the character in the frame.Data recovery technique is disclosed in 11/405, No. 083 the United States Patent (USP) in the patent No..
After switch process, data will send to output port (such as, output terminal P
1Or P
2), it is identical with the mode that data is inputed to the output phase calibration impact damper that is positioned at the switch rear end to send data to the mode of output port.Described output phase calibration impact damper is used for locating the 0th bit of character calibrated with the clock border of the local data clock that produces at output deserializer (SER), and described deserializer was created in the system configuration stage.Because the stage of the processing of being undertaken by switch is approximately synchronous phase, therefore, the deviation between switch clock and data clock can be thought to remain unchanged relatively after generation.Therefore, the time-delay of a Bit data in switch is constant substantially.For data clock, phase place or the relative input time of importing the data of every circuit can be inequality.The specific clock period that output phase calibration impact damper can be used for being utilized as the data clock that circuit provides calibrates the bit of the data character that transmits on the described circuit.Described calibration is to carry out on the basis of line line by line, because the character in the Frame is separately handled, so just need not carry out synchronous to these characters at each place of choosing so again.
Described staticizer then reconfigures bit and is character, the character after the reorganization with split before the character that transmits on the line have identical sequential.That is to say, the relation at the edge of the 0th bit of Chuan Shu N character and data clock next, with the edge of the 0th bit of the earliest character and data clock concern a hysteresis 20N clock period, herein, N is a positive integer.Therefore, be transmitted even without character, the sequential of character still is held.The data of described staticizer output can send to next-hop node after radiating circuit (TX) locates to be converted into different simulating signals.
Character on the All other routes is handled in the same manner.But different circuits has independently clock data recovery circuit, and between the restore data clock of different circuits, and can have different phase places between described restore data clock and the switching rate clock.The variation of phase place also may rely on different factors on every circuit, such as time or temperature, or relies on the composition of circuit, and described circuit is formed and comprised Route Length, the characteristic of amplifier or filtrator etc.
Fig. 6 shows one of switch and simplifies functional structure chart.As shown in Figure 6, described switch comprises two derailing switches, a passage converting unit (LEG, lane-exchange grid) and a port translation unit (PEG, port-exchange grid).As shown in the figure, a LEG only is shown herein, but in fact can comprises one or more LEG, or in specific design, can not need LEG at the output terminal of switch.Herein, the incoming line of LEG (0-9) and multichannel (such as, A-J road) several 0 be according to being associated, such as, road A is associated with incoming line 0.Data may be transmitted to output terminal P
1, such as, road A can be associated with incoming line 3.LEG or PEC can be by bindings, and the mode of conversion or route sends to output line and output port with character from incoming line.Circuit B-J can determine that each road signal of incoming frame all can be routed on the specific physical circuit of output terminal like this when the system configuration to the binding relationship of outlet line 1-9.Certainly, road A also can bind with other outlet lines.The binding relationship of road and circuit can change between the port of module, also can change in module and intermodule.
Through after the above-mentioned stage, time delay constantly changes in data transmission procedure immediately, in the bit of the character that transmits in the Memory Controller Hub and the operational blocks which partition system edge of data clock between concern and can remain unchanged.
The describe, in general terms of time delay such as Fig. 7 A and 7B.Shown in Fig. 7 A, propagation delay D1 represents the propagation delay between the output data of the output data of first memory module and second memory module.Keep the propagation delay of data in each passage to remain unchanged substantially and will first bit of the character that transmits in the circuit and the edge of data clock are consistent, its state that the is presented when state of described data clock is in the system configuration end always.Time delay D 1 is the summation of time delay D 2 and D3, and wherein D2 may be not relevant with switch, and D3 is then relevant with switch.As time goes on, time delay D 2 and D3 may be owing to environmental factor change, and still the variation owing to time delay can be compensated by the phase alignment impact damper, so the overall delay of system remains unchanged substantially.Specifically please refer to Fig. 7 B.Herein, remaining unchanged substantially can be regarded as, because the adjustability of circuit system, after not needing second synchronization, the change of total propagation delay of first bit in the character can be greater than the duration of a bit passing through synchronous processing.
Through the description of front, be in system clock in the module and the time delay between system clock source (may not be arranged in any module) and be identified as a fixed value.Certainly this time delay also may be along with time and environment change, but because the phase alignment impact damper in each module can be to the data clock, compensate the relative time delay that exists between switching rate clock and restore data clock, therefore, the time delay of final system clock also just can be compensated.
Through the description of front, need in the input phase calibration impact damper of memory module, not cushion the variation that a time delay of jumping adjusted in one or more complete characters in the present embodiment.The capacity of described phase alignment impact damper can be approximately the variable quantity of the time-delay deviation on described one circuit of jumping, rather than the summation of the variable quantity of all time-delay deviation of jumping onto all circuits.In the system configuration stage, data are placed on the appropriate location of described impact damper, so that described data are buffered in the described impact damper all the time at whole transmission cycle.
(0074) adopt the benefit of phase alignment impact damper to be, on the basis of considering the influence that environmental factor changes deviation, the overall delay of optimal Storage module.When on data are comprising the passage of multihop link, transmitting, with existing, on the intermediate module of data transmission data are recovered and compare by the scheme that the mode that increases time delay is eliminated deviation, the advantage of present embodiment scheme is to reduce storer and controls to total time delay between object module.In existing described scheme, can on one or more circuit of data initialization module or target receiver module, increase time delay with the removal deviation, or can constantly increase time delay with the total deviation of optimization system at whole configuration phase.
Relation between the data on data clock and the circuit (can be described as synchronized relation) in case just set up can not change, like this when data when two intermodules transmit, if there is not the restriction of bandwidth or delay, described data do not need to transmit continuously.When not having circuit, power supply can not have loss ground to pass to receiving end from transmitting terminal, and passes to another electronic circuit from an electronic circuit of clock data recovery circuit.Because data can send to the storer of memory module or any of two output ports from input port, therefore, when described two output ports do not need to use, can be closed.
A certain circuit in the sets of lines in the subport may keep active state to be used to send signaling message always, and such as current being on the invalid link of All other routes Frame of reminding in the sets of lines, or reminding data carries out refresh operation.But system still can comprise signal meter (SM), is used for designation data existence in the line, to start receiver and interlock circuit.Therefore, in the system stable operation process, data circuit can be in dynamic or static, and when data circuit was in dynamical state, data or clock can be transmitted.Data described herein can be routing iinformation, command messages (comprising address information), storage data or reading of data etc.
Above disclosed is preferred embodiment of the present invention only, can not limit the present invention's interest field certainly with this, and therefore the equivalent variations of doing according to claim of the present invention still belongs to the scope that the present invention is contained.
Claims (22)
1. an interconnection system is characterized in that, comprising:
First node;
Section Point, described Section Point and described first node communicate;
First clock, described first clock is provided for described first node and described Section Point; And
Second clock exists first integral relation and relative first clock to have time-delay with first clock, so that the transmission time of bit between first node output and Section Point output keeps constant substantially.
2. the system as claimed in claim 1 is characterized in that, described first node and described Section Point communicate by bus.
3. system as claimed in claim 2 is characterized in that, to have the clock frequency of second integral relation with described first clock, transmits the character of being made up of bit in a continuous manner between described first node and described Section Point.
4. system as claimed in claim 3 is characterized in that, described first integral relation is identical with described second integral relation.
5. system as claimed in claim 3 is characterized in that, to be lower than the clock frequency of second clock, the character that receives is converted to a plurality of serial data packet from serial data format.
6. system as claimed in claim 5 is characterized in that, the time-delay of described second clock is adjusted to such an extent that to make bits switch identical in the character of back be bit identical in the serial data packet.
7. system as claimed in claim 5 is characterized in that, each serial data packet is routed to arbitrary storer or route and gives another node.
8. system as claimed in claim 7 is characterized in that, described route is determined by the character that receives.
9. system as claimed in claim 7 is characterized in that described character is routed to another node, and described data are by the serializing again of described second clock.
10. system as claimed in claim 9 is characterized in that, the data of described serializing again by in the circuit that connects two nodes any one transmit.
11. system as claimed in claim 10 is characterized in that, the data of described serializing again and a line bonding of selecting from described circuit.
12. the system as claimed in claim 1 is characterized in that, the time-delay of passage is adjusted so that when the output measurements at the output of first node and described Section Point, total time-delay of described passage is constant substantially.
13. system as claimed in claim 12 is characterized in that, the character on the circuit in many circuits is converted to a plurality of serial data packet by serial data format, and the character in this character and described many circuits on another circuit is independent mutually.
14. system as claimed in claim 13 is characterized in that, the amount of bits that comprises in the quantity of described serial data packet and the described character equates.
15. the node in the interconnection system is characterized in that, comprising:
Data receiver circuit;
Data transmit circuit;
The switch that links to each other respectively with described data receiver circuit and described data transmit circuit;
Circuit, first bit that can keep a certain character in the character that comprises a plurality of bits of sampling time and reception is in stable relations;
Input Data Buffer is used for described first bit is sampled again, so that corresponding overall delay between the sampling bits again remains unchanged substantially in the bit of described sampling again and another module.
16. node as claimed in claim 15 is characterized in that, described circuit is a data clock recovery circuit.
17. node as claimed in claim 15 is characterized in that, the clock frequency of described Input Data Buffer is the factor of data clock frequency.
18. node as claimed in claim 15 is characterized in that, the character route that described switch is used for receiving gives storer at least one other node or route.
19. node as claimed in claim 15 is characterized in that, described switch is with data clock frequency output data.
20. node as claimed in claim 15 is characterized in that, described Input Data Buffer can be used for the character that will receive again sequence turn to a plurality of packets;
Described node also comprises output data buffer, can be used for the data of described switch output again sequence turn to character.
21. node as claimed in claim 15, first circuit of described character in many circuits of first port is received, and a circuit of selecting in many circuits by second port is transferred to another node.
22. a method of controlling interconnection system, described system comprise a plurality of nodes that communicate with one another; Described method comprises:
To comprise that the character in the data of a plurality of bits is transferred to Section Point from first node;
Go out to receive described character at described Section Point;
Recovered clock and adjustment are to the sampling time of described character from the data of described reception;
And, the clock frequency that with frequency is the factor of described clock frequency is sampled to the data of sampling again, and adjust described phase place or the time-delay of carrying out again sampling clock, so that the overall delay between the character on the character of first node transmission and the same passage that transmits from Section Point is constant substantially.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US99789907P | 2007-10-05 | 2007-10-05 | |
| US60/997,899 | 2007-10-05 | ||
| PCT/US2008/078752 WO2009046300A2 (en) | 2007-10-05 | 2008-10-03 | Mesosynchronous data bus apparatus and method of data transmission |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101836193A true CN101836193A (en) | 2010-09-15 |
| CN101836193B CN101836193B (en) | 2012-10-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008801113298A Active CN101836193B (en) | 2007-10-05 | 2008-10-03 | Mesosynchronous data bus apparatus and method of data transmission |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP2201463A4 (en) |
| JP (1) | JP2011502293A (en) |
| KR (1) | KR101132321B1 (en) |
| CN (1) | CN101836193B (en) |
| WO (1) | WO2009046300A2 (en) |
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| CN103051441A (en) * | 2013-01-23 | 2013-04-17 | 和记奥普泰通信技术有限公司 | FPGA (field programmable gata array)-based clock data recovery processing method |
| CN106033231A (en) * | 2015-03-16 | 2016-10-19 | 联想(北京)有限公司 | Information processing method, clock division device, and information processing system |
| CN112463671A (en) * | 2020-12-04 | 2021-03-09 | 上海君协光电科技发展有限公司 | Data delay system, method and device, computer equipment and storage medium |
| CN113360130A (en) * | 2021-08-11 | 2021-09-07 | 新华三技术有限公司 | Data transmission method, device and system |
| CN114495998A (en) * | 2021-12-15 | 2022-05-13 | 西安紫光国芯半导体有限公司 | Data storage and electronic device |
| CN117574819A (en) * | 2023-11-14 | 2024-02-20 | 上海奎芯集成电路设计有限公司 | Received data deviation adjusting circuit and received data deviation adjusting method |
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| CN101990089B (en) * | 2009-08-07 | 2013-01-02 | 宏碁股份有限公司 | Streaming audiovisual data transmission control method and equipment thereof |
| KR101579054B1 (en) | 2014-03-26 | 2015-12-21 | 한국원자력의학원 | Radiosensitizer containing podophyllotoxin acetate as the active ingredient |
| CN108259134B (en) * | 2018-01-10 | 2021-04-13 | 上海灵动微电子股份有限公司 | Data transmission method based on AFP protocol |
| KR102090554B1 (en) | 2018-04-13 | 2020-03-18 | 한국원자력의학원 | Radiosensitizer containing β-Apopicropodophyllin as an active ingredient |
| WO2021031153A1 (en) * | 2019-08-21 | 2021-02-25 | 华为技术有限公司 | Data processing device and system |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103051441A (en) * | 2013-01-23 | 2013-04-17 | 和记奥普泰通信技术有限公司 | FPGA (field programmable gata array)-based clock data recovery processing method |
| CN103051441B (en) * | 2013-01-23 | 2015-03-18 | 和记奥普泰通信技术有限公司 | FPGA (field programmable gata array)-based clock data recovery processing method |
| CN106033231A (en) * | 2015-03-16 | 2016-10-19 | 联想(北京)有限公司 | Information processing method, clock division device, and information processing system |
| CN106033231B (en) * | 2015-03-16 | 2020-03-24 | 联想(北京)有限公司 | Information processing method, clock frequency division device and information processing system |
| CN112463671A (en) * | 2020-12-04 | 2021-03-09 | 上海君协光电科技发展有限公司 | Data delay system, method and device, computer equipment and storage medium |
| CN113360130A (en) * | 2021-08-11 | 2021-09-07 | 新华三技术有限公司 | Data transmission method, device and system |
| CN113360130B (en) * | 2021-08-11 | 2021-10-29 | 新华三技术有限公司 | Data transmission method, device and system |
| CN114495998A (en) * | 2021-12-15 | 2022-05-13 | 西安紫光国芯半导体有限公司 | Data storage and electronic device |
| CN114495998B (en) * | 2021-12-15 | 2023-11-10 | 西安紫光国芯半导体有限公司 | Data memory and electronic device |
| CN117574819A (en) * | 2023-11-14 | 2024-02-20 | 上海奎芯集成电路设计有限公司 | Received data deviation adjusting circuit and received data deviation adjusting method |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2009046300A2 (en) | 2009-04-09 |
| KR20100098596A (en) | 2010-09-08 |
| WO2009046300A3 (en) | 2009-05-22 |
| KR101132321B1 (en) | 2012-04-05 |
| EP2201463A4 (en) | 2010-10-13 |
| EP2201463A2 (en) | 2010-06-30 |
| CN101836193B (en) | 2012-10-03 |
| JP2011502293A (en) | 2011-01-20 |
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