CN101136855B - Asynchronous clock data transmission device and method - Google Patents
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Abstract
本发明公开了一种异步时钟数据传输装置及方法。本发明装置包括:全局时钟计数单元,用于指示快速源时钟域的输入数据的序号;与全局时钟计数单元相连的多通道分配与控制单元,用于根据数据序号循环地对输入数据进行采样;与多通道分配与控制单元相连的同步控制单元,用于将采样到的数据同步到目标时钟域;与同步控制单元相连的字组装单元,用于将同步控制单元同步后的数据组装成组装数据。本发明方法步骤:指示快速源时钟域的输入数据的序号;根据数据序号,通过多个数据通道循环地对输入数据进行采样;将采样到的数据同步到目标时钟域;将同步后的数据组装成组装数据并输出。本发明装置及方法提高了传输效率,控制方法也更为简单。
The present invention discloses an asynchronous clock data transmission device and method. The device of the present invention comprises: a global clock counting unit, used to indicate the sequence number of input data in a fast source clock domain; a multi-channel distribution and control unit connected to the global clock counting unit, used to cyclically sample the input data according to the data sequence number; a synchronization control unit connected to the multi-channel distribution and control unit, used to synchronize the sampled data to the target clock domain; a word assembly unit connected to the synchronization control unit, used to assemble the data synchronized by the synchronization control unit into assembled data. The method steps of the present invention include: indicating the sequence number of input data in a fast source clock domain; cyclically sampling the input data through multiple data channels according to the data sequence number; synchronizing the sampled data to the target clock domain; assembling the synchronized data into assembled data and outputting it. The device and method of the present invention improve the transmission efficiency, and the control method is also simpler.
Description
技术领域 technical field
本发明涉及一种异步时钟数据传输装置及方法,尤其涉及一种从快速的源时钟域向慢速的目标时钟域传输数据时的异步时钟数据传输装置及方法。The present invention relates to an asynchronous clock data transmission device and method, in particular to an asynchronous clock data transmission device and method when data is transmitted from a fast source clock domain to a slow target clock domain.
背景技术 Background technique
在工程设计中,大多数跟数据传输相关的应用都涉及到跨越时钟域的数据移动,比如常用的磁盘控制器、网络处理器等。当信号从一个时钟域传送到另一个时钟域时,需要被当作异步信号进行处理。对于异步信号处理,最基本的问题是解决信号的稳定性问题,如果解决得不好,则接收到的异步信号可能处于不稳定状态,比如处于亚稳态,而且可能导致该不稳定状态在新的时钟域内传播蔓延,从而引起系统的功能故障。因此,当信号在异步时钟域间穿越时,通常需要通过同步器进行同步。当单比特信号在异步时钟域间穿越时,通常的同步器结构有电平同步器、边沿检测同步器和脉冲同步器等。In engineering design, most applications related to data transmission involve data movement across clock domains, such as commonly used disk controllers, network processors, etc. When a signal is passed from one clock domain to another, it needs to be treated as an asynchronous signal. For asynchronous signal processing, the most basic problem is to solve the stability problem of the signal. If the solution is not good, the received asynchronous signal may be in an unstable state, such as in a metastable state, and may cause this unstable state to be in a new state. Propagation spreads within the clock domain, causing functional failures in the system. Therefore, when a signal traverses between asynchronous clock domains, it usually needs to be synchronized by a synchronizer. When a single-bit signal traverses between asynchronous clock domains, common synchronizer structures include level synchronizers, edge detection synchronizers, and pulse synchronizers.
通常,通过目标时钟域同步器的同步后,就可以解决异步信号的稳定性问题。在更多的应用中,跨越时钟传送的不只是简单的单比特信号,而是通过数据总线、地址总线、及控制总线等传输大量的数据。这些数据信号同样在同步器的作用后,得到了稳定的信号。但由于异步信号的变化时间和目标时钟沿关系的不确定性,使得接收到的信号不一定正确。为了解决这个问题,通常的做法是采用握手和先进先出存储器(First In,First Out,简称FIFO)接口等方法。Usually, the stability problem of the asynchronous signal can be solved after being synchronized by the target clock domain synchronizer. In more applications, it is not just a simple single-bit signal that is transmitted across the clock, but a large amount of data is transmitted through the data bus, address bus, and control bus. These data signals also get stable signals after the action of the synchronizer. However, due to the uncertainty of the change time of the asynchronous signal and the relationship between the target clock edge, the received signal may not be correct. In order to solve this problem, the usual way is to adopt methods such as handshake and first-in-first-out memory (First In, First Out, referred to as FIFO) interface.
采用握手的这种方法,在源时钟域的数据有效时,传送根据单比特的数据准备好的指示信号给目标时钟域。目标时钟域在检测到该指示信号有效后,开始从数据总线上接收数据,并反馈数据已接收的应答信号给源时钟域。源时钟域在检测到该应答信号有效时释放数据有效指示和数据总线。在这个过程中,为了解决异步信号的稳定性问题,源时钟域的数据有效指示信号传递到目标时钟域,以及目标时钟域数据接收应答信号反馈到源时钟域都需要经过同步器进行同步处理,从而大大降低了这种通信方式的数据传输效率。This method of handshaking is adopted, and when the data in the source clock domain is valid, an indication signal prepared according to the single-bit data is transmitted to the target clock domain. After the target clock domain detects that the indication signal is valid, it starts to receive data from the data bus, and feeds back an acknowledgment signal that the data has been received to the source clock domain. The source clock domain releases the data valid indication and the data bus when detecting that the acknowledge signal is valid. In this process, in order to solve the stability problem of the asynchronous signal, the data valid indication signal in the source clock domain is transmitted to the target clock domain, and the data receiving response signal in the target clock domain is fed back to the source clock domain. Thus, the data transmission efficiency of this communication method is greatly reduced.
使用FIFO作为异步时钟数据传输的接口时,除了需要额外的FIFO存储空间外,还存在对FIFO的控制问题。在FIFO已经满的时候,不能再往FIFO中写入数据,这时如果还继续产生写操作,就会出现数据丢失现象;类似的,在FIFO为空时,不能再从FIFO中读取数据,这时如果还从FIFO中读取数据,则输出的数据就是不正确的。FIFO空满状态的判断,都需要对FIFO的读、写地址进行比较。但是它们在不同的时钟域内,为了进行比较,需要经过时钟域同步处理。虽然现在有较成熟的技术来解决这些问题,但是从快速时钟域向慢速时钟域传递数据时,在慢速时钟域这一侧,数据写入的速度比数据输出的速度还要快,这时使用FIFO结构就必须使FIFO的存储空间设置为无限大,否则会造成数据堆积效应,产生数据溢出问题。When using FIFO as an interface for asynchronous clock data transmission, in addition to requiring additional FIFO storage space, there is also a problem of controlling FIFO. When the FIFO is full, no more data can be written into the FIFO. At this time, if the write operation continues, data loss will occur; similarly, when the FIFO is empty, no more data can be read from the FIFO. At this time, if the data is also read from the FIFO, the output data is incorrect. The judgment of FIFO empty and full state needs to compare the read and write addresses of FIFO. However, they are in different clock domains. For comparison, clock domain synchronization processing is required. Although there are relatively mature technologies to solve these problems, when transferring data from the fast clock domain to the slow clock domain, the speed of data writing is faster than the speed of data output on the side of the slow clock domain. When using the FIFO structure, the storage space of the FIFO must be set to be infinite, otherwise it will cause data accumulation effect and data overflow problem.
发明内容 Contents of the invention
本发明所要解决的技术问题是为了提供一种异步时钟数据传输装置及其传输方法,用于在快速的源时钟域向慢速的目标时钟域传输数据时,高效、简单地实现数据的同步传输。The technical problem to be solved by the present invention is to provide an asynchronous clock data transmission device and its transmission method, which is used to efficiently and simply realize synchronous transmission of data when transmitting data from a fast source clock domain to a slow target clock domain .
为了解决上述技术问题,本发明首先提供一种异步时钟数据传输装置,包括:In order to solve the above technical problems, the present invention firstly provides an asynchronous clock data transmission device, including:
全局时钟计数单元,用于指示来源于快速源时钟域的输入数据的序号;The global clock counting unit is used to indicate the sequence number of the input data from the fast source clock domain;
多通道分配与控制单元,与所述全局时钟计数单元相连,配置有多个数据通道,用于每个所述数据通道根据所述数据序号,循环地对所述输入数据进行采样;A multi-channel allocation and control unit, connected to the global clock counting unit, is configured with multiple data channels, and is used for each of the data channels to cyclically sample the input data according to the data sequence number;
同步控制单元,与所述多通道分配与控制单元相连,用于将所述采样到的数据同步到目标时钟域;a synchronization control unit, connected to the multi-channel allocation and control unit, for synchronizing the sampled data to the target clock domain;
字组装单元,与所述同步控制单元相连,用于将所述同步控制单元同步后的数据组装成组装数据并输出。A word assembly unit, connected to the synchronization control unit, is used to assemble the data synchronized by the synchronization control unit into assembly data and output it.
根据上述的一种异步时钟数据传输装置,其中,所述多通道分配与控制单元中的所述每个数据通道,可以在各自的使能信号作用下进行所述采样。所述多通道分配与控制单元的数据通道个数,可以根据所述源时钟域的频率与所述目标时钟域的频率来确定。进一步地,所述数据通道个数,可以进一步采用Verilog语言及Verilog编译仿真器仿真来确定。According to the asynchronous clock data transmission device above, each of the data channels in the multi-channel allocation and control unit can perform the sampling under the action of its own enable signal. The number of data channels of the multi-channel allocation and control unit may be determined according to the frequency of the source clock domain and the frequency of the target clock domain. Further, the number of the data channels may be further determined by using Verilog language and Verilog compiling emulator simulation.
根据上述的一种异步时钟数据传输装置,其中,所述同步控制单元的同步,可以采用双握手通讯机制。According to the above asynchronous clock data transmission device, the synchronization of the synchronization control unit may adopt a double handshake communication mechanism.
根据上述的一种异步时钟数据传输装置,其中,所述字组装单元,可以进一步用于在所述每个组装数据组装完成后,均生成所述组装数据组装完成的标志信号,用于指示所述组装数据组装完成。所述字组装单元在进行所述组装时,所述同步后的数据组装成一个所述组装数据的个数,可以根据所述源时钟域频率和所述目标时钟域频率确定。According to the above-mentioned asynchronous clock data transmission device, wherein the word assembly unit can be further configured to generate a flag signal that the assembly of the assembly data is completed after the assembly of each assembly data is completed, which is used to indicate the The assembly data described above is assembled. When the word assembling unit performs the assembling, the number of the assembled data assembled from the synchronized data may be determined according to the source clock domain frequency and the target clock domain frequency.
根据上述的一种异步时钟数据传输装置,进一步包括数字信号处理器接口单元,与所述字组装单元相连,为所述装置提供数据输出接口。According to the asynchronous clock data transmission device above, it further includes a digital signal processor interface unit connected to the word assembly unit to provide a data output interface for the device.
在此基础上,本发明进而提供一种异步时钟数据传输方法,包括步骤:On this basis, the present invention further provides an asynchronous clock data transmission method, comprising steps:
(1)指示来源于快速源时钟域的输入数据的序号;(1) Indicates the sequence number of the input data originating from the fast source clock domain;
(2)根据所述数据序号,通过多个数据通道循环地对所述输入数据进行采样;(2) cyclically sampling the input data through multiple data channels according to the data serial number;
(3)将所述采样到的数据同步到目标时钟域;(3) synchronizing the sampled data to the target clock domain;
(4)将所述同步后的数据组装成组装数据并输出。(4) Assemble the synchronized data into assembled data and output it.
根据上述的一种异步时钟数据传输方法,其中,所述步骤(2)中,所述采样可以在所述数据通道各自的使能信号控制下进行。所述数据通道个数,可以根据所述源时钟域的频率与所述目标时钟域的频率确定。进一步地,所述数据通道个数,可以进一步采用Verilog语言及Verilog编译仿真器仿真来确定。According to the asynchronous clock data transmission method above, in the step (2), the sampling can be performed under the control of respective enable signals of the data channels. The number of data channels may be determined according to the frequency of the source clock domain and the frequency of the target clock domain. Further, the number of the data channels may be further determined by using Verilog language and Verilog compiling emulator simulation.
根据上述的一种异步时钟数据传输方法,其中,所述步骤(3)中,所述同步,可以采用双握手通讯机制。According to the above asynchronous clock data transmission method, wherein in the step (3), the synchronization may adopt a double handshake communication mechanism.
根据上述的一种异步时钟数据传输方法,其中,所述步骤(4)中,所述同步后的数据组装成一个所述组装数据的个数,可以根据所述源时钟域频率和所述目标时钟域频率确定。所述同步后的每个组装数据组装完成后,可以进一步生成数据组装完成的标志信号,指示所述组装数据组装完成。According to the above-mentioned asynchronous clock data transmission method, wherein, in the step (4), the number of the assembled data assembled into the synchronized data can be determined according to the frequency of the source clock domain and the target The clock domain frequency is determined. After the assembly of each of the synchronized assembled data is completed, a flag signal indicating that the assembled data is assembled may be further generated to indicate that the assembled data has been assembled.
根据上述的一种异步时钟数据传输方法,可以进一步包括步骤:According to the above-mentioned asynchronous clock data transmission method, it may further include steps:
(5)所述组装数据输出到一个数据输出接口供外部调用所述组装数据。(5) The assembly data is output to a data output interface for external calling of the assembly data.
本发明提供的一种异步时钟数据传输装置及方法,与现有采用技术相比,具有以下特点:An asynchronous clock data transmission device and method provided by the present invention, compared with the existing technology, has the following characteristics:
1)提高了传输效率;1) Improved transmission efficiency;
2)节约的设备成本;2) Saved equipment cost;
3)控制方法更为简单。3) The control method is simpler.
附图说明 Description of drawings
图1是本发明装置与方法构思示意图;Fig. 1 is a conceptual schematic diagram of the device and method of the present invention;
图2是本发明装置实施例结构示意图;Fig. 2 is a schematic structural view of a device embodiment of the present invention;
图3是本发明装置应用实施例多通道控制的相互关系示意图;Fig. 3 is a schematic diagram of the interrelationship of the multi-channel control of the device application embodiment of the present invention;
图4是本发明方法实施例流程示意图。Fig. 4 is a schematic flow chart of a method embodiment of the present invention.
具体实施方式 Detailed ways
以下结合附图和具体实施方式对本发明进行进一步的详细说明。The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.
参见图1,本发明的思路是:源目标域即快速时钟域的数据序列D1,在经过一个计数器的计数后,输入到相应一个异步时钟数据传输电路当中。该传输电路将源目标域的数据按照计数器给出的序号,进行数据组装,比如将第一号数据和第二号数据组装成一个数据,将第三号数据和第斯号数据组装成一个数据,以此类推。当然,根据具体的需要,也可采用其他组装方法。传输电路将组装后的数据序列D2,再通过一个数字信号处理器(DigitalSignal Processor,简称DSP)的CPU接口发送到目标时钟域即慢速时钟域内相关的数据处理单元上。基于此思想实现的异步时钟数据传输装置,将数据序列D1组装成数据序列D2,不仅可以提高数据传输的效率,而且也不会产生数据溢出的问题。Referring to FIG. 1 , the idea of the present invention is: the data sequence D1 in the source target domain, that is, the fast clock domain, is input to a corresponding asynchronous clock data transmission circuit after being counted by a counter. The transmission circuit assembles the data in the source and target domains according to the serial number given by the counter, for example, assembles the first data and the second data into one data, and assembles the third data and the third data into one data , and so on. Of course, other assembly methods can also be used according to specific requirements. The transmission circuit sends the assembled data sequence D2 to the relevant data processing unit in the target clock domain, that is, the slow clock domain, through a CPU interface of a Digital Signal Processor (DSP for short). The asynchronous clock data transmission device implemented based on this idea assembles the data sequence D1 into the data sequence D2, which can not only improve the efficiency of data transmission, but also avoid the problem of data overflow.
如图2所示,本发明的异步时钟数据传输装置,主要包括全局时钟计数单元201、多通道分配与控制单元202、同步控制单元203、字组装单元204,以及DSP接口单元205,其中:As shown in Figure 2, the asynchronous clock data transmission device of the present invention mainly includes a global
全局时钟计数单元201,相当于一个全局时钟计数器,用于指示来源于快速时钟域即源时钟域的输入数据的序号。全局时钟计数单元201产生的数据,送入多通道分配与控制单元202中。The global
多通道分配与控制单元202,与全局时钟计数单元201相连,配置有多个数据通道,每个通道在各自使能信号作用下,依据全局时钟计数单元201所输出的数据序号,连续循环地对全局时钟计数单元201的输出,进行数据采样。同一时刻,只有一个使能信号处于有效状态。这些通道在多通道分配与控制单元202和同步控制单元203的协同控制下,构成一个通道回环。该通道回环可以连续循环地采样快速时钟域输出的数据。多通道分配与控制单元202中的各个通道采样到各自对应的快速时钟域的数据后,送入同步控制单元203。The multi-channel allocation and
多通道分配与控制单元202中数据通道的个数,是根据源时钟域也即快速时钟频率和目标时钟域也即慢速时钟频率,用Verilog语言来描述转换通道的硬件,预定义通道个数为某一个数值M后,通过Verilog编译仿真器(Verilog Compiled Simulator,简称VCS)仿真来确定预定义通道数M的值。The number of data channels in the multi-channel allocation and
同步控制单元203,与多通道分配与控制单元202相连,用于将多通道分配与控制单元202各个通道采样到的快速时钟域的采样数据分别同步到目标时钟域。同步过程采用双握手通讯机制,以保证目标时钟域的时钟采样到的数据安全可靠,并消除亚稳态。同步控制单元203将同步后的数据送入字组装单元204中进行数据组装。The
字组装单元204,与同步控制单元203相连,用于将同步控制单元203同步后的数据组装成组装数据。组装数据的组装原则需要满足下面表达式:The
f1×n≥f2<f1×(n+1) (1)f 1 ×n≥f 2 <f 1 ×(n+1) (1)
其中,f1为慢速时钟的时钟频率,n为需要将多通道分配与控制单元202中通道数据组装到一起的通道个数,f2为快速时钟的时钟频率。也即慢速时钟频率f1乘上需要组装到一起的通道个数n,应该大于等于快速时钟频率f2。其理由为让相邻若干个通道的数据进行数据组装之后,再在慢速时钟域进行数据采样。这样就不会丢失源时钟域的数据,做到数据传输的准确无误。Wherein, f 1 is the clock frequency of the slow clock, n is the number of channels that need to assemble multi-channel distribution and channel data in the
假设分配与控制单元202中通道总数为M,按照表达式(1)所确定的组装字数为n,字组装单元204在进行数据组装时,需要遵循一定的组装原则。如果M刚好能被n整除,则M个通道数据刚好组装成M/n个组装数据;如果M不能被n整除,则M个通道数据需要组装成[M/n]+1个组装数据,其中的[M/n]为M/n的整数部分,组装方法是对M个数据中的前[M/n]*n个数据,依次进行组装,共组装成[M/n]个组装数据,对剩下的部分也即M-[M/n]*n个通道中的数据,组装成一个组装数据;对最后组装的这个数据,其位数不足部分,可以将其高位或者低位置为具有特定意义的数据,比如置为全零,或置为其他标志性数据等。Assuming that the total number of channels in the allocation and
字组装单元204在一个组装数据组装完成后,还相应地生成数据组装完成的标志信号,指示每个组装数据已组装完成。字组装单元204将组装后的组装数据,发送到DSP接口单元205中便于输出。After the assembly of one assembled data is completed, the
DSP接口单元205,与字组装单元204相连,为本发明数据传输装置提供数据输出接口,方便系统其他数据处理单元获得数据。经字组装单元204组装好的组装数据,通过DSP接口单元205传输到系统其他数据处理单元。DSP接口单元205在将组装后的组装数据传输到其他数据处理单元之前,还需要收到字组装单元204发出的数据组装完成的标志信号。也即字组装单元204在数据组装完成之后,还将生成的数据组装完成的标志信号也发送到DSP接口单元205,DSP接口单元205在接收到该标志信号后,才将组装数据传输到其他数据处理单元。The
按照本发明装置给出的组装原则和方式,组装后的数据不需再进行其他处理,从DSP接口单元205输出的数据顺序即同快速时钟域数据输入的顺序完全一致。According to the assembling principle and method provided by the device of the present invention, the assembled data does not need to be further processed, and the data sequence output from the
下面以61.44兆赫兹作为数据输入时钟,以50兆赫兹作为数据输出时钟为一应用实施例,来对本发明装置进行进一步的具体说明。也即源时钟域的工作频率为61.44兆赫兹,目标时钟域的工作频率为50兆赫兹。本发明装置还进一步假设61.44兆赫兹时钟域输入的数据宽度为32bits。The following uses 61.44 MHz as the data input clock and 50 MHz as the data output clock as an application example to further describe the device of the present invention in detail. That is, the operating frequency of the source clock domain is 61.44 MHz, and the operating frequency of the target clock domain is 50 MHz. The device of the present invention further assumes that the data width input by the 61.44 MHz clock domain is 32 bits.
全局时钟计数单元201相当于产生一个32位宽度信号的全局时钟计数器。在每个时钟产生一个32bits的数据,在本实施例中把这个32bits的数据定义为:bit0~bit4为采样计数值,bit5~bit16为码片计数值,bit17~bit20为时隙计数值,bit21~bit31为帧计数值。根据具体的应用,也可以把它定义为其它的含义。输入的数据是逐周期输出的32bits数据,在61.44兆赫兹时钟的上升沿发生变化,同样在61.44兆赫兹时钟的上升沿对数据进行采样。该32bits的计数单元由四个子计数器构成,其中,bit0~bit4为采样计数值,bit5~bit16为码片计数值,bit17~bit20为时隙计数值,bit21~bit31为帧计数值。在本实施例中,输入的数据可以是逐周期输出的32bits随机数。当然,也可以就把计数值本身作为输入数据进行测试。The global
多通道分配与控制单元202所配置的多个数据通道,在同步控制单元203的协同控制下构成一个通道回环。通道回环中的每个通道在各自使能信号作用下,连续循环地对全局时钟计数单元201所输出的61.44兆赫兹时钟产生的数据进行采样。同一时刻,只有一个使能信号处于有效状态。在本实施例中,用目标时钟域50兆赫兹的时钟来传输源时钟域61.44兆赫兹的时钟数据,需要十一个通道。每一个通道都对应地有一个采样数据和该采样数据的使能信号。在每个通道的使能信号下降沿时,对应的该通道就进行数据采样。这十一个通道在多通道分配与控制单元202和同步控制单元203的协同控制下,构成一个回环,从而可以连续循环地采样源时钟域61.44兆赫兹时钟所产生的32bits随机数。The multiple data channels configured by the multi-channel allocation and
本应用实施例中,多通道分配与控制单元202的十一个通道,是根据快速时钟频率61.44兆赫兹和慢速时钟频率50兆赫兹,用Verilog语言来描述转换通道的硬件,以及通过VCS仿真来确定的。In this application example, the eleven channels of the multi-channel distribution and
这十一个通道在存放61.44兆赫兹的输入数据时,采用如下方式:第一个通道采样有效的连续输入的随机数据的第一个32bit数据,第二个通道采样连续输入的随机数据的第二个32bit数据,以此类推,第十一个通道连续输入的随机数据的第十一个32bit数据。相邻通道的数据采样使能控制信号相差一个时钟周期,通道的相互关系如图3所示。When these eleven channels store the input data of 61.44MHz, the following method is adopted: the first channel samples the first 32bit data of the effective continuous input random data, and the second channel samples the first 32bit data of the continuous input random data Two 32bit data, and so on, the eleventh 32bit data of the random data continuously input by the eleventh channel. The data sampling enable control signals of adjacent channels differ by one clock cycle, and the relationship between the channels is shown in Figure 3.
图3中的clk_61.44表示源时钟域的时钟频率,gcc2[31:0]表示的是源时钟域需要传送到目标时钟域的数据的序号;而ch1_data[31:0]、ch2_data[31:0]、...、ch11_data[31:0]分别为这十一个通道的采样数据,ch1_en、ch2_en、...、ch11_en分别为十一个通道的采样数据使能信号。clk_61.44 in Figure 3 indicates the clock frequency of the source clock domain, and gcc2[31:0] indicates the serial number of the data that needs to be transmitted from the source clock domain to the target clock domain; and ch1_data[31:0], ch2_data[31: 0], ..., ch11_data[31:0] are the sampling data of the eleven channels respectively, and ch1_en, ch2_en, ..., ch11_en are the sampling data enable signals of the eleven channels respectively.
同步控制单元203在将各个通道采样到的61.44兆赫兹时钟域的数据分别同步到50兆赫兹时钟域的同步过程中,采用的是双握手通讯机制。The
在本发明的这一应用实施例中,由于源时钟域频率为61.44兆赫兹,目标时钟域频率为50兆赫兹,根据表达式(1),可以得出n为2,也即字组装单元204需要将同步控制单元203同步后的数据组装成双字数据。根据上述的组装原则可以得知,第一号通道和第二号通道的数据组装为一个双字数据,第三号通道和第四号通道的数据组装为一个双字数据,以此类推,直到一个循环内将最后一个通道的数据也组装完毕。具体的组装方式,可以选择将第一号通道的数据放在低位,第二号通道的数据放在高位;也可以颠倒过来,也即第一号通道的数据放在高位,第二号通道的数据放在低位。当然,将两个数据组装成一个数据的方法还有很多,在此并不一一列举。但本发明装置提出的这一优选的将第一号通道的数据放在低位,第二号通道的数据放在高位这一方式,是一种较优的常用方法。In this application example of the present invention, since the frequency of the source clock domain is 61.44 MHz and the frequency of the target clock domain is 50 MHz, according to the expression (1), it can be concluded that n is 2, that is, the
在本应用实施例中,多通道分配与控制单元202构成的通道回环中包含有十一个通道,也即通道数为奇数。在循环控制中,这十一个通道中的最后一个通道,也即第十一号通道,其采样到的数据,可能与源时钟域下一时钟周期的第一号通道数据相同,也可能不相同,对这两种情况应分别处理。如果第十一号通道与第一号通道采样到源时钟域的同一个序号的数据,则不输出该通道数据,也即将这最后一个通道的数据舍弃,并进入下一个循环;如果这最后一个通道和第一号通道采样到不是源时钟域的同一个序号的数据,则将该号通道的数据与其他相同位宽且具有特定意义的数据组装成一个双字数据。具有特定意义的数据比如包括全零或者指定标志性数据等。低32bit设置该通道的数据,高32bi相应地设置为该具有特定意义的数据。In this application embodiment, the channel loop formed by the multi-channel allocation and
在通道数为偶数时,刚好每两个通道的数据组装为一个双字数据。具体的组装方式参考上述通道数为奇数情况的描述。字组装单元204在将通道内的数据均组装成双字数据后,还相应地生成数据组装完成的标志信号。When the number of channels is even, the data of every two channels is assembled into a double word data. For the specific assembly method, refer to the above description of the case where the number of channels is odd. After the
从图3中可以看出,第十一号通道采样到的数据,和下一时钟周期第一号通道所采样到的数据相同。因此在进行双字组装时,将这第十一号通道采样到的数据丢弃,直接进行下一循环中的第一号通道与第二号通道数据的组装。It can be seen from FIG. 3 that the data sampled by the eleventh channel is the same as the data sampled by the first channel in the next clock cycle. Therefore, when double word assembly is performed, the data sampled by the eleventh channel is discarded, and the data of the first channel and the second channel in the next cycle are directly assembled.
经字组装单元204组装好的双字数据,通过DSP接口单元205传输到系统其他数据处理单元。The double-word data assembled by the
本发明在上述发明系统的基础上,进而提供一种异步时钟数据传输方法,用于从快速的源时钟域向慢速的目标时钟域传输数据时,高效、简单地实现数据同步传输。参见图4,本发明方法主要包括如下步骤:On the basis of the above inventive system, the present invention further provides an asynchronous clock data transmission method for efficiently and simply realizing synchronous data transmission when transmitting data from a fast source clock domain to a slow target clock domain. Referring to Fig. 4, the inventive method mainly comprises the following steps:
步骤401:首先通过全局时钟计数单元201,对作为源时钟域的快速时钟域的数据序列进行计数,指示来源于源时钟域的输入数据的序号。全局时钟计数单元201将计数完毕的数据传输到多通道分配与控制单元202中。Step 401: Firstly, the global
步骤402:多通道分配与控制单元202配置有多个数据通道。根据所述全局时钟计数单元201所输出的输入数据序号,在多通道分配与控制单元202和同步控制单元203的协同控制下,依据各自的使能信号,所有数据通道对从源时钟域所输入的数据连续循环地进行采样。Step 402: The multi-channel allocation and
步骤403:同步控制单元203将多通道分配与控制单元202的各个通道采样到的源时钟域的数据分别同步到目标时钟域。同步过程采用双握手通讯机制,以保证目标时钟采样到的数据安全可靠,并消除亚稳态。Step 403: The
步骤404:字组装单元204将同步控制单元203同步后的数据进行数据组装,并在每个组装数据组装完成后,相应地生成数据组装完成标志信号。在进行数据组装时,所遵循的组装原则如上所述,假设分配与控制单元202中通道总数为M,按照表达式(1)所确定的组装字数为n,如果M刚好能被n整除,则M个通道数据刚好组装成M/n个组装数据;如果M不能被n整除,则M个通道数据需要组装成[M/n]+1个组装数据,其中的[M/n]为M/n的整数部分,组装方法是对M个数据中的前[M/n]*n个数据,依次进行组装,共组装成[M/n]个组装数据,对剩下的部分也即M-[M/n]*n个通道中的数据,组装成一个组装数据;对最后组装的这个数据,其位数不足部分,可以将其高位或者低位置为具有特定意义的数据,比如置为全零,或置为其他标志性数据等。Step 404: The
步骤405:经字组装单元204组装好的组装数据,通过DSP接口单元205传输到系统其他数据处理单元。也即系统其他数据处理单元,通过DSP接口单元205这一数据输出接口,调用组装数据。DSP接口单元205在将组装数据传输到其他数据处理单元之前,还需要收到字组装单元204发出的数据组装完成标志信号。在接收到该标志信号后,DSP接口单元205才将组装数据传输到其他数据处理单元。Step 405: The assembled data assembled by the
通过本发明提出的数据传输装置及方法,不仅实现了异步时钟数据通讯过程中的数据同步问题,而且解决了从快速时钟向慢速时钟传输数据时使用握手机制时效率低下的问题,同时也解决了使用FIFO接口时需要无限大缓存空间的问题。本发明装置通过匹配不同的快慢速率,设置不同的通道数,就可以使得快速时钟域数据准确无误地传输到慢速时钟域,传输效率高。The data transmission device and method proposed by the present invention not only realize the data synchronization problem in the asynchronous clock data communication process, but also solve the problem of low efficiency when using the handshake mechanism when transferring data from the fast clock to the slow clock. Solved the problem of infinite buffer space when using FIFO interface. By matching different fast and slow rates and setting different channel numbers, the device of the present invention can transmit data in the fast clock domain to the slow clock domain without error, and the transmission efficiency is high.
与现有的采用FIFO来实现的技术相比,本发明方法由于没有类似于FIFO的空/满标志控制的限制,所以其控制的方式更为简单。在硬件实现时,也不会象FIFO那样受一定的工艺限制,从而进一步提高了数据传输的效率。Compared with the existing technology implemented by using FIFO, the method of the present invention has a simpler control mode because it has no restriction similar to the empty/full flag control of FIFO. When implemented in hardware, it will not be limited by a certain process like FIFO, thus further improving the efficiency of data transmission.
本发明装置的技术方案中是以61.44兆赫兹作为数据输入时钟,以50兆赫兹作为数据输出时钟这一具体应用的实施例来说明的。但显然,本专利描述的方法和装置适合于在任意慢速时钟域对任意快速时钟域传输来的数据传输。比如可以将本发明方法应用于语音等不连续业务的数据传输上。需要注意的是,本发明装置根据不同的数据输入时钟频率和数据输出时钟频率,需要改变其中的数据通道数量。In the technical scheme of the device of the present invention, the specific application example of using 61.44 MHz as the data input clock and 50 MHz as the data output clock is described. But obviously, the method and device described in this patent are suitable for data transmission from any slow clock domain to any fast clock domain. For example, the method of the present invention can be applied to data transmission of discontinuous services such as voice. It should be noted that the number of data channels in the device of the present invention needs to be changed according to different data input clock frequencies and data output clock frequencies.
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