CN101136855B - Asynchronous clock data transmission device and method - Google Patents

Abstract

The present invention discloses an asynchronous clock data transmission device and method. The device of the present invention comprises: a global clock counting unit, used to indicate the sequence number of input data in a fast source clock domain; a multi-channel distribution and control unit connected to the global clock counting unit, used to cyclically sample the input data according to the data sequence number; a synchronization control unit connected to the multi-channel distribution and control unit, used to synchronize the sampled data to the target clock domain; a word assembly unit connected to the synchronization control unit, used to assemble the data synchronized by the synchronization control unit into assembled data. The method steps of the present invention include: indicating the sequence number of input data in a fast source clock domain; cyclically sampling the input data through multiple data channels according to the data sequence number; synchronizing the sampled data to the target clock domain; assembling the synchronized data into assembled data and outputting it. The device and method of the present invention improve the transmission efficiency, and the control method is also simpler.

Description

An asynchronous clock data transmission device and method

technical field

The present invention relates to an asynchronous clock data transmission device and method, in particular to an asynchronous clock data transmission device and method when data is transmitted from a fast source clock domain to a slow target clock domain.

Background technique

In engineering design, most applications related to data transmission involve data movement across clock domains, such as commonly used disk controllers, network processors, etc. When a signal is passed from one clock domain to another, it needs to be treated as an asynchronous signal. For asynchronous signal processing, the most basic problem is to solve the stability problem of the signal. If the solution is not good, the received asynchronous signal may be in an unstable state, such as in a metastable state, and may cause this unstable state to be in a new state. Propagation spreads within the clock domain, causing functional failures in the system. Therefore, when a signal traverses between asynchronous clock domains, it usually needs to be synchronized by a synchronizer. When a single-bit signal traverses between asynchronous clock domains, common synchronizer structures include level synchronizers, edge detection synchronizers, and pulse synchronizers.

Usually, the stability problem of the asynchronous signal can be solved after being synchronized by the target clock domain synchronizer. In more applications, it is not just a simple single-bit signal that is transmitted across the clock, but a large amount of data is transmitted through the data bus, address bus, and control bus. These data signals also get stable signals after the action of the synchronizer. However, due to the uncertainty of the change time of the asynchronous signal and the relationship between the target clock edge, the received signal may not be correct. In order to solve this problem, the usual way is to adopt methods such as handshake and first-in-first-out memory (First In, First Out, referred to as FIFO) interface.

This method of handshaking is adopted, and when the data in the source clock domain is valid, an indication signal prepared according to the single-bit data is transmitted to the target clock domain. After the target clock domain detects that the indication signal is valid, it starts to receive data from the data bus, and feeds back an acknowledgment signal that the data has been received to the source clock domain. The source clock domain releases the data valid indication and the data bus when detecting that the acknowledge signal is valid. In this process, in order to solve the stability problem of the asynchronous signal, the data valid indication signal in the source clock domain is transmitted to the target clock domain, and the data receiving response signal in the target clock domain is fed back to the source clock domain. Thus, the data transmission efficiency of this communication method is greatly reduced.

When using FIFO as an interface for asynchronous clock data transmission, in addition to requiring additional FIFO storage space, there is also a problem of controlling FIFO. When the FIFO is full, no more data can be written into the FIFO. At this time, if the write operation continues, data loss will occur; similarly, when the FIFO is empty, no more data can be read from the FIFO. At this time, if the data is also read from the FIFO, the output data is incorrect. The judgment of FIFO empty and full state needs to compare the read and write addresses of FIFO. However, they are in different clock domains. For comparison, clock domain synchronization processing is required. Although there are relatively mature technologies to solve these problems, when transferring data from the fast clock domain to the slow clock domain, the speed of data writing is faster than the speed of data output on the side of the slow clock domain. When using the FIFO structure, the storage space of the FIFO must be set to be infinite, otherwise it will cause data accumulation effect and data overflow problem.

Contents of the invention

The technical problem to be solved by the present invention is to provide an asynchronous clock data transmission device and its transmission method, which is used to efficiently and simply realize synchronous transmission of data when transmitting data from a fast source clock domain to a slow target clock domain .

In order to solve the above technical problems, the present invention firstly provides an asynchronous clock data transmission device, including:

The global clock counting unit is used to indicate the sequence number of the input data from the fast source clock domain;

A multi-channel allocation and control unit, connected to the global clock counting unit, is configured with multiple data channels, and is used for each of the data channels to cyclically sample the input data according to the data sequence number;

a synchronization control unit, connected to the multi-channel allocation and control unit, for synchronizing the sampled data to the target clock domain;

A word assembly unit, connected to the synchronization control unit, is used to assemble the data synchronized by the synchronization control unit into assembly data and output it.

According to the asynchronous clock data transmission device above, each of the data channels in the multi-channel allocation and control unit can perform the sampling under the action of its own enable signal. The number of data channels of the multi-channel allocation and control unit may be determined according to the frequency of the source clock domain and the frequency of the target clock domain. Further, the number of the data channels may be further determined by using Verilog language and Verilog compiling emulator simulation.

According to the above asynchronous clock data transmission device, the synchronization of the synchronization control unit may adopt a double handshake communication mechanism.

According to the above-mentioned asynchronous clock data transmission device, wherein the word assembly unit can be further configured to generate a flag signal that the assembly of the assembly data is completed after the assembly of each assembly data is completed, which is used to indicate the The assembly data described above is assembled. When the word assembling unit performs the assembling, the number of the assembled data assembled from the synchronized data may be determined according to the source clock domain frequency and the target clock domain frequency.

According to the asynchronous clock data transmission device above, it further includes a digital signal processor interface unit connected to the word assembly unit to provide a data output interface for the device.

On this basis, the present invention further provides an asynchronous clock data transmission method, comprising steps:

(1) Indicates the sequence number of the input data originating from the fast source clock domain;

(2) cyclically sampling the input data through multiple data channels according to the data serial number;

(3) synchronizing the sampled data to the target clock domain;

(4) Assemble the synchronized data into assembled data and output it.

According to the asynchronous clock data transmission method above, in the step (2), the sampling can be performed under the control of respective enable signals of the data channels. The number of data channels may be determined according to the frequency of the source clock domain and the frequency of the target clock domain. Further, the number of the data channels may be further determined by using Verilog language and Verilog compiling emulator simulation.

According to the above asynchronous clock data transmission method, wherein in the step (3), the synchronization may adopt a double handshake communication mechanism.

According to the above-mentioned asynchronous clock data transmission method, wherein, in the step (4), the number of the assembled data assembled into the synchronized data can be determined according to the frequency of the source clock domain and the target The clock domain frequency is determined. After the assembly of each of the synchronized assembled data is completed, a flag signal indicating that the assembled data is assembled may be further generated to indicate that the assembled data has been assembled.

According to the above-mentioned asynchronous clock data transmission method, it may further include steps:

(5) The assembly data is output to a data output interface for external calling of the assembly data.

An asynchronous clock data transmission device and method provided by the present invention, compared with the existing technology, has the following characteristics:

1) Improved transmission efficiency;

2) Saved equipment cost;

3) The control method is simpler.

Description of drawings

Fig. 1 is a conceptual schematic diagram of the device and method of the present invention;

Fig. 2 is a schematic structural view of a device embodiment of the present invention;

Fig. 3 is a schematic diagram of the interrelationship of the multi-channel control of the device application embodiment of the present invention;

Fig. 4 is a schematic flow chart of a method embodiment of the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

Referring to FIG. 1 , the idea of the present invention is: the data sequence D1 in the source target domain, that is, the fast clock domain, is input to a corresponding asynchronous clock data transmission circuit after being counted by a counter. The transmission circuit assembles the data in the source and target domains according to the serial number given by the counter, for example, assembles the first data and the second data into one data, and assembles the third data and the third data into one data , and so on. Of course, other assembly methods can also be used according to specific requirements. The transmission circuit sends the assembled data sequence D2 to the relevant data processing unit in the target clock domain, that is, the slow clock domain, through a CPU interface of a Digital Signal Processor (DSP for short). The asynchronous clock data transmission device implemented based on this idea assembles the data sequence D1 into the data sequence D2, which can not only improve the efficiency of data transmission, but also avoid the problem of data overflow.

As shown in Figure 2, the asynchronous clock data transmission device of the present invention mainly includes a global clock counting unit 201, a multi-channel distribution and control unit 202, a synchronization control unit 203, a word assembly unit 204, and a DSP interface unit 205, wherein:

The global clock counting unit 201 is equivalent to a global clock counter, and is used to indicate the serial number of the input data from the fast clock domain, that is, the source clock domain. The data generated by the global clock counting unit 201 is sent to the multi-channel distribution and control unit 202 .

The multi-channel allocation and control unit 202 is connected to the global clock counting unit 201 and is configured with multiple data channels. Each channel, under the action of its own enable signal, performs continuous looping on the basis of the data serial number output by the global clock counting unit 201. The output of the global clock counting unit 201 performs data sampling. At the same time, only one enable signal is active. These channels form a channel loop under the coordinated control of the multi-channel allocation and control unit 202 and the synchronization control unit 203 . This channel loopback samples data output from the fast clock domain in a continuous loop. Each channel in the multi-channel allocation and control unit 202 samples the data of its corresponding fast clock domain and sends it to the synchronization control unit 203 .

The number of data channels in the multi-channel allocation and control unit 202 is based on the source clock domain, that is, the fast clock frequency, and the target clock domain, that is, the slow clock frequency. The hardware of the conversion channel is described in Verilog language, and the number of predefined channels is After a certain value M, the value of the predefined number of channels M is determined through Verilog Compiled Simulator (VCS for short) simulation.

The synchronization control unit 203 is connected to the multi-channel distribution and control unit 202, and is used for synchronizing the sampling data of the fast clock domain sampled by each channel of the multi-channel distribution and control unit 202 to the target clock domain respectively. The synchronization process uses a double-handshake communication mechanism to ensure that the data sampled by the clock in the target clock domain is safe and reliable, and eliminate metastable states. The synchronization control unit 203 sends the synchronized data to the word assembly unit 204 for data assembly.

The word assembly unit 204 is connected to the synchronization control unit 203 and is used to assemble the data synchronized by the synchronization control unit 203 into assembly data. The assembly principle of assembled data needs to satisfy the following expression:

f ₁ ×n≥f ₂ <f ₁ ×(n+1) (1)

Wherein, f ₁ is the clock frequency of the slow clock, n is the number of channels that need to assemble multi-channel distribution and channel data in the control unit 202, and f ₂ is the clock frequency of the fast clock. That is, the slow clock frequency f ₁ multiplied by the number n of channels to be assembled together should be greater than or equal to the fast clock frequency f ₂ . The reason for this is to perform data sampling in the slow clock domain after the data of several adjacent channels are assembled. In this way, the data in the source clock domain will not be lost, so that the data transmission is accurate.

Assuming that the total number of channels in the allocation and control unit 202 is M, and the number of assembled words determined according to the expression (1) is n, the word assembly unit 204 needs to follow certain assembly principles when performing data assembly. If M is just divisible by n, then the M channel data is just assembled into M/n assembled data; if M is not divisible by n, then the M channel data needs to be assembled into [M/n]+1 assembled data, where [M/n] is the integer part of M/n. The assembly method is to assemble the first [M/n]*n data in M data in sequence, and assemble them into [M/n] assembled data. For the remaining part, that is, the data in M-[M/n]*n channels, assemble it into an assembled data; for the last assembled data, if the number of digits is insufficient, you can set its high or low position as having Data with a specific meaning, such as setting to all zeros, or setting to other symbolic data, etc.

After the assembly of one assembled data is completed, the word assembly unit 204 also correspondingly generates a data assembly completed flag signal, indicating that each assembled data has been assembled. The word assembly unit 204 sends the assembled assembly data to the DSP interface unit 205 for output.

The DSP interface unit 205 is connected with the word assembly unit 204, and provides a data output interface for the data transmission device of the present invention, so as to facilitate other data processing units in the system to obtain data. The assembled data assembled by the word assembly unit 204 is transmitted to other data processing units of the system through the DSP interface unit 205 . Before the DSP interface unit 205 transmits the assembled assembled data to other data processing units, it also needs to receive a flag signal of completion of data assembly sent by the word assembled unit 204 . That is to say, after the data assembly is completed, the word assembly unit 204 also sends the flag signal that the generated data assembly is complete to the DSP interface unit 205, and the DSP interface unit 205 transmits the assembled data to other data after receiving the flag signal. processing unit.

According to the assembling principle and method provided by the device of the present invention, the assembled data does not need to be further processed, and the data sequence output from the DSP interface unit 205 is exactly the same as the data input sequence of the fast clock domain.

The following uses 61.44 MHz as the data input clock and 50 MHz as the data output clock as an application example to further describe the device of the present invention in detail. That is, the operating frequency of the source clock domain is 61.44 MHz, and the operating frequency of the target clock domain is 50 MHz. The device of the present invention further assumes that the data width input by the 61.44 MHz clock domain is 32 bits.

The global clock counting unit 201 is equivalent to a global clock counter that generates a 32-bit wide signal. A 32bits data is generated at each clock, and in this embodiment, the 32bits data is defined as: bit0～bit4 is the sampling count value, bit5～bit16 is the chip count value, bit17～bit20 is the time slot count value, bit21 ~bit31 is the frame count value. According to specific applications, it can also be defined as other meanings. The input data is 32bits data that is output cycle by cycle. It changes on the rising edge of the 61.44 MHz clock, and the data is also sampled on the rising edge of the 61.44 MHz clock. The 32bits counting unit is composed of four sub-counters, among which, bit0~bit4 are sampling counting values, bit5~bit16 are chip counting values, bit17~bit20 are time slot counting values, and bit21~bit31 are frame counting values. In this embodiment, the input data may be a 32bits random number output cycle by cycle. Of course, it is also possible to test the count value itself as input data.

The multiple data channels configured by the multi-channel allocation and control unit 202 form a channel loop under the coordinated control of the synchronization control unit 203 . Each channel in the channel loopback continuously samples the data generated by the 61.44 MHz clock output by the global clock counting unit 201 under the action of its respective enable signal. At the same time, only one enable signal is active. In this embodiment, the clock data of 61.44 MHz in the source clock domain is transmitted by using the clock of 50 MHz in the target clock domain, requiring eleven channels. Each channel has correspondingly a sampling data and an enable signal of the sampling data. When the enable signal of each channel falls, the corresponding channel performs data sampling. These eleven channels form a loop under the coordinated control of the multi-channel allocation and control unit 202 and the synchronization control unit 203, so that the 32bits random numbers generated by the 61.44 MHz clock in the source clock domain can be sampled continuously.

In this application example, the eleven channels of the multi-channel distribution and control unit 202 are based on the fast clock frequency of 61.44 MHz and the slow clock frequency of 50 MHz, using Verilog language to describe the hardware of the conversion channel, and through VCS simulation to be sure.

When these eleven channels store the input data of 61.44MHz, the following method is adopted: the first channel samples the first 32bit data of the effective continuous input random data, and the second channel samples the first 32bit data of the continuous input random data Two 32bit data, and so on, the eleventh 32bit data of the random data continuously input by the eleventh channel. The data sampling enable control signals of adjacent channels differ by one clock cycle, and the relationship between the channels is shown in Figure 3.

clk_61.44 in Figure 3 indicates the clock frequency of the source clock domain, and gcc2[31:0] indicates the serial number of the data that needs to be transmitted from the source clock domain to the target clock domain; and ch1_data[31:0], ch2_data[31: 0], ..., ch11_data[31:0] are the sampling data of the eleven channels respectively, and ch1_en, ch2_en, ..., ch11_en are the sampling data enable signals of the eleven channels respectively.

The synchronization control unit 203 adopts a double-handshake communication mechanism in the process of synchronizing the data in the 61.44 MHz clock domain sampled by each channel to the 50 MHz clock domain respectively.

In this application example of the present invention, since the frequency of the source clock domain is 61.44 MHz and the frequency of the target clock domain is 50 MHz, according to the expression (1), it can be concluded that n is 2, that is, the word assembly unit 204 The data synchronized by the synchronization control unit 203 needs to be assembled into double word data. According to the above assembly principle, it can be known that the data of the first channel and the second channel are assembled into a double-word data, the data of the third channel and the fourth channel are assembled into a double-word data, and so on, Until the data of the last channel is assembled in one cycle. For the specific assembly method, you can choose to put the data of the first channel in the low position, and the data in the second channel in the high position; The data of the channel is placed in the low order. Of course, there are many ways to assemble two data into one data, which are not listed here. However, the preferred method of placing the data of the first channel in the low position and the data of the second channel in the high position proposed by the device of the present invention is an optimal common method.

In this application embodiment, the channel loop formed by the multi-channel allocation and control unit 202 includes eleven channels, that is, the number of channels is an odd number. In loop control, the data sampled by the last channel among the eleven channels, that is, the eleventh channel, may be the same as the data of the first channel in the next clock cycle of the source clock domain, or may be different and the two cases should be treated separately. If the eleventh channel and the first channel sample the data of the same serial number in the source clock domain, the data of this channel will not be output, that is, the data of the last channel will be discarded, and the next cycle will be entered; if this If the last channel and the first channel sample data of the same serial number that is not in the source clock domain, assemble the data of the channel with other data of the same bit width and specific meaning into a double-word data. Data with specific meanings include all zeros or designated symbolic data, for example. The low 32bit sets the data of the channel, and the high 32bit is correspondingly set to the data with specific meaning.

When the number of channels is even, the data of every two channels is assembled into a double word data. For the specific assembly method, refer to the above description of the case where the number of channels is odd. After the word assembly unit 204 assembles the data in the channel into double word data, it also correspondingly generates a flag signal indicating that the data assembly is complete.

It can be seen from FIG. 3 that the data sampled by the eleventh channel is the same as the data sampled by the first channel in the next clock cycle. Therefore, when double word assembly is performed, the data sampled by the eleventh channel is discarded, and the data of the first channel and the second channel in the next cycle are directly assembled.

The double-word data assembled by the word assembly unit 204 is transmitted to other data processing units of the system through the DSP interface unit 205 .

On the basis of the above inventive system, the present invention further provides an asynchronous clock data transmission method for efficiently and simply realizing synchronous data transmission when transmitting data from a fast source clock domain to a slow target clock domain. Referring to Fig. 4, the inventive method mainly comprises the following steps:

Step 401: Firstly, the global clock counting unit 201 counts the data sequence of the fast clock domain as the source clock domain, and indicates the sequence number of the input data originating from the source clock domain. The global clock counting unit 201 transmits the counted data to the multi-channel distribution and control unit 202 .

Step 402: The multi-channel allocation and control unit 202 is configured with multiple data channels. According to the input data sequence number output by the global clock counting unit 201, under the coordinated control of the multi-channel distribution and control unit 202 and the synchronization control unit 203, all data channels are input from the source clock domain according to their respective enabling signals. The data is sampled continuously and cyclically.

Step 403: The synchronization control unit 203 synchronizes the data in the source clock domain sampled by each channel of the multi-channel allocation and control unit 202 to the target clock domain respectively. The synchronization process uses a double-handshake communication mechanism to ensure that the data sampled by the target clock is safe and reliable, and to eliminate metastable states.

Step 404: The word assembly unit 204 performs data assembly on the data synchronized by the synchronization control unit 203, and generates a data assembly completion flag signal accordingly after each assembly data assembly is completed. When data assembly is performed, the assembly principle to be followed is as described above, assuming that the total number of channels in the distribution and control unit 202 is M, and the number of assembly words determined according to the expression (1) is n, if M is just divisible by n, then M channel data is just assembled into M/n assembled data; if M is not divisible by n, M channel data needs to be assembled into [M/n]+1 assembled data, where [M/n] is M/ For the integer part of n, the assembly method is to assemble the first [M/n]*n data in M data in sequence, and assemble them into [M/n] assembled data, and for the remaining part, that is, M- The data in [M/n]*n channels is assembled into an assembled data; for the last assembled data, if the number of digits is insufficient, you can set its high or low position as data with specific meaning, such as setting it as full Zero, or set to other iconic data, etc.

Step 405: The assembled data assembled by the word assembly unit 204 is transmitted to other data processing units of the system through the DSP interface unit 205. That is, other data processing units of the system call the assembly data through the data output interface of the DSP interface unit 205 . Before the DSP interface unit 205 transmits the assembled data to other data processing units, it also needs to receive the data assembly completion flag signal sent by the word assembly unit 204 . After receiving the flag signal, the DSP interface unit 205 transmits the assembly data to other data processing units.

The data transmission device and method proposed by the present invention not only realize the data synchronization problem in the asynchronous clock data communication process, but also solve the problem of low efficiency when using the handshake mechanism when transferring data from the fast clock to the slow clock. Solved the problem of infinite buffer space when using FIFO interface. By matching different fast and slow rates and setting different channel numbers, the device of the present invention can transmit data in the fast clock domain to the slow clock domain without error, and the transmission efficiency is high.

Compared with the existing technology implemented by using FIFO, the method of the present invention has a simpler control mode because it has no restriction similar to the empty/full flag control of FIFO. When implemented in hardware, it will not be limited by a certain process like FIFO, thus further improving the efficiency of data transmission.

In the technical scheme of the device of the present invention, the specific application example of using 61.44 MHz as the data input clock and 50 MHz as the data output clock is described. But obviously, the method and device described in this patent are suitable for data transmission from any slow clock domain to any fast clock domain. For example, the method of the present invention can be applied to data transmission of discontinuous services such as voice. It should be noted that the number of data channels in the device of the present invention needs to be changed according to different data input clock frequencies and data output clock frequencies.

Claims (14)

1. asynchronous clock data transmission device comprises:

Global clock counting unit is used to indicate the sequence number of the input data that derive from the fast source clock zone;

Multichannel distributes and control unit, links to each other with said global clock counting unit, disposes a plurality of data channel, is used for according to said data sequence number, circularly to said sampling input data;

Synchronous control unit links to each other with control unit with said multichannel distribution, is used for the said data sync that samples is arrived target clock territory at a slow speed;

The word module units links to each other with said synchronous control unit, is used for the data set of said synchronous control unit after synchronously dressed up assembling data and output.

2. device as claimed in claim 1 is characterized in that, each data channel in said multichannel distribution and the control unit is carried out said sampling under enable signal effect separately.

3. device as claimed in claim 1 is characterized in that, said multichannel distributes the data channel number with control unit, confirms through emulation according to the frequency of said source clock zone and the frequency in said target clock at a slow speed territory.

4. device as claimed in claim 1 is characterized in that, said synchronous control unit synchronously, adopt two carrying out shake communication mechanism.

5. device as claimed in claim 1 is characterized in that, said word module units is further used for after said each assembling data assembling is accomplished, all generating the marking signal that said assembling data assembling is accomplished, and is used to indicate said assembling data assembling to accomplish.

6. device as claimed in claim 1; It is characterized in that; Said word module units is when carrying out said assembling, and said data set after is synchronously dressed up the number of said assembling data, confirms according to said source clock zone frequency and said target clock at a slow speed territory frequency.

7. device as claimed in claim 1 is characterized in that, further comprises the digital signal processor interface unit, links to each other with said word module units, for said device provides data output interface.

8. asynchronous clock data transmission method comprises step:

(1) indication derives from the sequence number of the input data of fast source clock zone;

(2) according to said data sequence number, through a plurality of data channel circularly to said sampling input data;

(3) the said data sync that samples is arrived target clock territory at a slow speed;

(4) said data set after is synchronously dressed up assembling data and output.

9. method as claimed in claim 8 is characterized in that, in the said step (2), said sampling is carried out under the enable signal control separately of said a plurality of data channel.

10. method as claimed in claim 8 is characterized in that, in the said step (2), said data channel number is confirmed through emulation according to the frequency of said source clock zone and the frequency in said target clock at a slow speed territory.

11. method as claimed in claim 8 is characterized in that, and is said synchronous in the said step (3), adopts two carrying out shake communication mechanism.

12. method as claimed in claim 8 is characterized in that, in the said step (4), said data set after is synchronously dressed up the number of said assembling data, confirms according to said source clock zone frequency and said target clock at a slow speed territory frequency.

13. method as claimed in claim 8 is characterized in that, in the said step (4), after said each assembling data assembling after is synchronously accomplished, further generates the marking signal that the data assembling is accomplished, and indicates said assembling data assembling to accomplish.

14. method as claimed in claim 8 is characterized in that, further comprises step:

(5) said assembling data output to a data output interface and supply the said assembling data of external call.

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