JP2006072968A - Memory module, memory unit, and hub with non-periodic clock, and method using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory module, a memory unit, and a hub having a non-periodic clock, and a method using the same. <P>SOLUTION: The memory module 20, as shown in Fig. 2, may include a phase-locked loop PPL receiving input of an external periodic clock ECLK1 and generating at least one internal periodic clock (for example, DCLK1, DCLK2, or RCLK), and a plurality of memory units M1-Mn receiving input of the internal periodic clocks DCLK1, DCLK2 and RCLK, or a non-periodic clock ECLK2 from the outside. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  One exemplary embodiment of the present invention relates to a memory component, such as a memory module, a memory unit, and / or a hub, that provides or provides one or more periodic clocks and one or more non-periodic clocks.

  One exemplary embodiment of the present invention relates to a memory component including a memory register or a memory interface register, eg, a memory module or memory unit.

  One preferred embodiment of the present invention relates to a memory component such as a memory module, a memory unit, and / or a hub in which one or more periodic clocks or one or more non-periodic clocks are selected based on a mode signal.

  According to a preferred embodiment of the present invention, one or more periodic clocks or one or more non-periodic clocks are selected and used in a plurality of memory units or memory devices, and the other one of the periodic clocks or the non-periodic clocks is used. It relates to memory components, eg memory modules, memory units and / or hubs, which are used for selected memory registers or memory interface registers.

  One preferred embodiment of the present invention relates to a memory component such as a memory module, a memory unit and / or a hub in which one or more periodic clocks or one or more non-periodic clocks are selected based on one or more mode signals. .

  One preferred embodiment of the invention relates to a memory component that implements the clock selection and includes a clock selection circuit that is part of a memory module, memory unit and / or hub.

  FIG. 1 illustrates a conventional memory module including a phase locked loop PPL, a register, and a plurality of memory devices M1-Mn.

  The phase locked loop receives a reference clock ECLK from an external device, for example, a memory controller, and generates a plurality of clocks (for example, DCLK1, DCLK2, and RCLK) having the same phase as the reference clock. In the memory module of the prior art, the reference clock has a constant period.

  The register receives the control signal CON, for example / CS, / RAS, / CAS, / WE and / or other similar control signals and the address signal ADDR from an external device, and the clock (for example, the RCKL clock) is phase-locked. It can be input from a loop. The register can output the control signal RCON and / or the address signal ADDR to a plurality of memory devices that can be synchronized with the clock RCKL.

  The plurality of memory devices may receive one or more data DQ, data mask DM, and / or data strobe DQS signal from an external device such as a memory controller. The plurality of memory devices can also receive at least one clock signal (eg, DCLK1, DCLK2), RCON and / or ADDR, and can generate an internal signal synchronized with the clock signal DCLK1 or the clock signal DCLK2. .

  The conventional memory module shown in FIG. 1 cannot receive a non-periodic clock and cannot operate in response to the non-periodic clock. In particular, when an aperiodic clock is supplied to the phase locked loop, the phase locked time is required every time the period of the aperiodic clock is changed in the fixed loop. In general, it takes several tens of microseconds (μsec) to fix the phase. However, when the control signal CON or the address signal APPR is supplied from an external device such as a memory controller to operate one of the plurality of memory devices during the phase fixing period, the plurality of memory devices M1-Mn Cannot properly receive the control signal CON or the address signal.

Since the plurality of memory devices in the module operate in response to the periodic clock signal DCLK1 or DCLK2, the setup time ts and the hold time th of the control signal CON or the address signal ADDR can be easily controlled by the user. Can not.
U.S. Pat. No. 6,738,880 US Pat. No. 6,742,098 US Publication No. 2003-221044

  An object of the present invention for solving the above-described problems is to provide a memory module for selectively providing a periodic clock and an aperiodic clock.

  Another object of the present invention is to provide a hub for selecting a periodic clock and an aperiodic clock to use as an internal clock.

  Still another object of the present invention is to provide a memory unit for selecting a periodic clock and an aperiodic clock and using them as an internal clock.

  Still another object of the present invention is to provide a clock providing method of a memory module for selecting a periodic clock and an aperiodic clock and providing them to an internal clock.

  Still another object of the present invention is to provide a memory unit clock generation method for selecting a periodic clock and an aperiodic clock and providing them to an internal clock.

  One preferred embodiment of the present invention relates to an aperiodic clock used for memory applications.

  A preferred embodiment of the present invention relates to a memory module, a memory unit, a hub, and a method using them.

  One preferred embodiment of the present invention relates to a method for generating and / or providing an aperiodic clock for use in memory applications.

  According to a preferred embodiment of the present invention, a phase-locked loop that receives an external periodic clock and generates one or more internal periodic clocks, and a plurality of internal periodic clocks or an external input of a first non-periodic clock. The present invention relates to a memory module including a memory unit.

  A preferred embodiment of the present invention is a phase locked loop for receiving at least one external periodic clock and generating at least one internal periodic clock, and a setting for generating at least one control signal by receiving a mode setting signal. A register, receiving a memory information, a memory interface register for providing the memory information to a plurality of memory units, a first aperiodic clock, the internal periodic clock, receiving the one or more control signals; The present invention relates to a hub of a memory module including a clock selection circuit that provides the internal periodic clock or the first non-periodic clock to the plurality of memory units and the memory interface register in response to the one or more control signals.

  According to a preferred embodiment of the present invention, a mode setting circuit that receives an input of an input signal and outputs a mode signal, and an input of a periodic clock and an aperiodic clock, and the periodic clock or The present invention relates to a memory unit including a clock selection circuit that outputs the non-periodic clock.

  A preferred embodiment of the present invention includes a first input pin that receives a periodic clock in a normal operation mode, a second input pin that receives an aperiodic clock in a test operation mode, and inputs of the periodic clock and the aperiodic clock. And a clock selection circuit that outputs the periodic clock or the aperiodic clock in response to a mode selection signal, and an input of the periodic clock or the aperiodic clock from the clock selection circuit to output an internal clock The present invention relates to a memory unit including a clock buffer.

  According to a preferred embodiment of the present invention, as a method for providing a clock to a memory module having a phase locked loop and a plurality of memory units, providing a periodic clock to the phase locked loop in a normal operation mode, and a test The present invention relates to a clock providing method including providing an aperiodic clock directly to the plurality of memory units in an operation mode.

  According to a preferred embodiment of the present invention, as a method of providing a clock to a plurality of memory units of a memory module having a hub, receiving an external periodic clock and generating an internal periodic clock, receiving a mode setting signal Generating control signals, receiving control information and address information and providing the control information and address information to a plurality of memory units; and inputting non-peripheral clocks, internal cycle clocks and control signals. In response, the present invention relates to a clock providing method including providing the internal periodic clock or the non-periodic clock to the plurality of memory units and the memory interface register in response to the control signal.

  A preferred embodiment of the present invention includes receiving an input signal and outputting a mode setting signal, receiving a periodic clock and an aperiodic clock, and responding to the mode setting signal with the periodic clock or A method for generating an internal clock of a memory unit, comprising: selecting the non-periodic clock and outputting the selected clock to a clock buffer; and generating an internal clock in the clock buffer in response to the selected clock. .

  According to the present invention, it is possible to provide a memory module for selectively providing a periodic clock and an aperiodic clock.

  Hereinafter, a preferred embodiment of the present invention will be described in more detail with reference to the drawings.

  FIG. 2 illustrates a memory module according to a preferred embodiment of the present invention.

  As shown in FIG. 2, when a plurality of memory devices (memory units) M1-Mn operate using the periodic clock ECLK1, the data strobe DQS or the data mask DM pin of each memory device is a tab of the memory module 20. A data strobe signal or a data mask signal can be received from the tab. However, when a plurality of memory devices operate using the non-periodic clock ECLK2, a plurality of non-periodic clocks are stored in the memory module 20 through the data strobe DQS, the data mask DM, or the non-connected NC pin connected to the tab. Can be provided to the device. A non-periodic clock such as ECLK2 is defined as a clock having an irregular period or irregular duty cycle.

  FIG. 3 shows a memory device according to a preferred embodiment of the present invention of FIG. As shown in FIG. 2, the memory device Mn includes a plurality of CON buffers for buffering control signals, ADDR buffers for buffering address signals, and / or DQ buffers for buffering data signals. Input buffers.

  The memory device may include a first pin for receiving a constant periodic clock such as DCLK1 and a second pin for receiving an aperiodic clock such as ECLK2 or the data strobe signal DQS from the data strobe buffer. it can. The memory device may include a mode setting circuit for outputting a mode setting signal MSS according to a mode register setting (MRS) signal.

  For example, when the mode register setting signal indicates the test mode, an aperiodic clock signal such as ECLK2 can be input through the second pin. In another case, the data strobe signal DQS may be input from the data strobe buffer through the second pin.

  A clock selection circuit in which the memory device Mn receives a periodic clock such as DCLK1 and an aperiodic clock such as ECLK2, selects one clock based on the MSS signal, and outputs one clock to the clock buffer CLK. Can further be included.

  For example, when the MSS signal is in a logic 'high' state, the clock selection circuit supplies the clock DCLK1 to the CLK buffer, and the data strobe signal is supplied to the data strobe buffer. The data strobe signal is not provided to the data strobe buffer.

  The CLK buffer receives an input of the clock selected by the clock selection circuit, and outputs an internal clock to, for example, a CON buffer, an address buffer, and / or a DQ buffer. The CON buffer, ADDR buffer, and DQ buffer receive input signals such as RCON, RADDR, and DQ, respectively, and output ICON, IADDR, and IDATA synchronized with the internal clock.

  In one embodiment, the second pin that receives an aperiodic clock signal in a test mode may be a data mask pin DM or an unconnected NC pin.

  FIG. 4 shows a memory module according to another preferred embodiment of the present invention. As shown in FIG. 4, the memory module 40 includes a phase locked loop and a plurality of memory devices as shown in FIG. 3, but does not include a register. Therefore, in the embodiment of FIG. 4, the control signal CON and the address signal ADDR can be directly supplied to a plurality of memory devices.

  FIG. 5 shows a memory module according to another preferred embodiment of the present invention.

  As shown in FIG. 5, the memory module 50 may include a phase locked loop, a register, and a plurality of memory devices as shown in FIG. The memory module 50 of FIG. 5 also includes a clock selection circuit comprising a first switch that receives the periodic clock DCLK1 from, for example, a phase locked loop, and a second switch that receives an aperiodic clock from an external device such as a memory controller, for example. Can be included.

  The clock selection circuit can select one clock in response to the mode selection signal N / T and output the selected clock to a plurality of memory devices. In one embodiment, the mode selection signal may be supplied from an external device. In one embodiment, when the mode selection signal has a logic value of logic 'low' or '0', the normal operation mode is selected, the periodic clock DCLK1 or DCLK2 is supplied to the plurality of memory devices, and the mode selection signal is If the logic value is logic 'high' or '1', the non-periodic operation mode is selected and the non-periodic clock ECCLK2 is supplied to the plurality of memory devices M1-Mn.

  As shown in FIG. 2, each of the plurality of memory devices includes the clock selection circuit shown in FIG. Conversely, the clock selection circuit of FIG. 5 is part of the memory module 50 and not part of each memory device. Thus, the embodiment of FIG. 5 requires less hardware, i.e., a conventional memory that requires only one clock selection circuit instead of n clock selection circuits as in FIG. Used up to the device.

  FIG. 6 shows a memory module according to still another embodiment of the present invention. As shown in FIG. 6, the memory module 60 may include a phase locked loop, a register, a clock selection circuit, and a plurality of memory devices.

  As shown in FIG. 6, in a preferred embodiment of the present invention, the clock selection circuit includes a first switch that receives the periodic clock DCLK1 from the phase locked loop and a second switch that receives the aperiodic clock from the external device. Can be included. The clock selection circuit can select one clock in response to a plurality of mode selection signals N / Tn, for example, N / T1 and N / T2. In one embodiment, the mode selection signal N / T1 and the mode selection signal N / T2 can be supplied from an external device.

  Table 1 shows possible combinations of N / T1 and N / T2 signal values that allow a register and / or multiple memory devices to be independently controlled by an aperiodic clock or a periodic clock. .

FIG. 7 shows a memory module according to still another embodiment of the present invention. As shown in FIG. 7, the memory module 70 is the same as the memory module 60 of FIG. 6 except that a plurality of non-periodic clocks ECLK2 and ECLK3 are supplied to the memory module 70. In the preferred embodiment of the present invention shown in FIG. 7, the non-periodic clocks ELCK2 and ELCK3 can be input to a plurality of memory devices and / or registers in response to the mode selection signals N / T1 and N / T2.
FIG. 8 illustrates a memory system according to a preferred embodiment of the present invention. As shown in FIG. 8, the memory system 100 may include a memory controller 600, a clock source 610, and a plurality of memory modules 500. Each memory module 500 may further include a plurality of memories, eg, a DRAM 520 and one or more hubs 510.
The memory controller 600 can receive the soundbound packet 14 including data, control and / or address information, or can transmit the southbound packet 10 including address information to the plurality of memory modules 500 in the downstream direction. The northbound packet 14 including data in the upstream direction can be received from the plurality of memory modules 500. The memory controller 600 can also communicate with a plurality of memory modules 500 through SMBUS. The clock source 610 can supply a periodic clock and / or an aperiodic clock such as ELCK 1 and ECLK 2 to the memory controller 600 and / or the plurality of memory modules 500.

  In the preferred embodiment of the present invention shown in FIG. 8, the plurality of memory modules 500 may be single in-line memory modules (SIMMs) or double in-line memory modules (DIMMs). In another embodiment, the DIMM may be a registered DIMM (RDIMM) or a fully buffered DIMM (FBDIMM).

  Further, in the preferred embodiment of the present invention shown in FIG. 8, the plurality of memory modules 500 can be connected to the memory controller 600 in a daisy chain manner. In the embodiment shown in FIG. 8, the memory system can include eight memory modules 500 (or eight FBDIMMs).

  FIG. 9 shows an example of the hub 510 of FIG. 8 in more detail.

  As shown in FIG. 9, each hub 510 may include a pair of receivers and transmitters 502, 504, and the pair of receivers and transmitters 502, 504 receive PSB information packets from the memory controller 600 of FIG. 8, a receiver RX 2 that receives a PNB information packet from another memory module 500, a transmitter TX 1 that transmits an SSB information packet to the other memory module 500, and an SNB information packet to the memory controller 600 of FIG. A transmitter TX2 for transmission may be included.

  The hub 510 also serializes information including data such as RDATA and provides it to the receiver and transmitter 502, 504, data including WDATA from the receiver and transmitter 502, 504, A controller 516 including a deserializer may be included that receives input of command information such as CMD.

  The controller also converts received information packets such as / CS, / RAS, / CAS, / WE or similar signals, control signals such as address signals and / or data signals into memory information MIF, and encodes them into memory information MIF. And output to the memory interface register 514.

  Hub 510 also includes a phase locked loop 506, such as any of the phase locked loops shown in FIGS. 2, 4-7, and receives a reference clock such as CLK or ELCK1, and the frequency of the reference clock CLK or ECLK1. It is possible to generate an RCKL or DCLK clock having the same phase and a frequency that is a predetermined multiple of.

  The hub 510 receives a mode setting signal from the memory controller 610 via SMBUS, for example, and selects control signals, eg, MSS and MSS2, as clock selection circuits such as any of the clock selection circuits shown in FIG. 3 or FIGS. A setting register 508 that outputs to the circuit 512 can be included. The clock selection circuit 512 receives a fixed period clock, for example, RCLK and DCLK from the phase locked loop, receives an aperiodic clock such as ECLK2, and receives control signals MSS1 and MSS2 output from the setting register 508. One or more clocks can be selected in response to. The clock selection circuit 512 can also output the selected clock as HICLK1 and HICLK2 to the memory interface 514 and / or a plurality of memory devices 520, for example, a dual data rate DRAM (DDR-DRAM).

  In one embodiment, the clock RCKL may be supplied to the memory interface register 514 as HICLK1 during normal operation. Further, the clock DCLK can be supplied to the plurality of memory devices 520 as HILCK2. In another embodiment, the ECLK2 clock may be supplied to the memory interface register as HICLK1 and supplied to the plurality of memory devices 520 as HICLK2 during the test operation.

  The memory interface register 514 can output the memory information to the plurality of memory devices 520 in synchronization with the selected clock HICLK1. The memory information may include data transmitted / received from / to the plurality of memory devices 520, command information, and / or address information. The memory device 520 can receive the memory information in synchronization with the HICLK2 and operate in response to the supplied memory information.

  FIG. 10 illustrates one embodiment of a clock selection circuit, such as the clock selection circuit 512 of FIG.

  As shown in FIG. 10, the clock selection circuit 512 interfaces with the phase locked loop, such as the phase locked loop 506 of FIG. 9, the memory interface register 514 of FIG. 9, and the plurality of memory devices 520 of FIG. can do.

  As shown in FIG. 10, the control signals MSSI and MSS2 can be supplied externally, for example, from a setting register such as the setting register 508 of FIG.

  The clock selection circuit 512 may further include two switches 1002 and 1004 in response to the control signals MISS1 and MISS2, respectively.

  Table 2 shows an example of the operation of the clock selection circuit 512 of FIG.

  The first case is a case where the memory interface register 14 and the plurality of memory devices 520 operate in response to a periodic clock as a case of normal operation.

  In the second case, the memory interface register 514 operates in response to a periodic clock, and the plurality of memory devices 520 operate in response to an aperiodic clock. The setup time and hold time of the input signal for the plurality of memory devices 520 can be adjusted by supplying an aperiodic clock.

  In the third case, the memory interface register 514 operates in response to an aperiodic clock, and the plurality of memory devices 520 operate in response to a periodic clock. As in the second case, the setup time and hold time can be controlled by supplying an aperiodic clock to the memory interface register 514. In the fourth case, a non-ambient clock is supplied to the memory interface register 514 and the plurality of memory devices 520 so that the setup time and hold time can be controlled similarly.

FIG. 11 illustrates another embodiment of a clock selection circuit 612, such as the clock selection circuit 512 of FIG. In the clock selection circuit 612 of FIG. 11, the second aperiodic clock ECLK3 is input to the clock selection circuit 612 in response to MSS1, and the aperiodic clocks ELCK2 and ELCK3 are respectively in response to MSS1 and MSS2 and a plurality of memory interface registers S14. 10 is different from the clock selection circuit 512 of FIG. 10 in that it can be input to the memory device 520 of FIG.
FIG. 12 shows yet another embodiment of a clock selection circuit 712, such as the clock selection circuit 512 of FIG. In the embodiment of FIG. 12, R-delay 1 is provided between the switch 1002 and the memory interface register 514, and D-delay 2 is provided between the switch 1004 and the plurality of memory devices 520. The delay time provided by R-delay 1 and D-delay 2 can be adjusted using one or more control signals.

As described above, according to a preferred embodiment of the present invention, a memory module having such an aperiodic clock option performs various operations including failure analysis of the memory and the memory module from the standpoint of a user and a developer. It can be implemented. That is, the application area of the memory and the memory module is widened.
Further, since it is not necessary to wait for the phase locking time in the test mode, the test time of the memory module can be shortened and the test efficiency can be improved.

  Although a preferred embodiment of the present invention has been described with reference to the accompanying drawings, each of the various features of the preferred embodiments of the present invention can be combined with any of the features and methods of the other embodiments.

  Although embodiments of the present invention have been described with reference to a particular number of circuits and signals, any number of circuits and signals can be used.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to these embodiments, and those skilled in the art can modify or change the present invention without departing from the spirit and spirit of the present invention. Moreover, all the terms included in the technical contents described above should be construed in an illustrative sense rather than a restrictive sense.

1 is a diagram illustrating a memory module of a conventional technique. 1 is a diagram illustrating a memory module according to an exemplary embodiment of the present invention. 1 is a diagram illustrating a memory device according to an exemplary embodiment of the present invention. 4 is a diagram illustrating a memory module according to another exemplary embodiment of the present invention. 4 is a diagram illustrating a memory module according to another exemplary embodiment of the present invention. 4 is a diagram illustrating a memory module according to another exemplary embodiment of the present invention. 4 is a diagram illustrating a memory module according to another exemplary embodiment of the present invention. 1 is a diagram illustrating a memory system according to an exemplary embodiment of the present invention. FIG. 9 illustrates the hub of FIG. 8 according to a preferred embodiment of the present invention. 1 is a diagram illustrating a clock selection circuit according to an exemplary embodiment of the present invention. 5 is a diagram illustrating a clock selection circuit according to another exemplary embodiment of the present invention. 5 is a diagram illustrating a clock selection circuit according to another preferred embodiment of the present invention.

Explanation of symbols

10 Southbound packet 14 Northbound packet 20, 50, 60, 70 Memory module 100 Memory system 502 Receiver 504 Transmitter 506 Phase locked loop 508 Setting register 510 Hub 512, 612, 712 Clock selection circuit 514 Memory interface register 520 Memory device 600 Memory controller 1002 R-delay 1004 D-delay

Claims (28)

A phase-locked loop that receives an external periodic clock and generates one or more internal periodic clocks;
A plurality of memory units that receive an input of the internal periodic clock or the first non-periodic clock from the outside;
A memory module comprising: Upon receiving the control information and address information from the internal periodic clock and the outside,
2. The memory module according to claim 1, further comprising a register that provides the control information and the address information to the plurality of memory units in synchronization with the internal cycle clock that has received the input.   The memory module according to claim 1, wherein each of the plurality of memory units receives control information and address information from the outside. Each of the plurality of memory units includes
A mode setting circuit for receiving an input signal and outputting a mode signal;
A clock selection circuit that receives the input of the internal periodic clock and the non-periodic clock, and outputs the internal periodic clock or the aperiodic clock according to the mode signal;
The memory module according to claim 2, further comprising: A register for receiving the control information and the address information from the internal cycle clock and the outside, and outputting the control information and the address information to the plurality of memory units in synchronization with the received internal cycle clock;
A memory clock selection circuit that receives the first aperiodic clock, the internal periodic clock, and a mode selection signal, and provides the internal periodic clock or the first aperiodic clock to the plurality of memory units according to the mode selection signal; The memory module according to claim 1, further comprising a clock selection circuit.   6. The memory clock selection circuit further comprises a switch for selectively providing the internal periodic clock or the first non-periodic clock to the plurality of memory units according to the mode selection signal. The memory module described. A register for receiving control information and address information from the outside and providing the control information and the address information to the plurality of memory units;
A clock selection circuit, the clock selection circuit comprising:
In response to the input of the first aperiodic clock, the internal periodic clock, and the first mode selection signal, the internal mode clock or the first aperiodic clock is provided to the plurality of memory units according to the first mode selection signal. A memory clock selection circuit;
A register clock that receives the first aperiodic clock, the internal periodic clock, and the second mode selection signal, and provides the internal periodic clock or the first aperiodic clock to the register according to the second mode selection signal. A selection circuit;
The memory module according to claim 1, further comprising: The memory clock selection circuit further includes a first switch for selectively providing the internal periodic clock or the first non-periodic clock to the plurality of memory units in response to the first mode selection signal;
The register clock selection circuit further comprises a second switch for selectively providing the internal periodic clock or the first non-periodic clock to the register in response to the second mode selection signal. Item 8. The memory module according to Item 7. A register for receiving control information and address information from the outside, and providing the control information and address information to the plurality of memory units;
A clock selection circuit, the clock selection circuit comprising:
The plurality of memory units receive the first aperiodic clock, the internal periodic clock, and the first mode selection signal, and change the internal periodic clock or the first aperiodic clock to the plurality of memory units according to the first mode selection signal. A memory clock selection circuit to provide,
In response to the input of the second aperiodic clock, the internal periodic clock, and the second mode selection signal, the internal periodic clock or the second aperiodic clock is provided to the register in response to the second mode selection signal. The memory module according to claim 1, further comprising a register clock selection circuit. The memory clock selection circuit includes:
A first switch for selectively providing the internal periodic clock or the first non-periodic clock to the plurality of memory units in response to the first mode selection signal;
The register clock selection circuit further comprises a second switch for selectively providing the internal periodic clock or the second non-periodic clock to the register in response to the second mode selection signal. The memory module according to claim 9. A phase-locked loop that receives an external periodic clock and generates at least one internal periodic clock;
A setting register that receives one mode setting signal and generates one or more control signals;
A memory interface register that receives input of memory information and provides the memory information to a plurality of memory units;
In response to the input of the first aperiodic clock, the internal periodic clock, and the one or more control signals, the plurality of the internal periodic clock or the first aperiodic clock in response to the one or more control signals. A clock selection circuit provided to the memory unit and the memory interface register;
A hub of a memory module, comprising:   12. The hub of a memory module according to claim 11, wherein the memory information includes address information, control information, or data. The clock selection circuit includes:
The first non-periodic clock, the internal periodic clock, and the one or more control signals are input with a first control signal and in response to the first control signal, the internal periodic clock or the first non-periodic clock. A memory clock selection circuit for selectively providing a clock to the plurality of memory units;
The second non-periodic clock, the other internal periodic clock, and the one or more control signals are input with a second control signal and in response to the second control signal, the other internal periodic clock or the first A register clock selection circuit for selectively providing one aperiodic clock to the register;
12. The hub of the memory module according to claim 11, further comprising: The clock selection circuit includes:
The first non-periodic clock, the internal periodic clock, and the one or more control signals are input with a first control signal and in response to the first control signal, the internal periodic clock or the first non-periodic clock. A memory clock selection circuit for selectively providing a clock to the plurality of memory units;
The second non-periodic clock, the other internal periodic clock, and the one or more control signals are input with a second control signal and in response to the second control signal, the other internal periodic clock or the second 12. The hub of the memory module according to claim 11, further comprising: a register clock selection circuit that selectively provides a non-periodic clock to the register. The memory clock selection circuit further includes a first delay element that delays the internal periodic clock or the non-periodic clock,
15. The hub of a memory module according to claim 14, wherein the register clock selection circuit further comprises a second delay element that delays the other internal periodic clock or the second non-periodic clock. A mode setting circuit that receives an input signal and outputs a mode signal;
A clock selection circuit that receives an input of a periodic clock and an aperiodic clock and outputs the periodic clock or the aperiodic clock in response to the mode signal;
A memory unit comprising:   17. The memory unit according to claim 16, further comprising a clock buffer that receives an input of the periodic clock or the non-periodic clock from the clock selection circuit and outputs an internal clock.   18. The memory unit according to claim 17, further comprising one or more memory information buffers that receive the clock output from the clock buffer.   The memory unit of claim 16, wherein the mode signal is provided by a mode register setting operation. A first input pin for receiving an input of a periodic clock in a normal operation mode;
A second input pin for receiving an aperiodic clock in a test operation mode;
A clock selection circuit for receiving the periodic clock and the aperiodic clock and outputting the periodic clock or the aperiodic clock in response to a mode selection signal;
A clock buffer for receiving an input of the periodic clock or the non-periodic clock from the clock selection circuit and outputting an internal clock;
A memory unit comprising:   21. The memory unit according to claim 20, wherein the second input pin receives a data strobe signal or a data mask signal in the normal operation mode, and receives the non-periodic clock in the test operation mode. . The clock selection circuit includes:
A first switch that selects the periodic clock in response to a first state of the mode selection signal and outputs the periodic clock to the clock buffer;
The memory unit according to claim 21, further comprising a second switch that selects the non-periodic clock in response to a second state of the mode selection signal and outputs the aperiodic clock to the clock buffer.   The clock selection circuit further includes a third switch that selects the data strobe signal or the data mask signal in response to the first state of the mode selection signal and outputs the selected signal to the data strobe buffer or the data mask buffer. 23. The memory unit according to claim 22, wherein: A method of providing a clock to a memory module having a phase locked loop and a plurality of memory units,
Providing a periodic clock to the phase locked loop in a normal mode of operation;
Providing an aperiodic clock directly to the plurality of memory units in a test mode of operation;
A clock providing method comprising: A method for providing a clock to a plurality of memory units of a memory module having a hub, comprising:
Receiving an external periodic clock and generating an internal periodic clock;
Receiving a mode setting signal and generating a control signal;
Receiving the aperiodic clock, the internal periodic clock, and the control signal, and providing the internal periodic clock or the aperiodic clock to the plurality of memory units and the memory interface register in response to the control signal; ,
Receiving control information and address information and providing the control information and address information to the plurality of memory units in synchronization with the internal periodic clock or the non-periodic clock;
A clock providing method comprising: Receiving an input signal and outputting a mode setting signal;
Receiving an input of a periodic clock and an aperiodic clock; and
In response to the mode setting signal, selecting the periodic clock or the non-periodic clock and outputting the selected clock to a clock buffer;
Generating an internal clock in the clock buffer in response to the selected clock;
An internal clock generation method comprising: Multiple memory units;
A memory module comprising: the memory module hub according to claim 11. A plurality of memory modules each including a memory module hub;
A clock generation source for providing the external periodic clock;
A memory system comprising: a memory controller that controls the plurality of memory modules.

Images