TW201439714A - System and method for determining a time for safely sampling a signal of a clock domain - Google Patents

Abstract

A system and method are provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a phase estimate of a first clock domain is calculated based on a relative frequency estimate between a second clock domain and the first clock domain and, based on the phase estimate, a first time during which a signal from the first clock domain is unchanging such that the signal is capable of being safely sampled by the second clock domain is determined to generate a first sampled signal in the second clock domain. Additionally, an updated phase estimate is calculated, and, based on the updated phase estimate, a second time during which the signal from the first clock domain is changing such that the signal is not capable of being safely sampled by the second clock domain is determined. During the second time the first sampled signal in the second clock domain is maintained.

Description

System and method for judging the time to safely sample the signal of the clock domain

The present invention relates to transmitting signals between clock domains, and more particularly to synchronizing clock domains.

Many digital systems have multiple clock domains. Therefore, when signals are moved from one clock domain to another, they must be synchronized to avoid metastable and synchronization failures. If the two clocks have a fixed frequency, the phases between the two clocks are periodic under the beat frequencies of the two clocks. The periodic synchronizer can take advantage of this periodic phase relationship to be simpler, has a lower latency, and has a lower probability of failure than a synchronizer that must process a completely asynchronous signal.

Unfortunately, traditional periodic synchronizers have a number of limitations. For example, the signals of most existing systems are synchronized with the periodic clock using a non-synchronous first-in first-out (FIFO). These can cause a large area burden on the FIFO memory. Because the FIFO's Gray-coded input and output metrics must be synchronized across multiple flip-flops to move them across the clock domain, the FIFOs also add several delay cycles.

There is therefore a need to address these and/or other issues associated with prior art.

The present invention provides a time for judging a signal for safely sampling a clock domain System and method. In a specific embodiment, a phase estimate of a first clock domain is calculated based on a relative frequency estimate between a second clock domain and the first clock domain, and based on the phase estimate, the decision is made. a first time to generate a first sampling signal in the second clock domain, wherein during the first time, a signal of the first clock domain is not changed, so that the signal can be used by the second The clock domain is safely sampled. In addition, an updated phase estimate is calculated, and based on the updated phase estimate, a second time is determined, wherein during the second time, the signal from the first clock domain is changing, such that the signal cannot be The second clock domain is safely sampled. The first sampled signal is maintained in the second clock domain during the second time period.

100‧‧‧ method

102‧‧‧ homework

104‧‧‧ homework

200‧‧‧ method

204‧‧‧ homework

206‧‧‧ homework

300‧‧‧All-digit periodic synchronizer

400‧‧‧frequency estimator

500‧‧‧ phase detector

510‧‧‧ phase detector

520‧‧‧ four-sample phase detector

530‧‧‧ phase detector corrector

540‧‧‧ phase detector

600‧‧‧ Phase Estimator

700‧‧‧ conflict detector

800‧‧ ‧ one-half party collision detector

900‧‧‧ Forward Synchronizer

1200‧‧‧Synchronizer

1400‧‧‧ phase loop

1500‧‧‧First In First Out Synchronizer

1600‧‧‧First In First Out Synchronizer

1800‧‧‧ system

1801‧‧‧Master processor

1802‧‧‧Communication bus

1804‧‧‧ main memory

1806‧‧‧Graphic processor

1808‧‧‧ display

1810‧‧‧Secondary storage

1905‧‧‧ homework

1906‧‧‧ homework

1907‧‧‧ homework

1908‧‧‧ homework

1909‧‧‧ homework

1910‧‧‧ Forward Synchronizer

1911, 1912‧‧ ‧ register

1915‧‧‧Output register

1916‧‧‧Selection unit

1917‧‧‧Selected signals

1930‧‧‧Synchronizer state diagram

1 illustrates a method for determining the time at which a signal of a time domain can be safely sampled using a frequency estimate, in accordance with an embodiment.

2 illustrates a method for determining the time at which a signal of a time domain can be safely sampled using a phase estimate, in accordance with another embodiment.

3 illustrates an all-digital periodic synchronizer for safely sampling a signal of a clock domain using a phase estimate, in accordance with yet another embodiment.

FIG. 4 illustrates a frequency estimator in accordance with yet another embodiment.

FIG. 5A illustrates a phase detector in accordance with another embodiment.

Figure 5B illustrates a phase detector for separating early and late detections in accordance with yet another embodiment.

Figure 5C illustrates a four sample phase detector in accordance with yet another embodiment.

Figure 5D illustrates a phase detector corrector in accordance with another embodiment.

Figure 5E illustrates a phase detector for detecting even and odd phases in accordance with another embodiment.

Figure 6 illustrates a phase estimator in accordance with yet another embodiment.

Figure 7 illustrates a collision detector in accordance with yet another embodiment.

Figure 8 illustrates a one-half one-party collision detector in accordance with another embodiment.

Figure 9 illustrates a forward synchronizer in accordance with yet another embodiment.

Figure 10 illustrates a synchronizer state diagram in accordance with the operation of the forward synchronizer shown in Figure 9.

Fig. 11 is a timing chart showing the operation of the forward synchronizer shown in Fig. 9.

Figure 12 illustrates a synchronizer with flow control in accordance with yet another embodiment.

Figure 13 illustrates a timing diagram of the operation of the flow controlled synchronizer shown in Figure 12.

Figure 14 illustrates a phase loop showing an even and odd number of inbound regions and an area in which the even register is selected, in accordance with another embodiment.

Figure 15 illustrates a FIFO synchronizer using an even/odd forward synchronizer in accordance with another embodiment.

Figure 16 illustrates a FIFO synchronizer in accordance with another embodiment in which the even and odd versions of the head and tail end indicators are retained to further reduce the FIFO latency.

17A-D illustrate various phase loops in accordance with other embodiments.

FIG. 18 illustrates an exemplary system in which various architectures and/or functions of various prior embodiments may be implemented.

Figure 19A illustrates a method for determining the time at which a signal of a time domain can be safely sampled using a phase estimate, in accordance with yet another embodiment.

Figure 19B illustrates a forward synchronizer in accordance with yet another embodiment.

Figure 19C illustrates a synchronizer state diagram in accordance with the operation of the forward synchronizer shown in Figure 19B.

Table 1 illustrates various symbols and signal names referred to in the description of the following figures, and exemplary values of at least some of these symbols and signal names.

In addition, examples of such various embodiments included below are disclosed in 2010 by Symbian J. Dally and Stephen G. Tell in 2010 IEEE Symposium on Asynchronous Circuits and Systems, Proceedings of Asynchronous Circuits and Systems International Symposium 75- On page 84, "Even/Odd Synchronizer: A Fast Full-Digital Synchronizer" (The Even/Odd Synchronizer: A Fast, All-Digital, Periodic Synchronizer), which is hereby incorporated by reference in its entirety.

1 illustrates a method 100 for determining the time at which a signal of a time domain can be safely sampled using a frequency estimate, in accordance with an embodiment. As shown in operation 102, a frequency estimate for a first clock domain is calculated using a frequency estimator. In the present case, the first clock domain may include a clock domain of any system that can sample a signal (e.g., a clock having a particular frequency). For example, the first clock domain may include a central processing unit (CPU, "Central processing unit"), a graphics processing unit (GPU, "Graphics processing unit"), a memory controller, and/or a clock domain. One of the other systems of the clock domain.

As mentioned above, the first clock domain can include the clock of the system. In addition, the clock domain can operate at a particular frequency (e.g., transmit signals). For this purpose, the frequency estimate of the first clock domain may comprise an estimate (e.g., measurement, etc.) of the frequency of the clock of the system.

In a specific embodiment, the frequency estimate can utilize a pair of b-bit counters Calculation. For example, a first one of the counters (hereinafter referred to as the first counter) can be clocked by the first clock domain and can count pulses of the clock in the first clock domain. In addition, a second one of the counters (hereinafter referred to as a second counter) may count a pulse of a clock in a second clock domain required for sampling a signal from the first clock domain, and may be Two-time domain timing. It must be noted that the second clock domain may comprise a clock domain of a system whereby the signal of the first clock domain may be sampled, thus being different from the system associated with the first clock domain. For example, the frequency of the first clock domain may be different from the frequency of the second clock domain.

When the second counter reaches its terminal count value, the first counter is stopped. In this manner, the time at which the first counter counts the pulse can be equal to the time at which the second counter is used to reach the terminal count value. The count value of the first counter can then be recorded in a register. This first count value may indicate a frequency estimate for the first clock domain.

In another embodiment, the frequency estimate may not be calculated by measuring the frequency of each of the first clock domain and the second clock domain. In such a specific embodiment, the first clock domain and the second clock domain may have a frequency that is a rational number. For example, the frequency of the first clock domain may be equal to the frequency of the second clock domain multiplied by N/D, where N and D are integers. Thus, for integers N and D, the frequency estimate can be calculated as N divided by D(N/D).

The frequency estimator used to calculate the frequency estimate can be included in a synchronizer. For example, the synchronizer may be implemented between a system associated with the first clock domain and a system associated with the second clock domain for synchronizing the first clock domain with the second clock domain Inter-signal (eg, for synchronizing samples of the signal from the second clock domain from the first clock domain). As described below, such synchronization can be performed based on the calculated frequency estimate.

Additionally, as shown in operation 104, the frequency estimate is used to determine a time such that the signal can be safely sampled by the second clock domain, during which time a signal from the first clock domain is not change. For example, the time during which the signal from the first clock domain has not changed may include that the signal from the first clock domain has not changed (eg, static, etc.) in time. One phase of the first clock domain. In another example, the time during which the signal from the first clock domain has not changed may include any time period other than a detected edge associated with a clock edge of the first clock domain. For example, it may be known that the signal changes in synchronization with the edges of the clock of the first clock domain. Therefore, the detection range may include a first time period before a clock edge of the first clock domain and a second time period after the clock edge of the first clock domain.

In a specific embodiment, the signal from the first clock domain does not change the time of the period, and may be determined based on recognizing that the first clock domain is reasonably related to the second clock domain. The rational relationship may be due to the frequency of the first clock domain and the frequency of the second clock, and the frequency of the first clock domain and the frequency of the second clock are both divided by one The reference frequency and then the multiplied phase locked loop (PLL, "Phase-locked-loops") is generated from a common crystal reference frequency.

In another embodiment, when it is recognized that the first clock domain and the second clock domain are in a rational correlation, it is automatically determined that the phase of the first clock domain has not changed (and thus cannot It is detected) or changes slowly. Therefore, the determination of the time during which the signal from the first clock domain has not changed may not require an estimate of the phase using the first clock domain (eg, thus utilizing only the frequency of the first clock domain) estimate).

For example, the phase can be expressed as P = a.b/D, where "a" is an integer part, "b" is a fractional part, and D is the denominator of a rational correlation frequency. In this manner, the phase can be detected and the upper and lower (lp) limits can be initialized to the boundaries of the detection region in proportion to D, as described above. In a specific embodiment, a first detection can initialize the phase boundaries (up and lp). The D relative phases can be repeatedly visited, at least one of which is expected to cause a detection (and thus detect a possible conflict). After the D+1 cycles that are not detected, it can be determined that all D relative cycles between the two clocks do not cause a collision, so that the time from the first clock domain does not change. It is judged so that the signal can be safely sampled by the second clock domain.

2 illustrates a method for using a phase estimate in accordance with another embodiment. To determine the method of safely sampling the time of a signal in a time domain. As shown in operation 202, a frequency estimate for a first clock domain is calculated using a frequency estimator. With respect to the present description, the frequency estimate can be calculated in the manner described above with respect to job 102 of FIG.

Additionally, as shown in operation 204, a phase estimate of the first clock domain is calculated based on the frequency estimate using a phase estimator. In a specific embodiment, a phase of the first clock domain can be detected. For example, early and late samples may be from the first clock domain relative to the second clock domain.

The early and late samples may include sample pairs, each pair consisting of an early sample and a late sample. Additionally, the early and late samples may be synchronized to one of the first clock domains. If a pair of early and late samples differ, it can be determined that a transition occurs during the detection zone (e.g., time) that occurs between the time the early and late samples were taken. In this way, a phase of the first clock domain can be detected.

In another embodiment, the phase estimate can be calculated based on the phase detection. For example, one b-bit operation estimate for the phase of the first clock domain may be maintained relative to the second clock domain. The phase estimate can be a b-bit portion that represents a value between 0 and 1 around a unit cycle. Additionally, the phase estimate can be reset to indicate that the first clock domain can be safely sampled each time the phase is detected in the manner described above.

In another embodiment, at the time of detection, the phase of the first clock domain must be set to f(S+1), wherein an additional loop is added to S (the delay of the synchronizer) to predict This phase estimate of a cycle before it occurs. The phase of the first clock domain described above may be set to f(S+1), so the phase estimate predicts the phase of the first clock domain at the next rising edge of the second clock domain. For example, the phase estimate can encode the phase within the even and odd cycles of the first clock domain. If the phase is not detected, the phase estimate may be incremented at the relative frequency of the first clock domain during each cycle of the second clock domain. For this purpose, an in-run phase estimate can be maintained. It must be noted that in addition to the frequency detector, the phase detector and the phase estimator can also be included in a synchronizer. For example, the synchronizer can be implemented Between the system associated with the first clock domain and a system associated with the second clock domain, for synchronizing signals between the first clock domain and the second clock domain (eg, Synchronizing the sampling of the signal from the second clock domain from the first clock domain). As described below, such synchronization can be performed based on the calculated phase estimate.

Furthermore, as shown in operation 206, the phase estimate is used to determine a time such that the signal can be safely sampled by the second clock domain, and a signal from the first clock domain is not present during the time. change. As described above, the phase estimate can indicate the time during which sampling can be safely performed by the first clock domain (i.e., when the signal from the first clock domain is known to have not changed).

For example, the phase estimate can predict the phase of the first clock domain at the next rising edge of the second clock domain. This may allow a delayed version of the input data to be sampled before the rising edge of the second clock domain is sampled before a direct input in which the inbound region is being converted (and thus may be changing) .

More illustrative information will now be presented with respect to a variety of alternative architectures and features, whereby the aforementioned architecture can be implemented according to the needs of the user. It is important to note that the following information is presented for illustrative purposes and should not be construed as limiting in any way. Any of the following features may be added or excluded as desired.

3 illustrates a full-digit periodic synchronizer 300 for safely sampling a signal of a clock domain using a phase estimate, in accordance with yet another embodiment. Alternatively, full digit periodic synchronizer 300 can be implemented to perform the methods of FIGS. 1 and/or 2. But of course the full digital periodic synchronizer 300 can be implemented in any desired environment. It must also be noted that the aforementioned definitions can also be applied hereinafter.

An arbitrary periodic signal can be synchronized using the entire digital component by measuring its frequency and phase, and then using this information to determine when it is safe to use the receive clock to simply sample the signal and when to directly sample it. It is safe to use a delayed clock. By using this frequency and phase, the use of FIFO memory can be avoided. In addition, synchronization delays can be reduced (eg, by avoiding synchronization via the brute-force synchronizer) The head and tail indicators of the code).

If a FIFO synchronizer is used for flow control, the synchronizer can replace a brute force synchronizer (using multiple series of flip-flops) for synchronizing the FIFO headend and tail end metrics. This reduces the latency of the FIFO synchronizer and avoids the use of Gray-coded metrics (which would otherwise require maintaining both Gray coding and binarization metrics).

In particular embodiments regarding the present embodiment, a signal d may be entered at the time of transmitting a synchronized clock (clock belonging to a domain transfer) TCLK, having a clock RCLK (belonging to a receiving clock domain) below the received frequency of f _R A fixed frequency f _T . The specific embodiments described herein can also be practiced when f _{T is} higher than f _R .

As shown, a frequency estimation block uses a pair of b-bit counters to measure the frequency of the transmitted clock. The frequency estimation block outputs a b-bit relative frequency f = f _T / f _R mod 2f.

A phase detection block records the time at which the transmission clock entered the detection region of the reception clock for the last time. When this occurs, a detection signal (det) is output. Since the detection signal is synchronized, it reflects the phase of the transmission clock before the S reception cycles. It must be noted that multiple detection zones and signals can be utilized. However, with respect to this embodiment, a single bit detection signal is assumed.

A phase estimation block retains one of the phases of the received clock to run an estimate. It sets the phase p to (S+1)f each time a detection is received, and increments the operating phase by f for each cycle of the undetected rclk.

Finally, a collision detection block uses the current phase estimate to determine when to sample directly as safe or when to delay sampling. When phase p is in a window near the dangerous point, collision signal c is asserted, which instructs a multiplexer to sample a delayed version of the near-synchronous input.

The synchronizer data path accepts an input d1 that is synchronized to a a bit wide of tclk. In the figure, d1 is generated by the register F1 clocked by tclk. Optionally, the register F1 It may not be necessary to be part of the synchronizer 300. However, the signal d1 can come directly from a register without the logic of the intermediary, as an alternative. Latch L1 (or a flip-flop, not shown) samples signal d1 on the falling edge of rclk to produce a delayed input signal d2. A multiplexer selects the direct input d1 when there is no conflict, and selects the delayed input d2 when there is a conflict. The result of this selection, dx, is guaranteed to be safely sampled by the scratchpad F2, which produces an output ds synchronized to rclk.

The conflict detection window is set such that sampling is safe on the selected input of the multiplexer. When c is set and the multiplexer selects d2, the sampling of the signal d1 by the latch L1 on the falling edge of rclk can be guaranteed to be safe. When c is not asserted, the sampling of d1 by the register F2 on the rising edge of rclk can be guaranteed to be safe.

Synchronizer 300 uses latch L1 to delay input d1 for a half cycle (sampling on this falling edge of clk _R ). Therefore, a phase delay of p _D = 0.5 can be provided. As an alternative, different timing latches or registers can be used to delay the different amounts of d1. As yet another option, a delay line (e.g., an even number of inverters in series) can be used to delay the signal d1 for a sufficient amount of time to make the sampling by the register F2 safe. These alternatives can provide different values for p _D .

FIG. 4 illustrates a frequency estimator 400 in accordance with yet another embodiment. Alternatively, frequency estimator 400 can be implemented in the context of the functions and architecture of Figures 1-3. But of course the frequency estimator 400 can be implemented in any desired environment. It must also be noted that the aforementioned definitions can also be applied hereinafter.

The synchronizer of Figure 3 relies on having an accurate estimate of the phase of the transmitted clock at the end of each receive clock cycle. This estimate produces a phase estimate by first measuring the relative frequency of the transmitted clock (as shown in Figure 3) and then using this frequency estimate to connect the same phase detector (as shown in Figure 5E). This phase estimate is calculated using interval arithmetic to maintain an accurate margin of error at that phase.

A block diagram 400 of the frequency measurement unit is provided as shown in Figure 4, which uses a pair of counters to calculate f, i.e., the frequency of the transmit clock relative to the receive clock. The frequency measurement procedure is initiated by a start signal st. The rising edge of st resets the receive counter (CR, "Receive counter"). The start signal is also transmitted to the transmit clock (tclk) field via a brute force synchronizer, ie a signal st _T for resetting the transfer counter (CT, "Transmit counter") is generated.

When the receive counter reaches a terminal count (e.g., a b = 10 bit counter count is 1023), the signal tc is set and synchronized to the tclk field. The synchronized terminal count signal tc _T stops the transfer counter. The delays of the sp and tc synchronizers are balanced, so the final count from the CT reflects the number of tclk cycles that occur during 2 ^b receive clock (rclk) cycles, ie the relative frequency of the transmitter f = f _T /f _R . The terminal count signal is synchronized back to the rclk domain to generate a signal tc _TR indicating when the frequency measurement f is ready and enabling it to be captured in the result register (RR, "Result register") .

The counter CT produces a result of a b+1 bit, so f produces a modulus of two. It is a fixed number of bits with one bit to the left of the binarization point and b bits to the right. The transmit frequency estimate modulus 2 is calculated instead of modulus 1, so the phase estimator (as explained below with respect to Figure 5E) can track that the transmitter is in an odd or even clock cycle.

There are three brute force synchronizers in the frequency measurement block of Figure 4. These synchronizers are used only once, meaning that the frequency is measured after reset. All of these synchronizers are outside of this critical path, so their delay can be set to arbitrarily high, thereby achieving an arbitrarily low probability of synchronization failure. Basically, a delay S of four or five clock cycles is sufficient to provide a probability of failure below 10 ^-40 .

Each of the start signal and the terminal count synchronizer introduces a cyclic uncertainty to the frequency measurement. Therefore, the output of the frequency measurement block is exactly ±1 LSB, which is ±2 ^-b .

FIG. 5A illustrates a phase detector 500 in accordance with another embodiment. Alternatively, phase detector 500 can be implemented in the functional and architectural environments of Figures 1-4. For example, the phase detector can include a component of the phase estimator described above. But of course the phase detector 500 can be implemented in any desired environment. It must also be noted that the aforementioned definitions can also be applied hereinafter.

As shown, the phase detection logic displayed with respect to phase detector 500 can be operated by taking early and late samples of a signal d _T synchronized with tclk with respect to rclk. If the early and late samples are different, it is determined that a transition occurs during the detection zone. The flip-flop F1 is generated by a signal d _T synchronized with tclk of each cyclic thixotropic. Relative to rclk, the signal d _T is sampled early by the flip-flop F3 and is sampled late by the flip-flop F2. The flip-flop F2 is clocked by a version of rclk delayed by T1, so d _{T is} sampled at time T1 after the rising edge of rclk. The result of the late sampling of this d _T is the signal d _L . The flip-flop F3 delays the signal d _T time T2 before sampling with rclk. This effect is the same as sampling d _T at time T2 before rclk. The result of this early sampling is the signal d _E .

The signals d _L and d _E are the result of sampling an unsynchronized signal, so that a metastable state can be entered. In order to allow time to settle out any metastability, these signals are transmitted through brute force synchronizers S1 and S2, respectively. This produces a delayed and synchronized version of these late and early signals, namely d _LS and d _ES . In order to achieve a sufficiently low probability of synchronization failure, the signals d _LS and d _ES will be delayed by S (substantially 2 to 4) of rclk by d _L and d _E . The flip-flops F2 and F3 can be considered as the first phase of the synchronizers S1 and S2, respectively, or these flip-flops can be omitted, and the synchronizers are used directly to take the early and late samples.

Mutual exclusion or gate X1 detects when there is a difference between d _LS and d _ES . The output det of this gate, when the signal is true before S cycles, the signal d _T has undergone a transition in the window [-T2, T1] of the conversion with respect to rclk. In this manner, phase detector 500 can detect when the transmit clock phase is in the range [-T2/T, T1/T], where T is the transmit clock cycle.

Delay lines T1 and T2 can be implemented by an even number of inverters in a chain. These delays must be made large enough to include the inward window t _ko = t _s + t _{h of the} register F2 plus a guard band g on either side of the inbound region. Four to eight fan-out of one (FO1) inverters can be used for each delay line as needed.

When only a single phase detector is shown here, it must be noted that two phase detectors can be used, one on the rising edge of rclk and one on the falling edge of rclk. The two detection signals can be used to reset the phase estimate to zero (plus (S+1)f) when a detection occurs on the rising edge of rclk, and reset when it occurs on the falling edge of rclk To 0.5 (plus (S+1)f). This prevents a metastable state from being sampled by the delayed path when the phase is processed very slowly.

As explained below with respect to Figures 5B-D, phase detector 500 can be modified to use multiple samples to provide a more accurate phase measurement that can be retained at the upper and lower limits of the phase estimate (e.g., using intervals) Arithmetic to calculate the phase) is used to allow a more accurate determination of when a clock is in the "incoming" region of the other, and can be automatically corrected to determine which portion of the loop is being detected.

Figure 5B illustrates a phase detector 510 for separating early and late detections in accordance with yet another embodiment. Alternatively, phase detector 510 can be implemented in the context of the functions and architecture of Figures 1-4. But of course, phase detector 510 can be implemented in any desired environment. It must also be noted that the foregoing definitions can also be applied hereinafter.

As shown, there are two outputs, including detE for detecting when the transmit phase is in the range [-T2/T, 0], and detL for detecting when the phase is in the range [0, T1/T] in. By using detE and detL, the phase estimate calculated based on the detected phase can be more accurately defined.

FIG. 5C illustrates a four sample phase detector 520 in accordance with yet another embodiment. Alternatively, four sample phase detector 520 can be implemented in the context of the functions and architecture of Figures 1-4. But of course, the four sample phase detector 520 can be implemented in any desired environment. It must also be noted that the foregoing definitions can also be applied hereinafter.

As shown, an additional delay line (relative to phase detector 510 in Figure 5B) can be included to generate additional detection signals. It must be noted that the number of additional delay lines that can be included can be any desired number that needs to be expanded. More accurate by adding a delay line Phase information. The four-sample phase detector 520 generates detLL when the transmission phase is in [-2T2/T, -T2/T], and generates detEE when the phase is in [T1/T, 2T1/T].

When the phase is detected, the original fast periodic synchronizer can effectively zero the phase estimate (eg, set the phase to (S+1)f as the delay of synchronizing the S cycles of the phase detection) . The time during which the transmission phase is in the inbound region can be more accurately detected by maintaining the upper and lower limits on the phase estimate (e.g., by using interval arithmetic to calculate the phase estimate). The limits of the frequency can be used for such updates of the phase estimate. Since the two synchronizers in Fig. 4 each introduce only one cycle of uncertainty, the frequency is limited to the range [f-1, f+1].

Table 2 illustrates an example of a Verilog code that can be used to update the upper and lower phase estimates (up and lp, respectively) using phase detector 510 of Figure 5B. Of course, it must be noted that the code presented in Table 2 is for illustrative purposes only and therefore cannot be considered limiting in any way.

The code shown in Table 2 sets the upper and lower limits for appropriate values on a phase detection. They are then developed over time using the boundaries of the frequency. The upper and lower limits of the phase estimation are used to indicate that when these limits overlap the region [-c, c] of the guard band, the transmission time domain is in the inaccess zone. For example, this may occur when the upper or lower limit is in the inbound zone or if the upper limit is positive and the lower limit is negative.

The last case shown in Table 3 covers the situation where the phase region includes the entire inbound zone. Table 3 illustrates an example of a Verilog code that can implement symbol based arithmetic for using the upper and lower limits of phase estimation. Of course, it must be noted that the code presented in Table 3 is for illustrative purposes only and therefore cannot be considered limiting in any way.

Table 4 illustrates an example of a Verilog code that can implement unsigned based arithmetic for using the upper and lower limits of phase estimation. Of course, it must be noted that the codes presented in Table 4 are for illustrative purposes only and therefore cannot be considered limiting in any way.

Using the unsigned representation shown in Table 4, the phase increases from 0 to the maximum (all are 1 s), and cneg is a large positive value corresponding to -c (nearly all 1s). Using an even/odd synchronizer (as described below), separate do not allow even (koe) and no odd (koo) signals can be generated in this way by identifying whether ko is even or odd by the current Tx cycle. .

In addition, in order to determine the actual size level such as T1/T, T2/T, in addition to T (transmitter cycle time), the process changes for determining T1 and T2 are utilized. This can assume that the synchronizer is in the receiver time domain. If the synchronizer is in the transmit time domain (e.g., estimating the receiver phase), then it is in the receiver cycle time.

If the transmission and reception clocks are not rationally related, T1/T (and T2/T) will be measured by detecting the portion of the transmission cycle that caused a detection. This can be done by joining two An additional counter is used to measure the frequency and complete. If the two clocks are not rationally related, the receive clock will consistently sample the transmit clock and this portion may converge to T1/T (or T2/T).

FIG. 5D illustrates a phase detector corrector 530 in accordance with another embodiment. Alternatively, corrector 530 can be implemented in the context of the functions and architecture of Figures 1-5C. For example, the phase detector corrector can be one of the components of the phase detector described above. But of course, the corrector 530 can be implemented in any desired environment. It must also be noted that the foregoing definitions can also be applied hereinafter.

As shown, the corrector 530 measures the detection interval d. The corrector 530 operates by counting the number of tclk cycles during which the det (det = dete | deto) is true during the 2b tclk cycles required for the counter CT2 to reach its terminal count. This can be 2d as a b-bit binary part. Similar to the frequency estimate, the accuracy of this d measurement is +/-1 due to the uncertainty of the synchronizer delay. Assuming this uncertainty, the output of the CD (a counter) is increased to provide an upper limit for 2d (e.g., such that the upper limit on the detection interval associated with the phase estimate is provided to compensate for the synchronizer delay). At this point (not shown) an additional value can be added to provide the guard band (eg, a limit for d is responsible for voltage and temperature changes, and for intermediate frequency jitter), as described above. Deviating this number to the right by one bit gives d. This completion signal indicates when the measurement of d can be completed.

If the clocks are not rationally correlated, the corrector 530 only samples the tclk phase consistently. If they are rationally correlated, the receiving clock repeatedly visits the same D (rational proportional denominator) point on the unit phase loop. If D is large enough, this is sufficient. The estimated error is less than 1/D. For small D, the phase detector can be calibrated using a separate frequency source (eg, a ring oscillator) to drive the CD counter. For this purpose, the corrector 530 can allow the phase detector to self-correct.

FIG. 5E illustrates a phase detector 540 for detecting even and odd phases, in accordance with another embodiment. Alternatively, phase detector 540 can be implemented in the context of the functions and architecture of Figures 5A-5D. But of course, phase detector 540 can be implemented in any desired environment. It must also be noted that the foregoing definitions can also be applied hereinafter.

Window t _d of the phase detector 540 detects when a transmitting data signals on a conversion will fall around the edge of a received pulse of ±. The phase detector samples the transmitted signal "even" that is thixotropic at each cycle. This signal is high during the even tclk cycle and low during the odd tclk cycle. The flip-flop F2 samples "even" by the rclk delayed by t _d which provides d _L , which is a sample of "even" t _d after the rising edge of rclk , that is, a late sample. An early sample d _E produced by F3 whose sample is delayed by t _d "even."

Between t _d after an edge if "even" occurs before rclk of t _d and rclk, these values sampled by the F3 and F2 will be different. The early and late samples are synchronized to the receive clock domain by a pair of brute force synchronizers that produce synchronized early and late samples d _ES and d _LS , respectively. The difference between the synchronized samples is detected by a pair of gates. If the early sample is high and the late sample is low, then an even edge of tclk is detected (ending an even cycle) and "dete" is set. If the early sample is low and the late sample is high, then an odd edge of tclk is detected and "deto" is set.

There are two brute force synchronizers in the phase detector operating in each cycle of rclk. But similar to those in the frequency measuring unit, these synchronizers are outside the critical path, so their delay can be large, and the frequency of the synchronization failure can be arbitrarily small. The delay S of the combination of the sampled flip-flop plus one of the 4 or 5 cycles of the synchronizer is substantially applicable to maintain a very low frequency of less than 10 ^-40 Hz.

In order to initialize the phase estimator, the value of t _d is defined as follows. While it is possible on the _d t is calculated on a worst-case limit, if the instantaneous value of _d t is measured, and then a guard is added to the charge of this measurement with variation of temperature t _d of the voltage can produce a more Accurate phase estimation.

FIG. 6 illustrates a phase estimator 600 in accordance with yet another embodiment. Alternatively, phase detector 600 can be implemented in the context of the functions and architecture of Figures 1-5E. But of course, phase estimator 600 can be implemented in any desired environment. It must also be noted that the aforementioned definitions can also be applied hereinafter.

As shown, phase estimator 600 operates by running an estimate of one b-bit operation of the phase relative to rclk. This estimate p is a b-bit portion that represents the value between zero and one around a unit cycle. The phase estimate p is reset to (S+1)f each time the phase detection logic sets det to indicate that it has detected a transition of d _T in the window [-T2, T1]. When det is not asserted, the phase is increased by f (i.e., the relative frequency of tclk for each rclk cycle). The register pR retains the b-bit running phase p. If det is set, phase p is reset to (S+1)f before the delay of the synchronizers in the phase detection logic to reflect that the phase is zero before S cycles. When det is low, the phase estimate is updated by adding f to the running sum at each cycle.

Note that this lookahead factor A is set to S+1, so the run phase p predicts the phase of tclk at the next rising edge of rclk. This causes the multiplexer in FIG. 3 to be set to select the delayed version of the input data before the rising edge of rclk samples a direct input that is transitioned in the inbound region.

The accuracy of the phase estimate can be based on the accuracy of the window of the phase detector and the frequency estimate. At the time of detection, the accuracy may initially be equal to the window [-T2, T1] of the phase detector. In response to each cycle that is not detected, the error in the frequency estimate may be a complete LSB.

FIG. 7 illustrates a collision detector 700 in accordance with yet another embodiment. Alternatively, collision detector 700 can be implemented in the context of the functions and architecture of Figures 1-6. But of course, the conflict detector 700 can be implemented in any desired environment. It must also be noted that the aforementioned definitions can also be applied hereinafter.

Collision detector 700 includes a specific embodiment of the hit detection logic. The collision detector 700 compares the operational estimates and limits p _L and p _{H of} the phase P. When p is interpreted as an unsigned number, if p < p _L or p > p _H , the output c will be set. When the phase is interpreted as a signed number, this corresponds to the phase being in the range [p _H , p _L ] (eg, a window around 0). This window can be set larger than the accuracy window [-N2 ^{- (b+1) -} T2, N2 ^{- (b + 1)} + T1].

FIG. 8 illustrates a one-half one-party collision detector 800 in accordance with another embodiment. Alternatively, the one-half-party collision detector 800 can be implemented in the context of the functions and architecture of Figures 1-7. But of course, the one-half party collision detector 800 can be implemented in any desired environment. It must also be noted that the aforementioned definitions can also be applied hereinafter.

When the limits p _L and p _H are limited to a 2 ^-I version, a simpler version of one of the hit detection logics as shown in FIG. 8 can be used. The one-half-party collision detector 800 detects when the most significant i-bits of p are both 0 or both. For example, to detect when p is in the range [-1/8, 1/8], it can be judged when the upper 3 bits of p are both 0s or both are 1s. In another example, by detecting when the upper two bits of p are both 0s or both are 1s, the p-system is detected to be in the range [-1/4, 1/4].

Table 5 illustrates an example of an operation that can be utilized in the all-digital near-synchronizer 300 of FIG. 3 described in Table 6. It must be noted that these parameters and job examples are presented for illustrative purposes only and should not be considered limiting in any way.

This job example is shown as shown in Table 6 below. The first line reflects the number of cycles, and the second line shows the actual phase relative to tclk of rclk. The line labeled Det indicates when the actual phase falls within the detection window of the phase detector. The actual output of the phase detector is three cycles later, as reflected in the row labeled Del. When Del is true, the phase is set to 4f = 0.868, which predicts the actual phase on the next cycle. The line labeled p shows the actual phase. At the time of this initial detection, it is completely accurate, but there may be an error that is as large as the detection window at the time of subsequent detection. The line labeled c shows when the estimate is The phase will fall within the conflict signal, so c is set. Notice that this loop is predicted before the conflict actually occurs. Finally, the line labeled ko shows when the actual clock phase falls within the inner window. When a single case occurs in the table, it can be set correctly by c on the previous cycle.

An analysis of the accuracy of the all-digital near-synchronizer 300 of FIG. 3 is provided below. The relative size of the inward window, the detection window and the collision window may determine the accuracy b required for the frequency and phase estimation. Let d be the size of the detection window, g be the guard band between the detection window and the inaccess window, and c is the size of the collision window. In the above example, d is 0.10, g is 0.04, and c is 0.25.

When determining an accurate phase estimate, the system can explicitly guarantee a secure synchronization. At this sampling time, the transmission phase is known as Φ [lp,up], and if lp [x, 1+x), the even register can be safely sampled. If the system parameters b and d are properly selected, the system can also guarantee safe synchronization in the plesiochronous mode, when an accurate phase estimate is not known, since it is one of lp and up. It is detected that it is sufficiently long when it is diverged by the critical value k. In this near-synchronous case, the range of frequencies is shown to ensure proper sampling at a phase detection for the synchronizer to occur long enough before the inbound event occurs.

Consider the following case of f: For f<g/S (the guard band), there will be a test before an error. In this case, the phase will move slowly enough into the detection zone, where a detection will occur at S cycles before the phase enters the inward window, and give us time before an actual collision occurs. To synchronize the detection, update the phase estimate, and assert the collision signal.

For g/S f < d, there will be a detection at each N = 1/f cycle, each time the phase rotation is at least once around the unit cycle. So as long as 2 ^-b <gck/S, there will be a test before the phase estimate accumulates too much error. (where k = 0.25 is a factor to add extra precision). For example, for these numbers of our example, we would gck/S=(0.04)(0.25)(0.25)/4=.000625, and b=11 bits are sufficient precision.

For f d, f is expressed as having a defined denominator of a rational score plus an error term f = N / D ± e, where D C= 1/ d . As shown below, these properties with a fractional sequence of definite denominators (referred to as Farey sequences) ensure that eDC <1. In this example, there may be a repeating pattern of D points around the phase loop that is offset by De in each D-cycle period. This provides two cases with the same f<d.

If De < g / S, the phase offset of each cycle is sufficiently small, there will be detection before the error, as when f < g / S.

If g/S De<d, a detection occurs in every 1/(D2e) cycle, so if 2 ^-b <gck/S, there will be a test before we accumulate too much error. The requirement for b here is actually the same as the above g/S Case of f<d.

We need to show that for f>d>1/C, we can always represent f as f=N/D±e, where D C and eDC < 1. Consider the Farey sequence F(C), the sequence of rational numbers is between 0 and 1, the denominator D C. For two adjacent numbers from this combination, p/q,r/s will always be r/s=(ps+1)/qs, where q, s<=C and (ps+1)=qr. Then the distance between two adjacent rational numbers p/q and r/s is 1/qs. The value f we assign between p/q and p/q+1/q(s+q) becomes p/q, and the number is from r/s-1/s(s+q) to r/s. Then we know that e = 1 / q (s + q), eDC = (1/q (s + q)) qC = C / (s + q) < 1, because of the nature of the Farey sequence, so s + q>C.

The dependencies between the synchronizer parameters require that they be selected in the order of p _D , d, c, and then b. The value of the phase delay p _D sets some limits on these other parameters. Setting the p _D = 0.5 as in the above example provides the greatest flexibility at the cost of slightly increasing the average delay of the synchronizer. The delay can be reduced by setting p _D to a small value (for example, 0.1). However, this imposes very urgent restrictions on the remaining parameters. Regardless of which value is selected for p _D , the phase detector can be implemented to detect when the conversion of d _T occurs simultaneously at phase 0 and phase p _D , and the phase estimator can be implemented to reset according to two simultaneous events Its phase estimate. When De is very small, the phase will be reset before a sample enters the inbound zone of any sampling path.

The size d of the detection area determines the error in the phase measurement in part, and is therefore set small enough that the phase estimator can accurately distinguish when the direct and delayed data values are to be selected. One limit is d < p _D / 2-k, where k is the accuracy parameter selected for the phase estimator. On the other hand, selecting a small d can result in a small guard band, thus increasing the number of bits utilized in the frequency and phase estimators. In a specific embodiment, setting d to about p _D /4 balances the two limits. Since d is determined by an inverter delay line, its value will vary significantly across the PVT, so the synchronizer is designed to operate at both extreme ends simultaneously.

The maximum tolerance of error is achieved when the collision detection window c is set to half of p _D . For example, when p _D is 0.5 (as in the example above), setting c to [-.25, .25] provides the maximum margin of error. The phase may deviate from 0.25-t _ko, and the synchronizer can still avoid unsafe sampling a signal. On the other hand, the large setting of c causes many "error positive" choices for the delayed data signal, which increases the average synchronizer delay. In a specific embodiment, c is set to [-.25, .25] or [-.125, .125]. Let c be one-half of a second to allow the simpler detection circuit of Figure 8 to be used. Once p _D is selected, the minimum values of d and c, b can be selected as described above, so 2 ^{- b} <gck / S.

Alternatively, the more expensive parts of the all-digital near-synchronizer 300 of Figure 3 can be shared between instances of the synchronizer. A single copy of the frequency estimation block can be shared between all synchronizers that synchronize the signals between tclk and rclk, where the value f is generated by a block and is spread across all synchronizations between the two clock domains. In the device. In a similar manner, a single phase detection block, phase estimation block, and collision detection block can be shared between some synchronizers that share the same phase relationship between tclk and rclk.

FIG. 9 illustrates a forward synchronizer 900 in accordance with yet another embodiment. Alternatively, the forward synchronizer 900 can be implemented in the context of the functions and architecture of Figures 1-2 and 4-8. But of course, the forward synchronizer 900 can be implemented in any desired environment. It must also be noted that the aforementioned definitions can also be applied hereinafter.

With respect to this embodiment, the limitation associated with sampling a delayed version of the signal can be avoided. In order to transfer a multi-bit signal from the transmission to the reception clock domain without using flow control, the transmission clock writes a pair of registers on alternate cycles. For example, register E is written to an even loop (updated at the end of the even loop) and register O is written to an odd loop.

The receiver then uses its phase estimate to select the most recently written transfer register that can be "safely" sampled in the receive time domain (at the end of the current rclk cycle). This selection is based on the predicted tclk phase at the end of the current rclk cycle p. At each receive clock, the register O is selected when the phase of the transmit clock is between e.x and o.x, where e represents the even loop and x is the "into" margin. Otherwise select the E register. This delay of this synchronizer varies between 0.x and 1.x depending on the phase averaged 0.5+0.x.

While the present embodiment is described with respect to even and odd clock cycles and two registers, it must be noted that any number of clock cycles and registers may be utilized in other embodiments. Therefore, the clock cycle can be labeled as modulus N and N registers can be utilized. Increasing the number of scratchpads allows for very large indentation areas (eg, greater than a single UI). For this reason, the use of N scratchpads can be simultaneously applied to the forward synchronizer shown in FIG. 9 with respect to the following figures. The process described in 11 controls the synchronizer.

As shown in FIG. 9 and relative to the transmitter side, "tdata" is alternately written into the E and O registers on each cycle of "tclk". On the receiver side, the selection logic determines that one of the two registers is to be selected for output on "rdata". This decision of the selection logic may be based on a phase estimate of the transmitter clock generated by the frequency and phase estimation logic (not shown). This logic can generate an intermediate signal indicating when the phase is in the even (or odd) recessed area "tkoe" ("tkoo") and when the transmitter is in the even clock cycle "teven."

Table 7 shows an example of a code that can be used to select a signal. It must be noted that these code numbers are presented for illustrative purposes only and should not be construed as limiting in any way.

Thus, with respect to this embodiment, the odd register is selected when the transmitter is in its even clock cycle (the odd register was just written at the end of the odd clock cycle) unless the reception is The pulse system is in the odd number in the inbound area, otherwise the even register is selected.

Upon initialization, the forward synchronizer 900 can go through a number of different states. Table 8 shows these selective states of the forward synchronizer 900 during initialization. Of course, it must be noted that these states are presented for illustrative purposes only and should not be construed as limiting in any way.

As described with respect to Figure 10, upon reset, the forward synchronizer 900 enters the frequency acquisition (FA) state and initiates its counter pairing to measure the frequency of the "other" clock. During this state, the forward synchronizer 900 checks if there is a phase detection (phase falling in the detection area).

Once the frequency is obtained, the phase acquisition (PA) state is entered, and the forward synchronizer 900 waits for a phase detection. At this time, a frequency estimate f and a phase estimate p have been determined and entered the tracking state (T). If there is no phase detection (for example, a timeout occurs), the two clocks are rationally correlated (f=N/D) (or nearly rationally related) to a phase offset, so the D can hit around the phase loop. And away from the detection area. In this example, the M state is entered because the phase is guaranteed to be sufficiently slow that it will be detected before an error occurs.

In the tracking state (T), the forward synchronizer 900 updates the phase estimate every cycle and takes appropriate when the forward synchronizer 900 detects that it is in the even or odd inbound region. action. Since the number of cycles of the last phase detection is counted and when this number exceeds a threshold, the phase estimate is no longer reliable and the forward synchronizer 900 enters the near synchronous (M) state.

If the phase drifts very slowly (either synchronous or near synchronous modulo-rational), the forward synchronizer 900 can be safely synchronized without prediction. In this case (the M state), The forward synchronizer 900 simply detects the entry into the detection zone using a brute force synchronizer and uses a sufficiently large guard band so that an error does not occur during the number of cycles required to synchronize the detection. For example, the even signal from the tclk field is selected directly between the E and O registers. Since the phase changes slowly enough and the guard band g = d-x is sufficiently large, this is safe, so a phase detection will occur when the signal is returned to the T state before the signal is unsafe. Note that in this rational case, when the phase drifts into the detection region, a 1-of-D detection pattern (where D is the rational denominator) can be identified. In this case, it is possible to utilize the T state at the time of the first detection.

The work in this T state relies on a fixed or near fixed frequency. For security (eg, for conditions where the frequency can change over a short period of time, such as when changing between power states), the frequency measurement circuit can operate continuously and compare its measurements to the current estimate. If the difference is greater than a threshold, the forward synchronizer 900 can fall back to the brute force (B) mode. For example, the FIFO synchronizer described above can be adjusted to operate by changing the modalities relative to the frequency by encoding the metrics and operating a pair of brute force synchronizers parallel to the E/O synchronizers. When the frequency is changing, the synchronizers switch to use the brute force synchronizer (B mode). Once the frequencies have stabilized, they change back to using the fast periodic synchronizer (M mode).

The forward synchronizer 900 can be used only for the clocks to periodically or periodically deviate from the unambiguous location (eg, a "non-periodic" signal triggers a brute force mode before the clocks begin to change unexpectedly. State). In this way, detection of frequencies that are too slow to change can be avoided, whereby several unsafe samples between the clock domains can be completed before detecting a change.

As described above, signals having a frequency difference between the pulse of the domain may also be synchronized during a rational number of two, i.e. _{f r = Nf t / D,} N and D are integers. With a rational frequency, an indication that N, D is reasonably related to the two frequencies is provided by the system. The phase between the two clocks is assumed to be unknown and can even vary slowly.

When the clock domains are rationally correlated, no frequency measurements are required. on the contrary, f=N/D becomes this frequency. In addition, the phase can be held multiplied by D for integration. For example, in one embodiment, the phase is represented as having an integer part a and a fractional part b, so the phase p = a.b/D.

Additionally, the phase can be detected as described above with respect to Figures 5B-E. The upper and lower limits up and lp are initialized to a ratio of D to the boundaries of the detection zone. The forward synchronizer 900 begins in an "initial" state. The first detection causes a transition to the "locked" state and initializes the phase boundaries (up and lp). In this locked state, the system repeatedly visits D relative phases, at least one of which is expected to cause a detection (and thus detect a possible collision). After D+1 undetected loops, a transition is made to the "safe" state.

It can therefore be noted that the D relative phases between the two clocks do not cause collisions, so it is safe to simultaneously sample even and odd registers directly in all D phases. In this "locked" state, the scaled phase boundaries (up and lp) rise by adding an N-modulus D to each cycle. There is no uncertainty in this frequency, so these boundaries will not diverge over time.

In this regard, a phase detection (or lack thereof) can be used to dynamically detect the phase difference when the clock domains are rationally correlated. Moreover, by detecting the conflict from the estimated phase, it is possible to avoid using a table of size D to store the conflict pattern so that a large D region can be avoided.

In a specific embodiment, if the phase between the two clocks changes slowly (each cycle is Δp, ie at least the actual frequency is temporarily f _t =Nf _r /D+Δp), then the above The system is implemented as long as Δp<min((dk)/2D, (dk)/2S), where (dk)/2 is the detection region (d) and the inward region (k) The margin between the sides, D is the denominator of the rational frequency, and S is the delay of the phase detector synchronizer. This restriction ensures that the first step of entering the detection zone (up to DΔp) may not penetrate into the inaccess zone, and once detected, the detection may enter the phase at the phase. The inbound area is synchronized before.

In this regard, the phase estimate can be used to construct a fast, simple forward synchronizer. It can move a parallel signal from one periodic clock domain to the other. In particular, in the present embodiment, a forward synchronizer is provided to move a parallel signal from the transmit clock (tclk) field to the receive clock (rclk) field in a synchronization failure. Safe, but no process control. In addition, this synchronizer can be used in a FIFO synchronizer to provide synchronization and flow control as described below.

Fig. 11 is a timing chart showing the operation of the forward synchronizer shown in Fig. 9. Regarding this embodiment, "tclk" is faster than "rclk". As shown, the phase estimator signals (even, tkoe and tkoo) reflect what phase the tclk will be on the next rising edge of rclk. Thus tkoe is shown high on the first edge of the displayed rclk because the next edge of rclk is in the inbound region of an even edge of tclk.

As shown, the most recently written scratchpad that is not in the inbound area is always sampled. The first edge of rclk samples the value "a" from the scratchpad E because the edge falls in an odd cycle of tclk. The next edge samples "b" from the scratchpad O because the rclk edge is in the indented area of tclk. The third edge samples "d" from the scratchpad O because it falls in an even number of tclk cycles. Finally, the last rclk edge samples "e" from the scratchpad E because it falls within the odd-numbered area of tclk. Please note that the value "c" is never sampled because tclk is faster than rclk. In order to determine that each value is accurately sampled once, it requires a synchronizer with flow control, as described below with respect to FIG.

Figure 12 illustrates a synchronizer 1200 with flow control in accordance with yet another embodiment. Alternatively, synchronizer 1200 can be implemented in the context of the functions and architecture of Figures 1-11. But of course, synchronizer 1200 can be implemented in any desired environment. It must also be noted that the aforementioned definitions can also be applied hereinafter.

With regard to this particular embodiment, flow control between the two clock domains can be provided. For example, a frequency and phase estimator is provided in both the transmitter and the receiver. The phase estimators can be extended to report phases in the range 0-2 (in the loop) such that they describe whether another clock domain is on an even or odd loop, and in the loop the clock is where. The biography The transmitter transmits data via a pair of scratchpads (data registers), and the receiver transmits flow control information via a pair of scratchpads (reverse thixotropy registers). Using this phase estimate, the synchronizer calculates when another clock is in the "not allowed" region in an even or odd loop. When in the inbound area of the loop (even or odd), there is an agreement to avoid sampling the register while a register is being written.

With regard to this embodiment, the flow control is implemented in the synchronizer. Synchronizer 1200 with flow control operates by alternately writing the transmitter to a pair of registers, as described above with respect to Figure 9, but the transmitter is suspended to prevent the register from being accepted by the receiver. Overwrite the scratchpad and avoid writing to the scratchpad when no valid data is available. The transmitter toggles a bit in each register (the forward thief register) to signal that new material has been written to the register. The receiver alternately thixes a pair of flow control flip-flops (reverse thixophones) to signal that the transmitter data is accepted. The receiver can delay the thixotropic-reactor because of the back pressure from the downstream process control (ie, an unprepared signal). When the receiver has thixed the corresponding flow control flip-flop, the transmitter knows that the receiver has accepted a value.

In a specific embodiment, a ready/effective process control protocol is utilized. The transmitter can selectively update a transfer register only when there is valid data available. When both registers are full, the transmitter signals that the upstream has not been prepared. When it has received a new character from the transmitter that has not been accepted by the downstream logic, as indicated by its ready input, the receiver additionally signals that the indication is valid. When the ready input is low, the receiver may not accept a valid data character from the transmitter.

In order for the clock domain to be safely crossed, the transmitter transmits the pair of registers (forward thief register) updated on the even and odd clock cycles (tae and tao, respectively). The thixotropic bit of the ta register. Similarly, the thixotropic bit of tb is transmitted via tbe and tbo, and the receiving thixotropic registers are transmitted via rae, rao, rbe, and rbo.

The receiver views these synchronized thixotropic bits to determine when it can be safely taken Sample ta or tb. At any point in time, the rtptr bit indicates whether the receiver is expecting its next data character on ta or tb. In a specific embodiment, the next character arrives at ta, and the receiver views the thixotropic bit of ta to see if a new character has arrived. If it is not in the inbound area, it directly watches tat (the thixo bit of ta). If it is in the even (odd) not allowed in-in region, it views the version of the tat synchronized on the odd (even) clock cycle tao(tae).

If you see a thixotropic change, rtptr is thixotropic. A second indicator optr drives the output multiplexer to determine which one of ta or tb is applied to the receiver output. This indicator advances when there is valid data in the current register and the "prepared" input is true, indicating that the downstream logic can accept the data. When optr advances, the corresponding receiver thixotropic bit ra or rb is thixotropic to signal that the material has been accepted. To be completely different from white space, when rtptr = optr, a rcount counter keeps a count of the characters that have arrived but have not yet been sent. This counter is incremented as rtptr advances and decreases as optr advances. When both progress, their maintenance does not change. When rcount is zero, the receiver "valid" output is set to low.

Fig. 13 is a timing chart showing the operation of the synchronizer with flow control shown in Fig. 12. With respect to this embodiment, the conveyor operates faster than the receiver. The transmitter writes "ta" with "a" on its first even cycle and writes "tb" with "b" on its first odd cycle. These writes are reacted by the thixotropic "tat" and "tbt" respectively. Since "optr" is initially zero, the "a" is propagated directly to the output and is sampled by the first even edge of rclk. After accepting "a", rptr proceeds to select "b" (as long as it is ready), and "ra" is changed to send a letter.

In this manner, the circuit causes each edge of tclk to enter a new value, and each edge of rclk leaves a new value. Note that filling in the entry queues of the transfer registers causes "tready" to go low until there is a receiver edge that causes a value to dequeue. These do not allow the inbound area to be large enough for these tready and rvalid signals to settle before their individual clock edges. In loop 5, "tready" is maintained throughout the loop. Low, because "rb" is thixotropic to accept "d" in the inbound area to guide the transmitter to apply back pressure, and the effective period of "d" and "e" is expanded to three cycle. The same thing happens in the acceptance of "f" on cycle 8.

Transmitting a signal in the inbound area of the receiving clock (eg, tat rising at the end of the transmitter cycle 2) and receiving the signal in the inbound area of the transmitting clock (eg, rb at the receiver) The transition at the end of cycle 1 is processed using the deformation of the simple forward synchronizer described above. This causes these transitions to be ignored on the dangerous edge, but can then be safely seen on the next edge of the sampling clock. Therefore, "tcount" is maintained at "2" in loops 6 and 9, even if a value has been accepted and no new value has arrived. This reception occurs in the inbound zone and may not be seen before the next cycle.

Figure 14 illustrates a phase loop 1400 showing an even and odd number of inbound regions and an area in which the even registers are selected, in accordance with another embodiment. Alternatively, the even/odd forward synchronizer phase loop 1400 can be implemented in the context of the functions and architecture of Figures 1-13. For example, phase loop 1400 can be implemented in the context of forward synchronizer 9 of FIG. But of course, phase loop 1400 can be implemented in any desired environment. Again, it must also be noted that the aforementioned definitions can also be applied hereinafter.

In the present embodiment, the transmitter phase is a real number in the range of [0, 2), which can be seen on a phase loop as shown in FIG. Odd clock cycle has a phase Φ [0,1), while the even clock cycle has Φ [1, 2). An odd (even) clock cycle ends in an odd (even) clock edge, and the signal is even during the even clock cycle (ie, when Φ [1, 2))). In order to avoid the synchronization failure, the receiver does not allow the in-in period φ in the even number. The even (E) register is not sampled during [2-x, x), and the O register is avoided during the period when the odd number is not allowed to enter [1-x, 1+x). These are not allowed to enter the inner cycle, please refer to the light gray color in this figure. The recessed inner window having a width of 2x represents the set and hold window of the sampled flip-flop. These do not allow the width of the inbound area to be enlarged in the drawing. A typical 40 nm flip-flop may have an internal window of approximately 60 ps, or only 6% of the 1 GHz clock period.

In order to comply with the rules we have chosen to safely sample the most recently written scratchpad, the selection logic is in Φ When [x, 1+x) is selected, the even (E) register is displayed as shown by the dark gray colored arc in the figure. The E register is selected as long as the phase is cleared when the phase is located at Φ=x. The E register is safely sampled during the period of the large medium gray arc shown in the figure, that is, Φ [x, 2-x) (Every place except the even number does not allow the entry area). However, it is only the newly written secure register up until Φ=1+x. When Φ When [1+x, x), the odd register (O) is the latest written secure register.

In order to determine that each value is only accurately sampled once, a synchronizer with flow control is needed, such as the FIFO synchronizer described below with reference to Figures 15-16. It has now been assumed that the receiver knows the tclk phase Φ. In practice, the receiver uses an estimate of the tclk phase p. In order to process the estimation error ε=|Φ-p|, a guard band may be added to the detection of the inaccess zone, or the phase estimation may be calculated using interval arithmetic, as described below with reference to FIGS. 7 and 9. It provides a limit on ε. When using interval arithmetic, the selection decision is done using the lower bound (lp) of the phase, as this will always select the most recently written scratchpad that can be safely sampled.

Figure 15 illustrates a FIFO synchronizer 1500 using an even/odd forward synchronizer in accordance with another embodiment. Alternatively, FIFO synchronizer 1500 can be implemented in the context of the functions and architecture of Figures 1-14. But of course, the FIFO forward synchronizer 1500 can be implemented in any desired environment. Again, it must also be noted that the aforementioned definitions can also be applied hereinafter.

It must be noted that Figures 15 and 16 describe one embodiment for measuring the relative frequencies of the two clocks and using this estimate to produce a phase estimate with error bounds. As shown in Figure 15, FIFO synchronizer 1500 is implemented using two E/O synchronizers. The FIFO uses a pair of memory, which is written synchronously, not read synchronously to hold the material being transferred. For small FIFOs, this memory is implemented as a flip-flop or latch array. Large FIFOs use a RAM or scratchpad file macro.

The FIFO memory is written, and when the input is valid (ivalid is true and filled to false), the tail indicator is incremented on the rising edge of the input clock (iclk). The head end indicator selection The bit selects the value at the head end of the FIFO and appears at the output port of the memory. The headend indicator increments on the rising edge of the output clock (oclk) when the blank is false and the output busy is false. The tail end indicator and the fill logic are in the iclk domain, and the head end indicator and the blank logic are in the oclk domain.

A pair of E/O synchronizers move the head and tail indicators between the two clock domains. A synchronizer transmits the tail end indicator to the oclk field by the iclk field, and a second synchronizer transmits the head end indicator to the iclk field by the oclk field. For the tail synchronizer, tclk=iclk and rclk=oclk, and for the headend synchronizer, tclk=oclk and rclk=iclk. Each of these synchronizers includes the logic shown in 9, and the frequency and phase estimation logic as described above.

16 illustrates a FIFO synchronizer 1600 in accordance with another embodiment in which the even and odd versions of the head and tail end indicators are retained to further reduce the FIFO latency. Alternatively, FIFO synchronizer 1600 can be implemented in the context of the functions and architecture of Figures 1-15. But of course, the FIFO synchronizer 1600 can be implemented in any desired environment. Again, it must also be noted that the aforementioned definitions can also be applied hereinafter.

The delay of a clock cycle can be avoided by maintaining the even and odd versions of the head and tail indicators, as shown in FIG. During each cycle, the input logic calculates the next end indicator and stores it in the ETail register (in even cycles) or the OTail register (in odd cycles). A multiplexer controlled by ieven (input even) selects the last written end indicator to the end signal to be used as the write address. A second multiplexer control controlled by the select signal osel from an E/O synchronizer can safely be at the end of the next output clock at the signal tailo (at the end of the oclk field) The most recently written tail register is sampled.

The signal tailo is used by the output logic to calculate the fill and calculate the next head end indicator. In operation, ose1 lags ieven, causing ieven to always select the most recently written tail metric, while osel can select an older scratchpad when the most recently written scratchpad cannot be safely sampled. In a similar manner, the output segment retains the even and odd header registers and uses a pair of multiplexers to generate the current headend and a version (head _I ) in the input clock.

The use of even/odd synchronizers provides faster speed and simplicity than conventional methods of using brute force synchronizers to transfer such head and tail indicators between clock domains. The latency of the FIFO synchronizer can be reduced because the even/odd synchronizer has an average delay of 0.5 cycles, which has a delay of S+0.5 cycles (substantially 3.5 cycles) compared to a brute force synchronizer, where S is the delay of a brute force synchronizer. The design can also be simpler because the head and tail indicators can be maintained in a binary format. With the conventional brute force synchronizer, these indicators must be Gray coded to prevent changing more than one single bit at a time.

17A-D illustrate various phase loops in accordance with other embodiments. Alternatively, the phase loops can be utilized in the context of the functions and architecture of Figures 1-16. But of course, the phase loop can be utilized in any desired environment. Again, it must also be noted that the aforementioned definitions can also be applied hereinafter.

In order to show that the synchronizer is functioning properly, (a) detection will occur often enough so that it never enters the near-simultaneous mode (and will always have an accurate phase estimate), or (b) when in near-simultaneous mode State, a test (p [-d,d]) occurs in an inaccessible area (p [-x,x]) At least S+1 cycles before.

As shown in Fig. 17A, secure plesiochronous synchronization can be achieved. For f < f _g , there is a test before an error. In this example, the phase moves slowly enough into the detection zone, and detection will occur at least A cycles before the phase enters the recessed inner window to provide time to synchronize the detection, update the phase estimate And avoid sampling the unsafe register. As also shown, this phase (diameter) exceeds eight clock cycles for a small value of f. Since f < f _g , the phase is located in the detection area (6 in the figure) exceeding the A loop before entering the recessed area.

Figure 17B shows a maximum detection range. For f _g f < 2d, a detection occurs at each N = 1 / f < A / g cycle, which is at least once per rotation around the unit cycle. As long as 2 ^{- b} < gk / 2A, since the phase limits only divergence 2 ^{- b} g / 2A between detections, the near-synchronous mode is not entered. For example, for these numbers of our example, we would have gk/2A = (0.1) (0.5) / (2) (4) = .00625, and b = 8 bits for sufficient precision. Since f < 2d, the phase cannot "jump" the detection area, and it can be ensured that at least one detection can be achieved each time the phase is rotated about the unit cycle. Because f f _g , this rotation will occur up to 1/f _g = A / g cycles. As shown in this particular embodiment, at least every nine cycles are detected.

For f 2d, f is expressed as having a defined denominator of one rational score plus an error term f=N/D±e, where D C= 1/2 d . As described below, these properties (referred to as Farey sequences) having a fractional sequence of a denominator can ensure eDC <1. In this example, one of the D points is repeated near the phase loop, which is offset by De in each D-cycle. This provides two cases with the same f<2d.

Fig. 17C shows a case in which one of D = 4 and a small residual frequency De is almost reasonable. If De < g / A, the phase offset of each cycle will be small enough that there is a test before the error, which is equivalent to the result at f < g / A. This is exemplified as D=4 in this embodiment. In fact, the restrictions here are much simpler, because each time one of the phases "groups" advances De, it passes through D cycles, as long as De<g/ A / D A loop has a test before it is allowed to enter the event, which is a loose limit.

Fig. 17D shows a case in which one of D = 4 and a large residual frequency De is almost reasonable. If g/A De<2d, a detection can be achieved in every 1/(De)<A/g cycle, so if 2 ^-b <gk/2A, a detection will occur before excessive errors are accumulated. The requirement for b here is actually the same as the above g/A f<2d case.

It is shown that for f>2d>1/C, f can always be expressed as f=N/D±e, where D C and eDC < 1. Consider the Farey sequence F(C), the sequence of rational numbers is between 0 and 1, the denominator D C. For two adjacent numbers from this combination, p/q, r/s, this combination will always be the case of r/s=(ps+1)/qs, where q, s<=C and (ps+1) ) = qr[7]. Then the distance between two adjacent rational numbers p/q and r/s is 1/qs. The value f we assign between p/q and p/q+1/q(s+q) becomes p/q, and the number is from r/s-1/s(s+q) to r/s. Then we know e 1/q(s+q), eDC (1/q(s+q))qC=C/(s+q)<1, because s+q>C due to these properties of the Farey sequence.

In other embodiments, the two free synchronizer parameters are d and k. Assuming that the inbound region 2x is one of the properties of the synchronizer flip-flop, d is selected to provide the value of the guard band, g = dx, which in turn determines the bits required for the frequency and phase estimation. The number 2 ^-b <gk/2A, so b>lg(2A/gk). Choose a small d, so a small guard band provides a more accurate phase estimate and reduces the synchronizer delay, but at the cost of requiring more bits in the frequency and phase estimators to ensure correct behavior. .

Selecting this k value provides a similar compromise. Selecting a small k provides a lower average synchronizer delay because the synchronizer will enter the near synchronous mode faster (without delay). However, choosing a small k also requires more bit precision in these estimates.

In an exemplary simulation, a Verilog RTL model of the periodic synchronizer described above can be constructed and two such synchronizers can be used to construct a flow control FIFO as illustrated in Figures 15-16. The delay lines in the phase detectors can be modeled by behavior, and all flip-flops can implement a time domain with setup and hold time checks. The Verilog simulation can be performed by fixing one clock to 1 GHz and the other clock to 2000 frequencies randomly selected between 500 Mhz and 2 GHz. In one embodiment, the phase of the 1 GHz clock is slowly swept back and forth over a range of 1600 ps, with a rate change of 1 ps every 10 cycles to ensure that all relative clock phases are tested. It is possible that timing errors will not be detected during this simulation.

FIG. 18 illustrates an exemplary system 1800 that can implement various architectures and/or functions of various prior embodiments. As shown, the provision of a system 1800 includes at least one host processor 1801 coupled to a communication bus 1802. System 1800 also includes a main memory 1804. Control logic (software) and data are stored in main memory 1804, which may be in the form of random access memory (RAM).

System 1800 also includes a graphics processor 1806 and a display 1808, ie A computer screen. In a specific embodiment, the graphics processor 1806 can include a plurality of shader modules, a fielding module, and the like. Each of the aforementioned modules can even be placed on a single semiconductor platform to form a graphics processing unit (GPU, "Graphics processing unit").

In the present description, a single semiconductor platform can represent a dedicated single semiconductor-based integrated circuit or wafer. It must be noted that the term "single semiconductor platform" can also represent a multi-chip module that has the added connectivity to simulate on-wafer operations and is implemented in a practical central processing unit (CPU) and busbar implementation. improve. Of course, a variety of modules can also be placed independently or placed in a combination of multiple semiconductor platforms depending on the needs of the user.

System 1800 can also include primary storage 1810. Secondary storage 1810 includes, for example, a hard disk drive and/or a removable storage drive that represents a floppy disk drive, tape drive, optical disk drive, and the like. The removable storage drive reads and/or writes a removable storage unit in a well known manner.

The computer program or computer control logic algorithm can be stored in main memory 1804 and/or secondary storage 1810. These computer programs, when executed, can enable system 1800 to perform a variety of functions. Memory 1804, storage 1810, and/or any other storage are all possible examples of computer readable media.

In a specific embodiment, the architecture and/or functions of the various previous figures may be implemented as at least one of the main control processor 1801, the graphics processor 1806, and the ability to simultaneously have the master processor 1801 and the graphics processor 1806. Integral circuit (not shown), a chipset (ie, an integrated circuit group designed to operate and sell units that perform related functions, etc.), and/or any other integrated circuit for this purpose In the content.

Furthermore, the architecture and/or functionality of the various previous figures can be implemented in a general purpose computer system, a circuit board system, a gaming host system for entertainment purposes, a particular application system, and/or any other desired system. For example, system 1800 can take the form of a desktop computer, a laptop computer, and/or any other type of logic. Additionally, system 1800 can take a variety of other types of devices including, but not limited to, personal digital assistant (PDA) devices, mobile telephone devices, electricity Wait and so on.

Additionally, although not shown, system 1800 can be coupled to a network for communication purposes (eg, telecommunications networks, local area networks (LANs), wireless networks, wide area networks (WANs), such as the Internet, peer-to-peer networks. Road, cable network, etc.).

As previously described in connection with Figure 14, the system explicitly ensures a secure synchronization when an accurate phase estimate is determined. In practice, the receiver uses an estimate of the tclk phase p. To process the estimated error ε=|Φ-p|, the phase estimate can be calculated using the interval arithmetic described previously with respect to Figures 7 and 9, which provides a bound on ε. When interval arithmetic is used, the selection decision between the even or odd registers is done using the lower limit of the transmit phase (lp), since this will always select the most recently written temporary memory that can be safely sampled. Device. An upper limit of the transmission phase (up) can also be calculated.

Table 9 illustrates an example of a Verilog code that can be used to update the upper and lower phase estimates (up and lp, respectively) using phase detector 540 of Figure 5E. Of course, it must be noted that the code presented in Table 9 is for illustrative purposes only and therefore cannot be considered limiting in any way.

At this sampling time, the transmission phase is known as Φ [lp,up], and if lp [x, 1+x), the even register can be safely sampled. Otherwise, the odd register can be safely sampled. However, when up-lp>1-2x, the phase estimate is no longer useful, and neither the even number nor the odd register can be safely sampled. The synchronizer is not operated in the near-simultaneous mode as described above. When up-lp>1-2x, the synchronizer is set to not select the even number or the odd-numbered register, but instead maintains at the output. The previously selected sample. When a critical number of rclk cycles have passed without the even number or the odd register being selected, then the synchronizer can operate in a near synchronous mode.

Maintaining the previous sample at the output of the synchronizer rather than converting to operate in a near-simultaneous mode, when clock jitter is increased for one or more clock cycles that produce a mediating error in the phase estimate The synchronizer is allowed to transfer signals between the transmit and receive time domains with less delay. In other words, the value of a previously sampled sample that is valid is maintained, and the phase estimator is recovered from a temporary condition that causes the phase estimates to be inaccurate. The synchronizer can track the number of receive clock cycles that have not been selected for sampling by the odd or even registers. Although the synchronizer is illustrated by an odd-numbered register and an even-numbered register, an additional register may be included to store signals corresponding to different relative phases with respect to the transmitted clock.

Figure 19A illustrates a method for determining the time at which a signal of a time domain can be safely sampled using a phase estimate, in accordance with yet another embodiment. As shown in operation 1905, a relative frequency estimate between a second clock domain (tclk) and a first clock domain (rclk) is calculated using a frequency estimate. With respect to the present description, the frequency estimate can be calculated in the manner described above with respect to operation 102 of FIG. The frequency estimator 400 shown in Figure 4 can be used to calculate the relative frequency estimate f, which indicates the frequency of the transmit clock relative to the receive clock. In another embodiment, the relative frequency estimate may be known or determined in some other manner, in this example, the relative frequency estimate is provided in step 1905.

Additionally, as shown in operation 1906, a phase estimate of the first clock domain is calculated based on the relative frequency estimate using a phase estimator. In one embodiment, as previously described with phase detectors 500, 510 and 540, and four sample phase detector 520, one phase of the first clock domain can be detected using early and late samples, which can be derived from The first clock domain of the second clock domain.

In another embodiment, the phase estimate can be calculated based on the phase detection. For example, one of the b-bit operation estimates for the phase of the first clock domain may be maintained relative to the second clock domain, as previously described by the fit corrector 530.

In another embodiment, at the time of detection, the phase of the first clock domain must be set to f(S+1), wherein an additional loop is added to S (the delay of the synchronizer) to predict This phase estimate of a cycle before it occurs. The phase of the first clock domain described above may be set to f(S+1), so the phase estimate predicts the phase of the first clock domain at the next rising edge of the second clock domain. For example, the phase estimate can encode the phase within the even and odd cycles of the first clock domain. If the phase is not detected, the phase estimate can be incremented by the relative frequency of the first clock domain during each cycle of the second clock domain to maintain an operational phase estimate.

As shown in operation 1907, it is determined whether a signal from the first clock domain can be safely sampled by the second clock domain to generate a sampled signal in the second clock. When the forward synchronizer 900 is used and up-lp > 1-2x, the phase estimate is no longer useful, and neither the even number nor the odd register can be safely sampled. Similarly, when using a synchronizer that is selected to store a plurality of registers from the signal at the different phase offsets of the first clock domain and up-lp>(N-1)- 2x, where N is the number of such registers, and the phase estimate is no longer useful.

If, based on the phase estimate, at job 1907, a time is determined during which a signal from the first clock domain has not changed such that the signal can be safely sampled by the second clock domain, then In job 1908, the signal from the first clock domain is sampled by the second clock domain to generate a sampled signal. After generating the sampled signal, the method returns to job 1906 and an updated phase estimate is calculated.

The phase estimate p is reset each time the phase detection logic indicates that a transition of tclk has occurred within one cycle of rlk. In particular, the phase estimate is reset to [-d,d], and if an even edge is detected, the even bit (msb) is set. The phase estimate then advances in time by S+1 cycles. When a transition has not occurred, the phase is incremented by f, which indicates the relative frequency of tclk for each rclk cycle. The time during which the transmission phase is within the inbound region can be more accurately detected by maintaining the upper and lower limits up and lp on the phase estimate, as shown in Table 9.

If in job 1907, based on the phase estimate, it is determined from the first time The signal in the pulse domain is changing such that the signal cannot be safely sampled by the second clock domain. In operation 1909, the sampled signal is maintained in the second clock domain. In other words, the signal from the first clock domain is not sampled, but is sampled in the second clock domain and the previously sampled signal from the first clock domain is retained.

FIG. 19B illustrates a forward synchronizer 1910 in accordance with yet another embodiment. It must be noted that in addition to a selection unit 1916, a phase detector and a phase estimator may also be included in the forward synchronizer 1910. For example, a forward synchronizer 1910 can be implemented between the system associated with the first clock domain and the system associated with the second clock domain for synchronizing the first clock domain with the second A signal between the clock domains (eg, for synchronizing samples of the signal from the second clock domain from the first clock domain). As described below, such synchronization can be performed based on the calculated phase estimate.

Alternatively, the forward synchronizer 1910 can be implemented in the context of the functions and architecture of Figures 1-2 and 4-8. But of course, the forward synchronizer 1910 can be implemented in any desired environment. It must also be noted that the aforementioned definitions can also be applied hereinafter.

With respect to this embodiment, the limitation associated with sampling a delayed version of the signal can be avoided. In order to transfer a multi-bit signal from the transmission clock domain to the reception clock domain without using flow control, the transmission clock writes a pair of registers on alternate cycles. For example, register 1912 is written on even cycles (updated at the end of the even cycle), and register 1911 is written on odd cycles (updated at the end of the odd cycle). An even input signal enables the register 1912 on even cycles and enables the register 1911 on odd cycles.

The phase estimate is used by selection unit 1916 to select the most recently written transfer register that can be "safely" sampled in the receive time domain (at the end of the current rclk cycle). The phase estimation may include the lp and the up values, and when neither the register 1912 nor the register 1911 can be "safely" sampled, the selecting unit 1916 sets the "None" output signal, and the output register 1915 is not It is enabled to sample the selected signal. The selection is based on the predicted tclk phase p at the end of the current rclk cycle. On each receive clock, if the transmit clock phase is Between e.x and o.x, a register 1911 is selected, where e represents the even-numbered loop and x is the "no-in" margin. Otherwise, the register 1912 is selected. This delay of the forward synchronizer 1910 will vary between 0.x and 1.x depending on the phase averaged 0.5+0.x.

While the present embodiment is described with respect to even and odd clock cycles and two registers, it must be noted that any number of clock cycles and registers may be utilized in other embodiments. Therefore, the clock cycle can be labeled as modulus N and N registers can be utilized. Increasing the number of scratchpads allows for very large indentation areas (eg, greater than a single UI).

As shown in Fig. 19B and with respect to the transmitter side, "tdata" is alternately written into the 1912 and 1911 registers on each cycle of tclk. On the receiver side, selection unit 1916 determines which of the two registers is to be selected to output the selected signal 1917. Selection unit 1916 can be based on this determination of the phase estimate of the transmitter clock generated by the frequency and phase estimation logic (not shown).

Figure 19C illustrates a synchronizer state diagram 1930 in accordance with the operation of the forward synchronizer shown in Figure 19B. Upon initialization, the forward synchronizer 1910 can go through a number of different states. Table 10 shows these selective states of the forward synchronizer 1910 during initialization. Of course, it must be noted that these states are presented for illustrative purposes only and should not be construed as limiting in any way.

As described with respect to Figure 19C, upon reset, the forward synchronizer 1910 enters the frequency acquisition (FA) state and initiates its counter pairing to measure the frequency of the "other" clock. During the FA state, the forward synchronizer 1910 checks to determine if there is a phase detection (phase falls into the detection region) after reaching a terminal count and the signal tc is set.

Once the frequency is obtained, the phase acquisition (PA) state is entered, and the forward synchronizer 1910 waits for a phase detection (pd). At this time, a frequency estimate f and a phase estimate p have been determined. If the signal can be safely sampled, none of them need to be cancelled and enter the tracking state (T). If the signal cannot be safely sampled, none is asserted and enters the no-select state (SN). When in state SN, if there is no phase detection (eg, a timeout occurs), the two clocks are rationally correlated (f=N/D) (or nearly rationally related) to a phase offset, so the D It is possible to hit around the phase circle and away from the detection area. In this example, the M state is entered because the phase first is guaranteed to be slow enough that it will be detected before an error occurs. When in the state SN, if there is a phase detection, none is canceled and the state T is entered.

In the states T and SN, the forward synchronizer 1910 updates the phase estimate every cycle and takes appropriate action when the forward synchronizer 1910 detects that the phase estimate is in an inbound zone. . Since the number of cycles of the last phase detection is counted in the state SN and when the number exceeds a predetermined value, the signal to is asserted, and the phase estimation is no longer reliable, and the forward synchronizer 1910 enters the near synchronization ( M) status. The number of such cycles can be reported back to a software driver.

The job in this T state is based on a fixed or near fixed frequency. For security (eg, for conditions where the frequency can change over a short period of time, such as when changing between power states), the frequency measurement circuit can operate continuously and compare its measurements to the current estimate. If the change in one clock frequency is greater than a threshold, the forward synchronizer 1910 can fall back to the brute force mode and enter the brute force state (B).

The forward synchronizer 1910 can be used only for the clocks to be periodic or when the explicit signaling is deviated from the periodic behavior (eg, an "non-periodic" signal is triggered before the clock starts unpredictably changing) Brute force mode). In this way, detection of frequencies that are too slow to change can be avoided, whereby several unsafe samples between the clock domains can be completed before detecting a change.

While various specific embodiments have been described in the foregoing, it is understood that Therefore, the breadth and scope of the preferred embodiments are not limited to any of the exemplary embodiments described above, but are to be defined only by the scope of the following claims.

Claims (20)

A method comprising: calculating a phase estimate of the first clock domain based on a relative frequency estimate between a second clock domain and a first clock domain; determining a first time based on the phase estimate a first sampling signal is generated in the second clock domain, wherein during the first time, a signal of the first clock domain is not changed, so that the signal can be secured by the second clock domain. Ground sampling; generating a first sampling signal in the second time domain during the first time period; calculating an updated phase estimate; determining a second time based on the updated phase estimate, wherein the second time During the time, the signal from the first clock domain is changing such that the signal cannot be safely sampled by the second clock domain; and during the second time period, the first time is maintained in the second time domain A sample signal. The method of claim 1, wherein the phase is estimated to include an interval of an upper limit and a lower limit. The method of claim 2, wherein the determining the second time comprises determining that a difference between the upper limit and the lower limit exceeds a threshold. The method of claim 1, wherein the phase estimate is increased during each of the plurality of cycles of the second clock domain. The method of claim 1, wherein the phase estimate encodes a phase within an even cycle and an odd cycle of the first clock domain. The method of claim 1, further comprising a cycle of the second clock domain A clock edge in the first clock domain cannot be detected, and wherein the calculation of the updated phase estimate includes increasing the phase estimate by the relative frequency estimate. The method of claim 1, further comprising detecting a clock edge in the first clock domain during a cycle of the second clock domain, and wherein calculating the updated phase estimate comprises setting the update The phase estimate is equal to a detection interval. The method of claim 1, further comprising a count that increases the cycle in which the signal cannot be safely sampled. The method of claim 8, further comprising: determining that the count of the loops exceeds a predetermined value; and operating in a near synchronous mode. The method of claim 1, wherein the updated phase estimate indicates that a clock edge is in a non-input range in the first clock domain, wherein the signal cannot be used by the second The clock domain is safely sampled. The method of claim 1, wherein calculating the phase estimate further comprises compensating for a synchronizer delay by applying an upper limit on a detection interval associated with the phase estimate. The method of claim 1, wherein the phase estimate is calculated using interval arithmetic to maintain an accurate margin of error associated with a phase associated with the phase estimate. The method of claim 1, wherein the first clock domain is continuously written to the plurality of registers on a continuous cycle, and wherein the second clock domain uses the phase estimate to select A newly written register that can be safely sampled in the second clock domain in the plurality of registers. The method of claim 13, wherein the plurality of registers comprises only two registers. The method of claim 13, wherein the alternating cycles comprise an even cycle and an odd cycle such that a first one of the plurality of registers is written during the even cycle, and the plurality of cycles A second one of the registers is written during the odd loop. The method of claim 1, wherein a FIFO synchronizer transmits a tail end indicator to an output time domain by using a complex even/odd synchronizer and transmits a head end indicator to an input time domain In the middle to achieve. For example, in the method of claim 16, wherein an even end end index, an odd end end point, an even head end index, and an odd end end index are utilized by: an even clock at an input clock. Calculating the even end end index on the loop, and calculating the odd end end index on the odd clock cycle of the input clock; and storing the calculated even end end on the even clock cycles of the input clock The indicator is in an even-numbered tail-end register, and the calculated odd-end index is stored in an odd-end register on the odd-numbered clock cycles of the input clock. A system comprising: a phase estimator configured to calculate a phase estimate of the first clock domain based on a relative frequency estimate between a second clock domain and the first clock domain, and Calculating an updated phase estimate for each cycle in the second clock domain; and a synchronizer coupled to the phase estimator and configured to: determine a first time based on the phase estimate, wherein During the first time period, a signal of the first clock domain is not changed, so that the signal can be safely sampled by the second clock domain, and a second time domain is generated during the first time period. The first sampled signal determines a second time based on the updated phase estimate, wherein during the second time, the signal from the first clock domain is changing such that the signal cannot be used by the second clock domain The sampled signal is safely sampled, and during the second time period, the first sampled signal is maintained in the second clock domain. The system of claim 18, wherein the phase is estimated to include an interval of an upper limit and a lower limit. A system of claim 18, wherein the phase estimate is increased during each of the plurality of cycles of the second clock domain.