JP2008300915A - High-speed serial communication utilizing duty ratio of clock - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve transmission and reception speeds of serial data. <P>SOLUTION: When serial data to be transmitted are configured, such that in transmission/reception of the serial data, a plurality of bits of 0 or 1 are in succession, like "00..." or "11...", the duty ratio of a synchronizing clock 121 that a transmission side 100 outputs is varied according to the number of successive bits. At this time, output data 120 from the transmission side is 0 when the data to be transmitted is "00...", or 1 when "11...". A receiving side 130 recognizes whether reception data is 0 or 1, further decides how many bits of 0 or 1 of the reception data are successive from the duty ratio of the synchronizing clock, and stores the data as many as the successive bits to a data receiving shift register 133. Consequently, the data 120 of a plurality of bits can be transmitted and received within one cycle of the synchronizing clock 121. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a serial transmission / reception system in which a data reception side receives serial data in synchronization with a synchronous clock output from a data transmission side.

In the conventional serial transmission / reception method in which the data reception side receives serial data in synchronization with the synchronous clock output from the data transmission side, reception of 1-bit data is executed for each cycle of the synchronization clock (for example, Patent Document 1). reference).
JP 2000-196576 A

  As described above, in the conventional method in which the receiving side receives serial data in synchronization with the clock output from the transmitting side, only one bit of data can be transmitted and received during one period of the synchronous clock. For this reason, in order to improve the transmission / reception speed, it is necessary to increase the frequency of the synchronous clock and transmission / reception data. As a result, the transmission / reception speed is also limited according to the capability of the terminal.

  The present invention solves the above-described problems, and realizes transmission / reception of a plurality of bits of data during one cycle of a synchronization clock in serial data transmission / reception, and improves serial data transmission / reception speed without increasing the frequency of the synchronization clock and data. It provides the technology to make it.

  The serial data transmission side sets the HIGH width of the synchronous clock to be output when the data to be transmitted has the same data having a plurality of consecutive bits such as “00...”, “11. Extends according to the number of consecutive bits. At this time, even if the HIGH width is changed, only the duty ratio of the synchronous clock is changed, and the cycle of one clock is not changed.

  The serial data receiving side can receive serial data of a plurality of bits during one period of the synchronous clock by switching the number of bits of data received according to the HIGH width of the synchronous clock.

  According to the above configuration, the transmission / reception speed of serial data can be improved without increasing the frequency of the synchronous clock.

  Embodiments 1 and 2 of the present invention will be described with reference to the drawings.

Embodiment 1
In the first embodiment, both the serial data transmission side circuit and the reception side circuit have a shift register of N (N is an arbitrary integer of 2 or more) bits, and a plurality of bits of data are stored in one cycle of the synchronous clock. This is a form for carrying out the exchange.

  The first embodiment will be described with reference to FIGS. 1 to 6 regarding the configurations of the data transmission circuit and the data reception circuit, and FIGS. 7 to 10 regarding the detailed operation of serial data transmission / reception.

  FIG. 1 is a block diagram showing a configuration of a serial transmission / reception system according to the present invention, which includes a data transmission circuit 100 and a data reception circuit 130.

  The data transmission circuit 100 shown in FIG. 1 includes a data transmission shift register 101, a transmission data supply unit 102, a transmission status confirmation shift register 103, an edge detection circuit 104, a clock 1 cycle counter 105, and a synchronous clock output switching. The circuit 106, the data transmission terminal 107, and the synchronous clock transmission terminal 108 are configured.

  The data transmission shift register 101 is a circuit for storing serial transmission data and transmitting it in synchronization with the internal clock 118 of the transmission circuit. As shown in FIG. 2, N selectors 200 and N flip-flops are used. 201. “LH” of each flip-flop 201 is a hold terminal. When the value of the transmission data is switched or the stored transmission data is completely output, the synchronous clock output switching signal 114 becomes LOW, and the data shift operation is interrupted. After the transmission of all the bits of the stored data is completed, the serial transmission data update signal 116 becomes HIGH, and the next transmission data is supplied from the transmission data supply unit 102 by N bits.

  The transmission data supply unit 102 is a circuit for supplying the next transmission data when serial transmission / reception starts and when transmission of N-bit data stored in the data transmission shift register 101 is completed. When transmission of N-bit data stored in the data transmission shift register 101 is completed and the transmission data update signal 116 is switched to HIGH, the transmission supply data 109 is switched to N-bit serial transmission data to be output next.

  The transmission status confirmation shift register 103 is a circuit for notifying the completion of transmission of all the bits stored in the data transmission shift register 101, and operates in synchronization with the transmission circuit internal clock 118 as shown in FIG. N flip-flops 300, a NOR gate 301, an AND gate 302, an inverter 303, and another flip-flop 304 that operates in synchronization with an inverted signal of the transmission circuit internal clock 118. The shift register 103 performs a shift operation at the same timing as the data transmission shift register 101. When transmission of N-bit serial data is completed, the supply data switching signal 113 is set to HIGH to notify the completion of transmission. After the transmission is completed, the transmission data update signal 116 is set to HIGH at the end of the synchronous clock cycle, thereby storing new transmission data in the data transmission shift register 101 and clearing the shift register 103, and the next N bits. To enable data transmission.

  The edge detection circuit 104 detects switching of the value of transmission data, switches the transmission data edge detection signal 112 to HIGH at the time of detection, interrupts the shift operation of the two shift registers 101 and 103, and sets the transmission / reception synchronization clock 121 to LOW. It is a circuit for switching to. After all bit data transmission of the data transmission shift register 101 is completed, switching of the input value to the shift register 101 when storing the next N bits of transmission data from the transmission data supply unit 102 is erroneously recognized as a transmission data switching edge. In order to prevent this, when the transmission data update signal 116 is HIGH, the transmission data edge detection signal 112 is not switched to HIGH.

  The clock 1 cycle counter 105 is a counter that can set an arbitrary count cycle for setting the frequency of the transmission synchronization clock 117 and operates in synchronization with the transmission circuit internal clock 118. When the count value reaches 0, transmission / reception of serial data is started. When the count value reaches the set value, the end of one cycle of the synchronous clock is notified by switching the clock one cycle count end signal 115 to HIGH.

  The synchronous clock output switching circuit 106 is a circuit for switching the HIGH width of the transmission synchronous clock 117 in accordance with the number of bits of transmission data, and is synchronized with the selector 400 and the transmission circuit internal clock 118 as shown in FIG. And a flip-flop 401 that operates.

  From the data transmission terminal 107, serial data stored in the data transmission shift register 101 is transmitted to the data reception circuit 130 as transmission / reception data 120.

  A transmission / reception synchronization clock 121 is transmitted from the synchronization clock transmission terminal 108 to the data reception circuit 130.

  On the other hand, the data reception circuit 130 includes a data reception terminal 131, a synchronous clock reception terminal 132, a data reception shift register 133, a reception status confirmation shift register 134, and a reception data storage unit 135, as shown in FIG. It is configured.

  The serial transmission data transmitted from the data transmission circuit 100 is received at the data reception terminal 131. In addition, the synchronous clock receiving terminal 132 receives the synchronous clock.

  The data reception shift register 133 is a circuit for receiving serial data from the data reception terminal 131 in synchronization with the reception circuit internal clock 140 when the reception synchronization clock 137 is HIGH, as shown in FIG. And N flip-flops 500 that operate in synchronization with the internal clock 140 of the receiving circuit. When data is stored in all bits of the data reception shift register 133, all the stored data bits are stored in the reception data storage unit 135.

  The reception status check shift register 134 is a circuit for notifying the reception data storage unit 135 that the data reception shift register 133 has completed reception of N-bit data. As shown in FIG. The flip-flop 600 includes N flip-flops 600 that operate in synchronization with the circuit internal clock 140, and a flip-flop 601 for resetting the N flip-flops 600. The shift register 134 performs a shift operation at the same timing as the data reception shift register 133, and when reception of the N-bit serial data is completed, the data storage permission signal 139 is switched to HIGH, whereby the data reception shift register 133 Data is stored in the reception data storage unit 135.

  The reception data storage unit 135 is a circuit for storing the serial data received by the data reception shift register 133 and using it according to the application. When the data storage permission signal 139 becomes HIGH, the received data is stored.

From here, the detailed operation of the circuit according to the first embodiment will be described with reference to a circuit diagram and a timing chart. As an operation to explain,
A. Serial transmission / reception operation [1] Start transmission of data of “11100...
[2] After transmitting 3 bits of HIGH data, detect switching of transmission data and interrupt transmission / reception:
[3] After one cycle of the synchronous clock ends, the next data transmission of “00.
B. Operation when N-bit data transmission / reception is completed [1] Of the N-bit data initially stored in the data transmission shift register 101, only 2-bit “00” data remains untransmitted:
[2] Start 2-bit transmission of LOW data in this state:
[3] After completion of 2-bit transmission, the next N-bit data is stored in the data transmission shift register 101 and transmission is resumed.
The two typical patterns are targeted.

As a prerequisite for the explanation, the setting of each parameter is
The data transmission shift register 101, the transmission status confirmation shift register 103, the data reception shift register 133, and the reception status confirmation shift register 134 are 8 bits (N = 8),
One period of the synchronous clock is 10 periods of the transmission circuit internal clock 118 and the reception circuit internal clock 140.

  With respect to the above-described operation A, the operation of the data transmission circuit 100 will be described with reference to FIG. 7, and the operation of the data reception circuit 130 will be described with reference to FIG.

  In the data transmission circuit 100, one cycle before the transmission circuit internal clock 118 prior to transmission start (time t1), the synchronous clock output switching signal 114 is HIGH, and the data transmission shift register 101 and the transmission status confirmation shift register 103 are A shift operation is executed in synchronization with the transmission circuit internal clock 118. At the same time as the count value of the clock 1 cycle counter 105 becomes “0”, the transmission data 110 is HIGH (because the data to be transmitted is “111”), and the transmission synchronization clock 117 is also switched to HIGH to start transmission / reception of serial data ( Time t1). After the HIGH data is output by 2 bits, the transmission data edge detection signal 111 is switched to LOW and the switching edge is detected by the edge detection circuit 104. Therefore, the transmission data edge detection signal 112 becomes HIGH, thereby outputting a synchronous clock. The switching signal 114 is negated (time t2). As a result, the shift operation of the data transmission shift register 101 and the transmission status confirmation shift register 103 is interrupted, and the transmission data 110 is held HIGH. On the other hand, since the output value of the transmission synchronous clock 117 is switched by the synchronous clock output switching signal 114, it is synchronized with the positive edge of the next internal clock 118 to which the transmission data edge detection signal 112 is asserted, that is, three cycles of the internal clock 118. After maintaining HIGH for the number of minutes, it switches to LOW (time t3).

  When the count value of the clock 1 cycle counter 105 reaches the upper limit (set to 9 in this example because one cycle width of the synchronous clock is 10 cycles of the internal clock 118) (time t4), the clock 1 cycle counter 105 The one cycle count end signal 115 is set to HIGH only for one cycle of the internal clock 118. In response to the assertion of the clock 1 cycle count end signal 115, the transmission data edge detection signal 112 becomes LOW, and as a result, the synchronous clock output switching signal 114 becomes HIGH. Is started after the count value becomes zero (time t5).

  In the data reception circuit 130, the reception synchronization clock 137 is used as the LH signal of the data reception shift register 133 and the reception status confirmation shift register 134. Therefore, when the reception synchronization clock 137 is HIGH, the data reception shift register 133 is the reception circuit. The reception data is stored in synchronization with the internal clock 140, and the reception status confirmation shift register 134 stores HIGH. In this example, since the HIGH width of the synchronous clock is three cycles of the internal clock 140, data “111” for three bits is stored in the data reception shift register 133, and three flip-flops of the reception status confirmation shift register 134 are stored. The stored value of the group 600 is switched from LOW to HIGH. In this case, since only 3 bits of data are stored in the data reception shift register 133, the next data transmission / reception is performed without storing the data in the reception data storage unit 135. That is, the data storage permission signal 139 holds LOW.

  Next, regarding the above-described operation B, the operation of the data transmission circuit 100 will be described with reference to FIG. 9, and the operation of the data reception circuit 130 will be described with reference to FIG.

  In the data transmission circuit 100, when HIGH is stored in all the flip-flops 300 of the transmission status confirmation shift register 103, the supply data switching signal 113 becomes HIGH (time t11). As a result, the synchronous clock output switching signal 114 becomes LOW and the shift operation is interrupted, so that the transmission data 110 is held LOW. The transmission synchronization clock 117 is switched from HIGH to LOW at the next positive edge of the transmission circuit internal clock 118 (time t12). When the count value of the clock 1 cycle counter 105 becomes “9” while the supply data switching signal 113 is HIGH, the transmission data update signal 116 becomes HIGH. As a result, the transmission supply data 109 from the transmission data supply unit 102 is changed. Then, the data is switched to the next data to be transmitted (time t13). Further, when the transmission data update signal 116 becomes HIGH, the transmission supply data 109 is stored in the data transmission shift register 101 and the transmission status confirmation shift register 103 is cleared, and the next data transmission can be performed (time). t14).

  In the data reception circuit 130, when the 2-bit LOW data is received from the data transmission circuit 100, the storage of the reception data in all the flip-flops 500 of the data reception shift register 133 is completed. At this time, HIGH is also stored in all the flip-flops 600 in the reception status confirmation shift register 134, and as a result, the data storage permission signal 139 becomes HIGH (time t12). At this timing, all 8-bit data is stored in the reception data storage unit 135, and the reception status confirmation shift register 134 is cleared after one cycle of the internal clock 140, so that the next 8-bit data can be received. .

<< Embodiment 2 >>
The second embodiment is different from the first embodiment.
(1) After the start of serial transmission / reception, test data and test synchronous clock are transmitted / received first, and the difference between the timing at which the received data is switched in the data receiving circuit and the rising timing of the synchronous clock is the number of cycles of the internal clock of the receiving circuit. A function that counts whether it corresponds to minutes, and corrects a timing shift that occurs when transmitting / receiving actual data and a synchronous clock based on the result, and
(2) After starting serial transmission / reception, the test data and the test synchronous clock are transmitted / received first to recognize the decrease in the HIGH width of the synchronous clock due to the delay added when passing through the terminal. A function for correcting a decrease in HIGH width in actual transmission / reception of the synchronous clock based on the result,
(3) A function for preventing the disappearance of the HIGH period of the synchronous clock, which may occur due to a delay when passing through the terminal, by adding an offset to the HIGH width of the synchronous clock;
(4) A function of removing an increase in the HIGH period due to the offset added in (3) above on the transmission side;
(5) A function of preventing the disappearance of the LOW period of the synchronous clock, which may occur due to a delay when passing through the terminal, by setting an upper limit of the HIGH width of the synchronous clock;
(6) After transmission / reception of N bits is completed, the transmission side provides a transmission / reception error reception period. During this period, the data transmission terminal is turned to the input, and data reception is not performed because N-bit transmission / reception has not been executed normally. When the data transmission circuit recognizes that N bits of data have been transmitted even though the circuit has not received N bits of data, or when N bits of data are stored in the data reception shift register Regardless of whether the data transmission circuit is transmitting more data, a function that transmits a transmission / reception error signal from the data reception circuit to the data transmission circuit and re-executes transmission / reception of data that failed to be transmitted / received is added. It is a form.

  The second embodiment will be described with reference to FIGS. 11 to 16 regarding the data transmission circuit, FIGS. 17 to 24 regarding the data reception circuit, and FIGS. 25 to 32 regarding the detailed operation of serial data transmission / reception. Do.

  FIG. 11 is a block diagram showing a configuration of a data transmission circuit according to the second embodiment of the present invention. As shown in FIG. 11, the data transmission circuit 1100 includes a data transmission shift register 1101, a transmission data supply unit 1102, a transmission status confirmation shift register 1103, an edge detection circuit 1104, a clock 1 cycle counter 1105, and a synchronous clock. The output switching circuit 1106, serial data transmission circuit 1107, synchronous clock transmission terminal 1108, offset addition circuit 1109, clock 1 cycle counter (2) 1110, and clock HIGH width counter 1111 are included.

  As shown in FIG. 12, the data transmission shift register 1101 includes N selectors 1200 and N flip-flops 1201. The shift register 1101 is a circuit for receiving transmission supply data 1112 from the transmission data supply unit 1102 and transmitting it from the serial data transmission circuit 1107 in synchronization with the transmission circuit internal clock 1124. Whether the value of transmission data is switched, transmission of N bits of transmission data is completed, or the HIGH width of the transmission / reception synchronization clock 1131 transmitted from the synchronization clock transmission terminal 1108 is set to the upper limit value set by the clock HIGH width counter 1111 When it reaches, the shift register operation permission signal 1123 becomes LOW, the shift operation is interrupted, and the transmission synchronization clock 1120 is switched to LOW. When transmission of all the bits of the stored data is completed and the transmission / reception error acceptance period ends, the transmission data update signal 1118 becomes HIGH, and the transmission supply data 1112 is supplied from the transmission data supply unit 1102.

  The transmission data supply unit 1102 is a circuit for supplying transmission data to the data transmission shift register 1101 at the start of serial transmission / reception and when transmission of N-bit data stored in the data transmission shift register 1101 is completed. When N-bit data in the data transmission shift register 1101 is normally transmitted, the transmission supply data 1112 is switched to the next N-bit transmission data to be output and output to the data transmission shift register 1101. When transmission / reception is not normally performed for the transmitted N bits and the transmission / reception error signal 1121 is transmitted from the reception side, the transmission supply data 1112 is switched again to the N-bit data transmitted immediately before, and the data transmission shift register 1101 is switched. The transmission / reception that has not been normally executed is executed again.

  The transmission status confirmation shift register 1103 is a circuit for notifying the completion of transmission of the N-bit data stored in the data transmission shift register 1101, and operates in synchronization with the transmission circuit internal clock 1124 as shown in FIG. N flip-flops 1300 and a NOR gate 1301 are configured. The shift register 1103 performs a shift operation at the same timing as the data transmission shift register 1101. When transmission of all bits of serial data is completed, the N-bit data transmission completion signal 1116 is set to HIGH to notify transmission completion. . When the transmission / reception error acceptance period ends after the completion of N-bit data transmission, the shift register 1103 is cleared, and the next data can be transmitted / received.

  The edge detection circuit 1104 is a circuit for detecting a change in the value of transmission data, switching the transmission data edge detection signal 1115 to HIGH at the time of detection, and interrupting transmission / reception of data. In addition, after all bit data transmission of the data transmission shift register 1101 is completed, switching of the input value to the shift register 1101 when storing the next N-bit transmission data from the transmission data supply unit 1102 is performed at the time of data transmission. In order to prevent erroneous recognition as a data switching edge, the transmission data edge detection signal 1115 is not switched to HIGH when the transmission data update signal 1118 is HIGH.

  The clock 1 cycle counter 1105 is a counter that operates in synchronization with the transmission circuit internal clock 1124 and can arbitrarily set the count cycle for setting the frequency of the transmission synchronization clock 1120. When the count value becomes “0”, transmission / reception of serial data is started. When the count value reaches the set value, the clock 1 cycle count end signal 1117 is switched to HIGH to notify the end of one cycle of the synchronous clock.

  The synchronous clock output switching circuit 1106 is a circuit for switching the HIGH width of the transmission synchronous clock 1120 according to the number of bits of transmission data, and is synchronized with the selector 1400 and the transmission circuit internal clock 1124 as shown in FIG. And a flip-flop 1401 that operates in the same manner. Note that an offset can be arbitrarily added to the transmission synchronization clock 1120 by the offset addition circuit 1109. When the offset is added, the offset is removed from the HIGH width when the synchronization clock is used on the reception side. To do.

  The serial data transmission circuit 1107 is a circuit for transmitting serial data and receiving a transmission / reception error signal 1121 transmitted from the receiving side to the data transmission circuit 1100. As shown in FIG. 1500, an inverter 1501, a tristate buffer 1502, an AND gate 1503, and a serial data transmission terminal 1510. Although it is suitable for output during data transmission, it is suitable for input in order to accept the transmission / reception error signal 1121 during the transmission / reception error reception period after completion of transmission of all N bits of data in the data transmission shift register 1101.

  The synchronous clock transmission terminal 1108 is a terminal for transmitting the transmission / reception synchronous clock 1131 and always faces the output.

  The offset adding circuit 1109 is a circuit for preventing the disappearance of the HIGH period due to the influence of the delay when passing through the terminal by adding an offset to the HIGH width of the synchronous clock. As shown in FIG. M + 1) flip-flops 1600, M OR gates 1601, and one selector 1602. The offset value can be set arbitrarily, and the HIGH width of the synchronous clock can be expanded by (offset setting value) × (one cycle width of the internal clock).

  The clock 1 cycle counter (2) 1110 executes the count operation for one cycle of the transmission synchronization clock 1120 after the end of transmission of the N-bit data, and the data and synchronization clock are used as the reception period of the transmission / reception error signal 1121 during the count period. This is a circuit for controlling the data transmission circuit 1100 so as not to transmit. The same value as the clock 1 cycle counter 1105 is set as the upper limit value of the counter 1110. When the count value reaches the upper limit value, the transmission data update signal 1118 is switched to HIGH, thereby switching to the output of the serial data transmission circuit 1107 and clearing the transmission status confirmation shift register 1103.

  The clock HIGH width counter 1111 counts the HIGH width of the synchronous clock, and delays when passing through the terminal by interrupting the transmission of data and clock when the HIGH width reaches the upper limit value of the predetermined HIGH width. This is a circuit for preventing the disappearance of the LOW period of the synchronous clock due to the influence of. The upper limit value of the HIGH width can be arbitrarily set, and the HIGH width of the clock to be transmitted can be limited to (HIGH width upper limit value) × (one cycle width of the internal clock) or less.

  As shown in FIG. 17, the data reception circuit 1700 is synchronized with the serial data reception circuit 1701, the synchronous clock reception terminal 1702, the data reception shift register 1703, the reception status check shift register 1704, and the reception data storage unit 1705. A clock HIGH width correction circuit 1706, a synchronous clock offset removal circuit 1707, a reception data offset removal circuit 1708, a synchronous clock LOW width counter 1709, and a reception signal switching timing correction circuit 1722 are configured.

  The serial data receiving circuit 1701 is a circuit for receiving serial data and transmitting a transmission / reception error signal 1713. As shown in FIG. 18, an offset adding circuit 1800, a tristate buffer 1801, an inverter 1802, An AND gate 1803 and a serial data receiving terminal 1810 are included. It is suitable for input when data is received, but when N-bit transmission / reception is not normally executed, it is directed to output and a transmission / reception error signal 1713 is transmitted. At this time, the transmission / reception error signal 1713 is added with an offset having the same value as the offset added to the transmission synchronization clock 1120 by the data transmission circuit 1100 of FIG. This prevents the transmission / reception error signal 1713 from being lost.

  The synchronous clock receiving terminal 1702 is always directed to the input and is a terminal for receiving the transmission / reception synchronous clock 1131.

  The data reception shift register 1703 is a circuit for receiving serial reception data (0) 1719 from the serial data reception circuit 1701 in synchronization with the reception circuit internal clock 1723 when the reception synchronization clock (0) 1720 is HIGH. There are N flip-flops 1900 as shown in FIG. When data is stored in all bits of the data reception shift register 1703, all stored data bits are stored in the reception data storage unit 1705.

  The reception status confirmation shift register 1704 is a circuit for notifying the reception data storage unit 1705 that the data reception shift register 1703 has completed reception of N-bit data. As shown in FIG. N flip-flops 2000 operating in synchronization with the internal clock 1723, the other two flip-flops 2001, 2013, inverters 2010, 2016, AND gates 2011, 2012, 2014, 2017, OR gate 2015, It is comprised by. The shift register 1704 executes a shift operation at the same timing as the data reception shift register 1703, and when reception of N-bit serial data is completed, the data storage permission signal 1718 is switched to HIGH to thereby change the data reception shift register 1703. Is stored in the received data storage unit 1705. In addition, when N-bit data is already stored in the data reception shift register 1703, data is continuously transmitted from the transmission side, or no N-bit data is stored in the data reception shift register 1703. However, when the transmission side finishes N-bit data transmission and enters the transmission / reception error acceptance state, it is determined that transmission / reception of N-bit data has not been performed normally, and the transmission / reception error signal 1713 is transmitted to the serial data reception circuit 1701. Supply.

  When the HIGH width of the transmission / reception synchronization clock 1131 decreases due to the delay when passing through the terminal, the synchronous clock HIGH width correction circuit 1706 expands the HIGH width by the reduced amount to increase the HIGH width during transmission. FIG. 21 shows a circuit for restoration, and includes (M + 1) flip-flops 2100, M OR gates 2101, one selector 2102, and a reception synchronization clock HIGH width counter 2103, as shown in FIG. Is done. First, the transmission side outputs a test synchronous clock, and a decrease in the HIGH width of the synchronization clock on the reception side is counted by the reception synchronization clock HIGH width counter 2103, and the HIGH width is expanded by the correction circuit 1706 by the decrease. To do.

  The reception synchronization clock HIGH width counter 2103 has a HIGH width of the reception synchronization clock (1) 1714 which is a synchronization clock that has passed through the reception signal switching timing correction circuit 1722 when an initial setting permission signal (0) 2410 described later is LOW. The number of cycles of the reception circuit internal clock 1723 is counted. Also, the reception synchronization clock (2) 1715 indicates the count result, that is, the reception-side circuit internal clock count of the reception synchronization clock HIGH width 2105 corresponding to the decrease from the HIGH width of the synchronization clock actually input from the synchronization clock reception terminal 1702. By using the selector 2102 as the output switching select signal, the reception synchronization clock (2) 1715 can be a synchronization clock in which the HIGH width at the time of transmission is restored.

  The synchronous clock offset removal circuit 1707 is a circuit for removing the influence of the offset added on the transmission side from the HIGH width of the reception synchronous clock (0) 1720. As shown in FIG. Flip-flop 2200, M AND gates 2201, one selector 2202, one inverter 2203, and one AND gate 2204.

  The reception data offset removal circuit 1708 is a circuit for aligning the timing of switching values between the synchronization clock that has passed through the synchronization clock offset removal circuit 1707 and the reception data. As shown in FIG. Flip-flop 2300 and one selector 2301. When passing through the synchronous clock offset removing circuit 1707, the synchronous clock is delayed by the offset, and as a result, the positive edge of the synchronous clock is shifted from the timing of switching the value of the received data. Thus, the timing is also adjusted by adding a delay corresponding to the offset to the received data.

  The synchronous clock LOW width counter 1709 is a circuit that counts the LOW width of the synchronous clock. The data transmission circuit 1100 in FIG. 11 does not transmit data and a synchronization clock to accept a transmission / reception error signal 1121 during the next one synchronization clock after the end of N-bit data transmission. For this reason, when the transmission side finishes transmitting N-bit data, the transmission / reception synchronization clock 1131 is held LOW for at least one cycle of the transmission / reception synchronization clock 1131. The counter 1709 is intended to confirm the end of transmission of N-bit data on the transmission side by counting the LOW width of the synchronous clock.

  The received signal switching timing correction circuit 1722, as shown in FIG. (Y + 1) flip-flops 2403, data positive edge detector 2405, synchronous clock positive edge detector 2406, clock delay counter 2407, data delay counter 2408, and initial setting permission signal (0) 2410 A flip-flop 2420 for generation, inverters 2421 and 2422, AND gates 2423 and 2424, and selectors 2425 and 2426 are included. When the first test data and the test synchronous clock are transmitted and received, the circuit 1722 counts the deviation between the positive edge of the data on the receiving side and the positive edge of the synchronous clock with the internal clock 1723 of the receiver circuit, When the positive edge of the clock is detected first, the data delay counter 2408 is set to the reception synchronization clock (0_2) 2416. When the positive edge of the received data is detected first, the clock delay counter 2407 is set to the serial reception data ( 0_2) This is a circuit for preventing the occurrence of a data reception error in subsequent transmission / reception by initializing the data reception circuit 1700 to add a delay to the 2415 by the amount of deviation. The initial setting is executed when the initial setting permission signal (0) 2410 is the initial value LOW, and the first falling edge of the reception synchronization clock (0) 1720 occurs in the initial setting permission signal (0) 2410. Then, since it becomes HIGH, the initial setting is not changed until serial transmission / reception is completed.

  The data positive edge detector 2405, the synchronous clock positive edge detector 2406, the clock delay counter 2407, and the data delay counter 2408 shown in FIG. 24 are respectively positive edges of the serial reception data (0_2) 2415 at the time of initial setting. Used to count the positive edge delay of the reception synchronization clock (0_2) 2416 with respect to the positive edge of the serial reception data (0_2) 2415 relative to the positive edge of the reception synchronization clock (0_2) 2416 with the internal clock 1723 of the reception circuit. It is.

  The data positive edge detector 2405 is a circuit that sets the data positive edge detection signal 2411 to HIGH when the positive edge of the serial reception data (0_2) 2415 that is reception data that has passed through the synchronizer 2400 is detected. Once the data positive edge detection signal 2411 becomes HIGH, it remains HIGH until the serial transmission / reception is completed.

  The data delay counter 2408 counts how many periods of the reception circuit internal clock 1723 the delay of the reception timing of the serial reception data (0_2) 2415 relative to the reception timing of the reception synchronization clock (0_2) 2416 corresponds to. The counter operates in synchronization with the internal clock 1723 of the receiving circuit while the data delay count enable 2414 is asserted, and ends when the clock delay count enable 2413 is asserted.

  The synchronous clock positive edge detector 2406 and the data delay counter 2407 are circuits that execute the same operation with respect to the synchronous clock, respectively.

  The positive edge delay or the reception synchronization clock of the reception synchronization clock (0_2) 2416 with respect to the positive edge of the serial reception data (0_2) 2415 in the data reception circuit 1700 confirmed by the both positive edge detectors 2405 and 2406 and the both delay counters 2407 and 2408 ( 0_2) Reflecting the delay of the positive edge of the serial reception data (0_2) 2415 with respect to the positive edge of 2416 in the clock delay count value 2417 or the data delay count value 2418, and adding a delay only to the one where the positive edge is detected first, It is possible to generate serial reception data (1) 1710 and reception synchronization clock (1) 1714, which are reception data and synchronization clock whose timing has been adjusted.

From here, the detailed operation of the circuit according to the second embodiment will be described. As an operation to explain,
C. At the beginning of serial transmission / reception, test data and a test synchronization clock are transmitted / received. The delay of the positive edge of the serial reception data (0_2) 2415 with respect to the signal is counted by the internal clock 1723 of the reception circuit, the operation of setting the reception signal switching timing correction circuit 1722 based on the result, and the reduction of the HIGH width of the test synchronous clock Minute is counted by the reception circuit internal clock 1723, and the synchronous clock HIGH width correction circuit 1706 is set based on the result.
D. Serial transmission / reception operation [1] Start transmission of data of “11100...
[2] After transmitting 3 bits of HIGH data, detect switching of transmission data and interrupt transmission / reception:
[3] After one cycle of the synchronous clock ends, the next data transmission of “00.
E. Operation when N-bit data transmission / reception is completed [1] Of the N-bit data initially stored in the data transmission shift register 1101, only 2-bit “00” data remains untransmitted:
[2] Start 2-bit transmission of LOW data in this state:
[3] After completion of 2-bit transmission, transition to the transmission / reception error acceptance state:
[4] Store next N-bit data in data transmission shift register 1101 and resume transmission.
The three typical patterns are targeted.

As a prerequisite for the explanation, the setting of each parameter is
-Eight flip-flops 1201 of the data transmission shift register 1101 (N = 8)
-One cycle width of the transmission / reception synchronization clock 1131 is 10 cycles of the internal clocks 1124, 1723-Offset added to the HIGH width of the transmission / reception synchronization clock 1131 is two cycles of the internal clocks 1124, 1723-HIGH width of the transmission / reception synchronization clock 1131 Is 6 cycles of internal clocks 1124 and 1723. The first test data to be transmitted and received is HIGH, and the HIGH width of the test synchronous clock is 5 cycles of internal clocks 1124 and 1723.

  The circuit operation on the reception side in the case of operation C of the second embodiment will be described with reference to FIG. Here, serial reception data (0) 1719 is test data, and reception synchronization clock (0) 1720 is a test synchronization clock.

  Now, the reception timing of the serial reception data (0) 1719 and the reception synchronization clock (0) 1720 is the timing as shown in FIG. 25 (before and after the time t21), and the HIGH width of the reception synchronization clock (0) 1720 is further increased. The circuit operation will be described on the assumption that the receiving circuit internal clock 1723 is reduced by about one cycle (hatching in FIG. 25) due to the influence of the delay that occurs when passing through the terminals.

  In this case, after the serial reception data (0) 1719 and the reception synchronization clock (0) 1720 have passed through the synchronizers 2400 and 2402, respectively, the positive edge (time t23) of the serial reception data (0_2) 2415 is the reception synchronization clock (0_2) 2416. Is delayed by one cycle of the receiving circuit internal clock 1723, the count value of the clock delay counter 2407 remains “0”, and the count value of the data delay counter 2408 is “1”. (Time t23). These results are reflected as select signals of the selector 2425 for generating the serial reception data (1) 1710 and the selector 2426 for generating the reception synchronization clock (1) 1714, respectively. In actual transmission / reception, the serial reception data (1 ) 1710 is the serial reception data (0_2) 2415 as it is, and the reception synchronization clock (1) 1714 is received by hitting the reception synchronization clock (0_2) 2416 with the reception circuit internal clock 1723 once. The timing of the positive edge of the data after passing through the signal switching timing correction circuit 1722 and the positive edge of the synchronous clock can be made uniform.

  Further, the fact that the HIGH width of the reception synchronization clock (1) 1714 is reduced by one period of the reception circuit internal clock 1723 during transmission / reception of the test data and the test synchronization clock indicates that the reception synchronization clock HIGH width counter 2103 counts ( (Reception synchronization clock HIGH width) 2105, and in actual transmission / reception, the synchronization clock HIGH width correction circuit 1706 determines the HIGH width of the reception synchronization clock (1) 1714 for one period of the reception circuit internal clock 1723 (from time t26 to time t27). By extending, it is possible to correct the decrease in the HIGH width in the reception synchronous clock (0) 1720 due to the influence of the delay when passing through the terminal.

  The above circuit setting operation is executed when the initial setting permission signal (0) 2410 is LOW (until time t26). Since the initial setting permission signal (0) 2410 becomes HIGH after the transmission / reception of the test data and the test synchronous clock is completed, the setting is not changed in the subsequent serial transmission / reception.

  Next, regarding the operation D of the second embodiment, the operation of the data transmission circuit 1100 will be described with reference to FIGS. 26 and 27, and the operation of the data reception circuit 1700 will be described with reference to FIG.

  In the data transmission circuit 1100, one cycle before the transmission circuit internal clock 1124 prior to the start of transmission (time t31), the shift register operation permission signal 1123 is HIGH, and the count value of the clock one cycle counter 1105 is set to “0”. At the same time (time t31), the transmission data is HIGH (because the data to be transmitted is “111”), the transmission synchronization clock 1120 is also switched to HIGH, and transmission / reception of serial data is started. The transmission status confirmation shift register 1103 also starts a shift operation at the same time. Then, after 2 bits of HIGH data are output, the transmission data edge detection signal 1114 switches to LOW, the switching edge is detected by the edge detection circuit 1104, and the transmission data edge detection signal 1115 is set to HIGH (time t32). As a result, the shift register operation permission signal 1123 becomes LOW, the shift operations of the data transmission shift register 1101 and the transmission status confirmation shift register 1103 are interrupted, and the serial transmission data 1113 is held HIGH. On the other hand, since the transmission synchronization clock 1120 is offset by two periods of the transmission circuit internal clock 1124 by the offset addition circuit 1109, the next transmission circuit internal clock 1124 rises even if the shift register operation permission signal 1123 becomes LOW. In this case, the HIGH width corresponding to five cycles of the internal clock 1124 of the transmission circuit, which is obtained by adding the offset “2” to the number of bits “3” of the data “111” to be transmitted this time, is maintained (from time t31). Until time t33). While the shift register operation is interrupted, the clock 1 cycle counter 1105 continues to operate, and when the counter value reaches the upper limit “9” (time t34), the clock 1 cycle count ends as a signal to end one cycle of the synchronous clock. The signal 1117 is set to HIGH. In response to this, the edge detection circuit 1104 switches the transmission data edge detection signal 1115 to LOW, so that the shift registers 1101 and 1103 again start the shift operation from the next rising edge (time t35) of the transmission circuit internal clock 1124, and the data And transmission of the synchronous clock is started.

  With respect to the operation of the data transmission circuit 1100 described above, the synchronization clock HIGH width corresponds to five cycles of the transmission circuit internal clock 1124, and the above-described upper limit value of the synchronization clock HIGH width (six cycles of the transmission circuit internal clock 1124) FIG. 27 shows an operation when the synchronous clock HIGH width reaches the upper limit value, although it is assumed that it has not reached. The difference in conditions between FIG. 26 and FIG. 27 is that the former has an upper limit of the synchronous clock HIGH width corresponding to six cycles of the internal clock 1124, whereas the latter is set to four cycles of the internal clock 1124. That is. In the condition of FIG. 26, the timing of interruption of the shift operation of the shift registers 1101 and 1103 is switching from “1” to “0” of the transmission data, so that the serial transmission data 1113 is changed at the first transmission. High, the transmission synchronous clock 1120 is output HIGH for 5 cycles of the transmission circuit internal clock 1124 (number of transmission bits + offset), thereby performing a total of 3 bits of data transmission of “111” and “0” in the second transmission. In FIG. 27, since the transmission synchronous clock 1120 is limited to four periods of the transmission circuit internal clock 1124, the shift operation of the shift registers 1101 and 1103 is interrupted. Timing is 2 cycles of the clock HIGH before the offset addition is the transmission circuit internal clock 1124 Therefore, a total of 2-bit data transmission of “11” is performed in the first transmission, and a 1-bit data transmission of “1” is performed in the second transmission (time t35). Has been implemented.

  In data reception circuit 1700, serial reception data (0) 1719 and reception synchronization clock (0) 1720 pass through synchronizers 2400 and 2402, respectively, in reception signal switching timing correction circuit 1722 according to the initial setting in operation C of the second embodiment. Further, by delaying the reception synchronization clock (0_2) 2416 by one period of the reception circuit internal clock 1723, the reception synchronization clock (1) 1710 and the reception synchronization clock (1) 1714 shown in FIG. The positive edge of the synchronous clock (1) 1714 and the switching timing of the value of the serial reception data (1) 1710 are aligned and passed to the subsequent circuits (time t42). Further, with respect to the reception synchronous clock (0) 1720, the HIGH width is four periods of the reception circuit internal clock 1723 due to the delay when passing through the terminal (from immediately before time t41 to immediately after time t43. In the synchronous clock HIGH width correction circuit 1706, the HIGH width is expanded by one period of the reception circuit internal clock 1723 in accordance with the initial setting in the operation C of the second embodiment, so that the clock HIGH width at the time of transmission is reproduced and received. Synchronous clock (2) 1715 is passed to the next circuit (from time t42 to time t46). Further, among the HIGH widths of the reception synchronization clock (2) 1715, the number of bits of reception data indicates three cycles of the reception circuit internal clock 1723 excluding the influence of the offset added by the data transmission circuit 1100. Therefore, the signal from which the influence of the offset is removed by the synchronous clock offset removal circuit 1707 is used as the shift register operation permission signal 1716 of the data reception circuit 1700 as the LH signal of the shift registers 1703 and 1704 ( From time t44 to time t46). By passing through the synchronous clock offset removal circuit 1707, the shift register operation permission signal 1716 is delayed by an offset amount (from time t42 to time t44) with respect to the serial reception data (1) 1710 as shown in FIG. Therefore, the reception data offset removal circuit 1708 also delays the serial reception data (1) 1710 by the offset amount, thereby switching the reception data used in the data reception shift register 1703 and the reception status confirmation shift register 1704. And the positive edge of the synchronous clock are aligned (time t44). By the serial reception data (2) 1711 and the shift register operation enable signal 1716 generated in this way, 3-bit HIGH data “111” is stored in the data reception shift register 1703, and 3 bits of the reception status confirmation shift register 1704 are stored in 3 bits. HIGH is stored (time t46).

  Next, regarding the operation E of the second embodiment, the operation of the data transmission circuit 1100 will be described with reference to FIG. 29 and the operation of the data reception circuit 1700 will be described with reference to FIGS. 30 is a timing chart when no transmission / reception error occurs, and FIGS. 31 and 32 are timing charts when a transmission / reception error occurs.

  In the data transmission circuit 1100, HIGH is stored in all the flip-flops 1300 of the transmission status confirmation shift register 1103 at the timing when transmission of one bit of data is completed and transmission of the next bit is started, and an N-bit data transmission completion signal 1116 is received. It becomes HIGH (time t62). As a result, after transmitting 2 bits of data, the operations of the shift registers 1101 and 1103 are finished. On the other hand, since the offset is added to the transmission synchronization clock 1120 by two periods of the transmission circuit internal clock 1124 by the offset addition circuit 1109, the offset “2” is added to the bit number “2” of the data “00” to be transmitted this time. The HIGH width is held for four periods of the transmission circuit internal clock 1124 (from time t61 to time t63). Further, when the N-bit data transmission completion signal 1116 becomes HIGH, the transmission supply data 1112 supplied from the transmission data supply unit 1102 to the data transmission shift register 1101 is transmitted next from the data that has been transmitted. Switching to power data (time t62). When the N-bit data transmission completion signal 1116 is HIGH and the clock 1 cycle count end signal 1117 is HIGH (time t64), the serial data transmission circuit 1107 is directed to the input (time t65), and the data reception circuit 1700 It enters the state of waiting for the transmission / reception error signal. When the transmission / reception error signal 1121 is output from the data reception circuit 1700 during the transmission / reception error acceptance state, the transmission data supply unit 1102 transmits the transmission supply data 1112 immediately before the transmission data to be transmitted at the reception timing. Switching to completed N-bit data (time t67). However, when the transmission / reception error signal 1121 is not output, the transmission data supply unit 1102 holds the transmission supply data 1112 as data to be transmitted next. The transmission / reception error acceptance state lasts for one cycle of the synchronous clock, and this time is counted by the clock one cycle counter (2) 1110.

  The clock 1 cycle counter (2) 1110 starts counting when the clock 1 cycle count end signal 1117 is asserted while the N-bit data transmission completion signal 1116 is HIGH (time t64), and the count value is When the upper limit value “9” is reached (time t68), the transmission data update signal 1118 is HIGH for one cycle of the transmission circuit internal clock 1124 (until time t69). When the transmission data update signal 1118 becomes HIGH, the transmission / reception error acceptance state is completed, the next data to be transmitted is stored in the data transmission shift register 1101, the transmission status confirmation shift register 1103 is cleared, and the output direction of the serial data transmission circuit 1107 (Time t70) to prepare for the next data transmission. Further, when data to be transmitted next is stored in the data transmission shift register 1101, the transmission data edge detection signal 1114 may be switched. However, the edge detection circuit 1104 does not change the transmission data update signal 1118 while it is HIGH. Does not detect the edge of the transmission data edge detection signal 1114, the transmission data edge detection signal 1115 does not become HIGH (time t68).

  In the data receiving circuit 1700, the received signal switching timing correction circuit 1722 adjusts the edge timing with respect to the received data and the synchronous clock, and the synchronous clock HIGH width correction circuit 1706 extends the decrease of the synchronous clock HIGH width. Referring to serial reception data (2) 1711 and shift register operation enable signal 1716 that have been offset-corrected by synchronous clock offset removal circuit 1707 and reception data offset removal circuit 1708, respectively (time t81 in FIGS. 30 to 32) Execute data reception.

  Here, as shown in FIG. 32, the reception status confirmation shift register 1704 becomes all bits HIGH, and the shift register operation permission signal 1716 is HIGH even though the N-bit reception completion signal 2005 is HIGH. In this case (time t81a in FIG. 32), it is determined that the receiving side has erroneously received extra data (when 4-bit data is transmitted, 5-bit data has been received due to factors such as correction failure). The error occurrence signal (2) 2007 is switched to HIGH (time t82 in FIG. 32). Thereafter, when the shift register operation permission signal 1716 becomes LOW, the LOW width is counted by the synchronous clock LOW width counter 1709. The synchronous clock LOW width counter 1709 is cleared by the positive edge of the shift register operation enable signal 1716 (time t81 in FIG. 32), and starts counting at the negative edge of the shift register operation enable signal 1716 (time t82 in FIG. 32). The clock LOW width count end signal 1717 is set to HIGH for one cycle of the reception circuit internal clock 1723 at the rise of the reception circuit internal clock 1723 next when the count value reaches the upper limit value “7” (from time t83 in FIG. 32 to time until t84). When the synchronous clock LOW width counter 1709 recognizes that the LOW width of the shift register operation permission signal 1716 is a width obtained by subtracting the offset from one period width of the synchronous clock (in this example, the shift register operation permission signal 1716). When the data transmission circuit 1100 is in a transmission / reception error acceptance state, the transmission / reception error signal 1713 is transmitted from the serial data reception circuit 1701 (when counting that the LOW width is equal to eight cycles of the reception circuit internal clock 1723) (From time t83 to time t84 in FIG. 32). However, an offset having the same width as the offset added to the synchronous clock on the transmission side is added to the transmission / reception error signal 1713 at the time of output and reflected in the waveform of the serial transmission / reception data 1130 (from time t83 in FIG. 32 to time until t85). After the transmission / reception error signal 1713 is issued, the reception status confirmation shift register 1704 is cleared (time t84 in FIG. 32), and the serial data reception circuit 1701 is directed in the reception direction to prepare for reception of the next data. When an error occurs, the reception data storage permission signal 1718 does not become HIGH, so the data in the data reception shift register 1703 is not stored in the reception data storage unit 1705, and the data reception shift register 1703 is overwritten with the next reception data.

  Further, as shown in FIG. 31, even though the N-bit reception completion signal 2005 is not asserted, the LOW width of the shift register operation enable signal 1716 is a width obtained by subtracting the offset from one period width of the synchronous clock. In such a case, it is determined that the receiving side has mistakenly received data (only 4 bits could be received due to factors such as correction failure when 4-bit data was transmitted), and an error occurrence signal (1 ) 2006 switches to HIGH, and at the same time, the transmission / reception error signal 1713 switches to HIGH (time t83 in FIG. 31). The subsequent circuit operation is the same as the example shown in FIG.

  As shown in FIG. 30, when the shift register operation permission signal 1716 is LOW when the N-bit reception completion signal 2005 is HIGH (time t82 in FIG. 30), data transmission / reception is normal. When it is determined that the shift register operation permission signal 1716 has been completed and it is confirmed that the LOW width of the shift register operation permission signal 1716 is a width obtained by subtracting the offset from one period width of the synchronous clock, the data storage permission signal 1718 is switched to HIGH (FIG. At time t83), the data in the data reception shift register 1703 is stored in the reception data storage unit 1705. Also, the reception status confirmation shift register 1704 is cleared (time t84 in FIG. 30) to prepare for the next data reception.

  As described above, the present invention has an effect of improving the serial transmission / reception speed. For example, when transferring a program code from a host to a memory built in an LSI using serial communication, the transfer time can be shortened. Can be achieved.

It is a block diagram which shows the structure of the data transmission circuit in Embodiment 1 of this invention, and a data reception circuit. It is a block diagram of the data transmission shift register in FIG. It is a block diagram of the transmission condition confirmation shift register in FIG. It is a block diagram of the synchronous clock output switching circuit in FIG. It is a block diagram of the data reception shift register in FIG. It is a block diagram of the reception condition confirmation shift register in FIG. 3 is a timing chart illustrating the operation of the data transmission circuit according to the first embodiment. 3 is a timing chart illustrating an operation of the data receiving circuit according to the first embodiment. 4 is a timing chart showing the operation of the data transmission circuit in the operation when N-bit data transmission / reception is completed in the first embodiment. 4 is a timing chart showing the operation of the data receiving circuit in the operation when N-bit data transmission / reception is completed in the first embodiment. It is a block diagram which shows the structure of the data transmission circuit in Embodiment 2 of this invention. It is a block diagram of the data transmission shift register in FIG. It is a block diagram of the transmission condition confirmation shift register in FIG. It is a block diagram of the synchronous clock output switching circuit in FIG. It is a block diagram of the serial data transmission circuit in FIG. It is a block diagram of the offset addition circuit in FIG. It is a block diagram which shows the structure of the data receiver circuit in Embodiment 2 of this invention. It is a block diagram of the serial data receiving circuit in FIG. It is a block diagram of the data reception shift register in FIG. It is a block diagram of the reception condition confirmation shift register in FIG. It is a block diagram of the synchronous clock HIGH width correction circuit in FIG. It is a block diagram of the synchronous clock offset removal circuit in FIG. FIG. 18 is a configuration diagram of a reception data offset removal circuit in FIG. 17. FIG. 18 is a configuration diagram of a reception signal switching timing correction circuit in FIG. 17. 10 is a timing chart illustrating an initial setting operation of the data reception circuit in the serial transmission / reception operation according to the second embodiment. 10 is a timing chart illustrating an operation of the data transmission circuit when transmission data is switched in the serial transmission / reception operation according to the second embodiment. 10 is a timing chart showing an operation of the data transmission circuit when an overflow of the synchronous clock HIGH width occurs in the serial transmission / reception operation in the second embodiment. 9 is a timing chart illustrating an operation of a data reception circuit in a serial transmission / reception operation according to the second embodiment. 10 is a timing chart showing the operation of the data transmission circuit when a transmission / reception error occurs in the operation when N-bit data transmission / reception is completed in the second embodiment. 10 is a timing chart showing the operation of the data receiving circuit when no transmission / reception error occurs in the operation at the time of completion of N-bit data transmission / reception in the second embodiment. 10 is a timing chart showing the operation of the data receiving circuit when a transmission / reception error with insufficient received data occurs in the operation when N-bit data transmission / reception is completed in Embodiment 2. 10 is a timing chart showing an operation of the data receiving circuit when a transmission / reception error occurs when extra reception data is received in the operation at the time of completion of N-bit data transmission / reception in the second embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Data transmission circuit 101 Data transmission shift register 102 Transmission data supply part 103 Transmission status confirmation shift register 104 Edge detection circuit 105 Clock 1 period counter 106 Synchronous clock output switching circuit 107 Data transmission terminal 108 Synchronous clock transmission terminal 109 Transmission supply data 110 Transmission Data 111 Transmission data edge detection signal 112 Transmission data edge detection signal 113 Supply data switching signal 114 Synchronization clock output switching signal 115 Clock 1 cycle count end signal 116 Transmission data update signal 117 Transmission synchronization clock 118 Transmission circuit internal clock 120 Transmission / reception data 121 Transmission / reception synchronization clock 130 Data reception circuit 131 Data reception terminal 132 Synchronization clock reception terminal 133 Data reception shift register 134 Reception status confirmation shift Register 135 Reception data storage unit 136 Reception data 137 Reception synchronization clock 138 Reception storage data 139 Data storage enable signal 140 Reception circuit internal clock 200 Selector 201 Flip flop 300 Flip flop 301 NOR gate 302 AND gate 303 Inverter 304 Flip flop 400 Selector 401 Flip 500 flip-flop 600 flip-flop 601 flip-flop 1100 data transmission circuit 1101 data transmission shift register 1102 transmission data supply unit 1103 transmission status confirmation shift register 1104 edge detection circuit 1105 clock 1 period counter 1106 synchronous clock output switching circuit 1107 serial data transmission circuit 1108 Synchronous clock transmission terminal 1109 with offset Circuit 1110 one clock cycle counter (2)
1111 clock HIGH width counter 1112 transmission supply data 1113 serial transmission data 1114 transmission data edge detection signal 1115 transmission data edge detection signal 1116 N-bit data transmission completion signal 1117 clock 1 cycle count end signal 1118 transmission data update signal 1119 synchronous clock output switching Signal 1120 Transmission synchronization clock 1121 Transmission error signal 1122 Clock HIGH over signal 1123 Shift register operation enable signal 1124 Transmission circuit internal clock 1130 Serial transmission / reception data 1131 Transmission / reception synchronization clock 1200 Selector 1201 Flip flop 1300 Flip flop 1301 NOR gate 1400 Selector 1401 Flip flop 1500 flip-flop 1501 inverter 15 2 Tristate buffer 1503 AND gate 1510 Serial data transmission terminal 1600 Flip-flop 1601 OR gate 1602 Selector 1700 Data reception circuit 1701 Serial data reception circuit 1702 Synchronous clock reception terminal 1703 Data reception shift register 1704 Reception status confirmation shift register 1705 Reception data storage unit 1706 Synchronization clock HIGH width correction circuit 1707 Synchronization clock offset removal circuit 1708 Reception data offset removal circuit 1709 Synchronization clock LOW width counter 1710 Serial reception data (1)
1711 Serial received data (2)
1712 Reception storage data 1713 Transmission / reception error signal 1714 Reception synchronization clock (1)
1715 Reception synchronous clock (2)
1716 Shift register operation enable signal 1717 Clock LOW width count end signal 1718 Data storage enable signal 1719 Serial reception data (0)
1720 Receive synchronous clock (0)
1721 Initial setting permission signal (1)
1722 Reception signal switching timing correction circuit 1723 Reception circuit internal clock 1800 Offset addition circuit 1801 Tristate buffer 1802 Inverter 1803 AND gate 1810 Serial data reception terminal 1900 Flip flop 2000 Flip flop 2001 Flip flop 2005 N bit reception completion signal 2006 Error occurrence signal ( 1)
2007 Error occurrence signal (2)
2010 Inverter 2011, 2012 AND gate 2013 Flip flop 2014 AND gate 2015 OR gate 2016 Inverter 2017 AND gate 2100 Flip flop 2101 OR gate 2102 Selector 2103 Reception synchronization clock HIGH width counter 2105 Reception synchronization clock HIGH width 2200 Flip flop 2201 AND gate 2202 Selector 2203 Inverter 2204 AND gate 2300 Flip-flop 2301 Selector 2400 Synchronizer 2401 Flip-flop 2402 Synchronizer 2403 Flip-flop 2405 Data positive edge detector 2406 Synchronous clock positive edge detector 2407 Clock delay counter 2408 Data delay counter 2410 Initial setting Permission signal (0)
2411 Data positive edge detection signal 2412 Synchronous clock positive edge detection signal 2413 Clock delay count enable 2414 Data delay count enable 2415 Serial reception data (0_2)
2416 Reception synchronous clock (0_2)
2417 Clock delay count value 2418 Data delay count value 2420 Flip-flops 2421 and 2422 Inverters 2423 and 2424 AND gates 2425 and 2426 Selector

Claims (17)

A serial data transmission terminal;
A synchronous clock transmission terminal;
A data transmission shift register for temporarily storing and transmitting serial transmission data;
Transmission data supply for storing serial data for transmission to the data transmission shift register at the start of serial transmission or when transmission of serial transmission data temporarily stored in the data transmission shift register is completed And
Reflecting the transmission status of the serial transmission data stored in the data transmission shift register, generating a data transmission completion signal when all bits of the serial transmission data stored in the data transmission shift register have been transmitted, A data transmission status confirmation shift register having the same number of bits as the data transmission shift register for notifying that transmission of all bits of serial transmission data stored in the data transmission shift register is completed;
By detecting the switching edge of the Q signal of a flip-flop in the data transmission shift register from 0 to 1 or 1 to 0, and generating an edge detection signal at the detected timing, An edge detection circuit for detecting and notifying a switching point from 1 or 1 to 0;
A clock 1 cycle counter with a configurable number of counts for counting the clock width of the output synchronous clock and generating the 1 cycle count end signal at the end of the count to notify the end of one cycle period of the synchronous clock When,
From the timing at which the edge detection circuit detects the switching position of serial transmission data from 0 to 1 or 1 to 0, or the timing at which the serial data temporarily stored in the data transmission shift register is completely transmitted, The signal output from the synchronous clock transmission terminal is set to LOW during the period until one clock is counted by the clock one cycle counter, and the signal output from the synchronous clock transmission terminal is set to HIGH in other cases. And a synchronous clock output switching circuit for
If the data to be serially transmitted has a portion in which multiple bits of 0 or 1 are continuous, the synchronous clock is switched by switching the duty ratio of the synchronous clock output from the synchronous clock transmission terminal according to the number of consecutive bits. A transmission circuit for transmitting serial data of a plurality of bits during one period of A serial data receiving terminal;
A synchronous clock receiving terminal;
The serial reception data input from the serial data reception terminal for receiving and temporarily storing serial data of an arbitrary number of bits operates as a D signal, and the synchronous clock input from the synchronous clock reception terminal A data reception shift register operating as an LH signal;
When the data reception shift register is updated all bits with the serial data received at the serial data reception terminal, the data storage unit for storing and using the data; and
Reflects the reception status of serial data in the data reception shift register, asserts a data storage enable signal when the data reception shift register is updated with all-bit serial data, and the data reception shift register A data reception status confirmation shift register having the same number of bits as the data reception shift register for notifying that reception has been completed;
By changing the number of bits of serial reception data stored in the data reception shift register in accordance with the duty ratio of the synchronous clock output from the synchronous clock reception terminal, a serial number of a plurality of bits is obtained during one period of the synchronous clock. A receiving circuit for receiving data. The transmission circuit according to claim 1,
By adding an offset to the signal for switching the synchronous clock output from the synchronous clock output switching circuit to HIGH and arbitrarily extending the HIGH period width of the synchronous clock, the HIGH of the clock due to the influence of the delay generated at the terminal A transmission circuit, further comprising an offset addition circuit capable of setting an offset value for preventing width loss. The receiving circuit according to claim 2,
A synchronous clock offset removing circuit for removing the offset added to the HIGH width of the synchronous clock and returning the HIGH width of the synchronous clock to the HIGH width before adding the offset;
Serial reception is performed by adding to the serial reception data received from the serial data reception terminal a delay having exactly the same length as the delay generated in the synchronization clock when the synchronization clock passes through the synchronization clock offset removal circuit. A reception data offset removal circuit for preventing the occurrence of a shift between the data switching timing and the rising timing of the synchronous clock;
A receiving circuit which removes the influence of an offset even when an offset is added to the HIGH width of the synchronous clock, and reproduces and receives the duty ratio of the synchronous clock before adding the offset. The transmission circuit according to claim 1,
The synchronous clock HIGH signal assert period is counted, and when the assert period exceeds a certain count period, a HIGH width overflow signal is asserted, and the HIGH width of the synchronous clock output from the synchronous clock transmission terminal exceeds a certain period. A clock HIGH width counter for notifying that,
The synchronous clock output switching circuit sets a signal output from the synchronous clock transmission terminal to LOW during a period from the timing when the HIGH width overflow signal is asserted to the time when one clock is counted by the clock one cycle counter. Has more functions,
A transmission circuit characterized by preventing the loss of the LOW width of a clock due to the influence of a delay generated at a terminal by limiting the HIGH width of the synchronous clock. The transmission circuit according to claim 1,
A communication error reception period counter that starts counting when all the data stored in the data transmission shift register is transmitted and the period of the clock ends;
When all the data stored in the data transmission shift register is transmitted, the input is switched at the same time, and the communication error signal is input when the communication error signal is input while the communication error reception period counter is counting. A serial data transmission circuit for detecting that an error has occurred in serial transmission / reception by detecting and asserting a transmission / reception error signal;
The transmission data supply unit stores again the same data as the serial transmission data stored immediately before in the data transmission shift register when the transmission / reception error signal is asserted, and if not asserted, the transmission data supply unit stores the serial data stored immediately before. A transmission circuit further comprising a function of storing data to be transmitted next to transmission data. The receiving circuit according to claim 2,
The serial transmission data stored in the data transmission shift register of the transmission circuit is counted by counting the LOW width of the input signal from the synchronous clock reception terminal and asserting the clock LOW width count end signal when overflow occurs. A clock LOW width counter for notifying that all bits have been transmitted,
When the LOW width count end signal is further asserted when the input signal from the synchronous clock reception terminal is HIGH even though serial reception data is stored for all the bits of the data reception shift register, or A serial data receiving circuit that switches to output when the LOW width count end signal is asserted even though serial received data is not stored for all bits of the data reception shift register, and outputs a transmission / reception error signal And a receiving circuit. The receiving circuit according to claim 2,
Before starting serial data transmission / reception, a certain HIGH signal is input from the transmission circuit to the synchronous clock receiving terminal, and the HIGH width of the expected received signal and the HIGH of the signal actually received from the synchronous clock receiving terminal are input. A synchronous clock HIGH width correction circuit for comparing the width and correcting a decrease from the expected value of the HIGH width;
A receiving circuit that corrects a HIGH width of a reception synchronization clock that decreases due to a delay generated at a terminal when transmitting and receiving the synchronization clock, and reproduces the synchronization clock width intended by the transmission side. The receiving circuit according to claim 2,
Before starting serial data transmission / reception, input a signal of a certain HIGH width from the transmission circuit to the synchronous clock reception terminal and the serial data reception terminal, and measure the timing difference between the positive edges of the two reaching the reception circuit. A receiving circuit characterized in that a delay is added to a signal that has arrived early among the both, so that the arrival timings of the both coincide with each other.   A serial transmission / reception system comprising the transmission circuit according to claim 1 and the reception circuit according to claim 2.   A serial transmission / reception system comprising the transmission circuit according to claim 3 and the reception circuit according to claim 4.   A serial transmission / reception system comprising the transmission circuit according to claim 5 and the reception circuit according to claim 2.   A serial transmission / reception system comprising the transmission circuit according to claim 6 and the reception circuit according to claim 7.   A serial transmission / reception system comprising the transmission circuit according to claim 1 and the reception circuit according to claim 8.   A serial transmission / reception system comprising the transmission circuit according to claim 5 and the reception circuit according to claim 8.   A serial transmission / reception system comprising the transmission circuit according to claim 1 and the reception circuit according to claim 9.   A serial transmission / reception system comprising the transmission circuit according to claim 5 and the reception circuit according to claim 9.

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