JP2727778B2 - High-speed line termination circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed line termination circuit, and more particularly to a high-speed line termination circuit used as a high-speed interface in a multiplexing device of a data transmission system.

[0002]

2. Description of the Related Art A multiplexer in a data transmission system performs mutual conversion between data transmitted by a plurality of low-speed lines and data transmitted by a plurality of high-speed lines. Data from each low-speed line is received by a low-speed line termination circuit corresponding to each low-speed line and input to a multiplexing / demultiplexing circuit. Data input from each low-speed line termination circuit to the multiplexing / demultiplexing circuit is rearranged and sent to each high-speed line by each high-speed line termination circuit corresponding to each high-speed line. On the other hand, data from each high-speed line is received by each high-speed line termination circuit and input to the multiplexing / demultiplexing circuit. Data input to the multiplexing / demultiplexing circuit from each high-speed line termination circuit is rearranged, and each low-speed line termination circuit corresponding to each low-speed line
Sent to each low-speed line.

The high-speed line termination circuit receives transmission data to be transmitted to the corresponding high-speed line from the multiplexing / demultiplexing circuit, multiplexes the transmission data with a transmission frame synchronization signal, and multiplexes the transmission data with the transmission frame synchronization signal. Is transmitted to the corresponding high-speed line. Further, the high-speed line termination circuit receives a received signal, which is a multiplexed signal of the received data and the received frame synchronization signal, from the corresponding high-speed line, removes the received frame synchronization signal from the received signal, and multiplexes / demultiplexes the received data. Send to circuit.

In order to remove the received frame synchronization signal from the received signal, timing information of the received frame synchronization signal is required. In order to obtain this timing information, the high-speed line termination circuit has a frame synchronization circuit that performs frame synchronization with the received signal. The frame synchronization circuit also plays a role of monitoring a signal received from the high-speed line and detecting an abnormality of the high-speed line. That is, the frame synchronization circuit
When the frame cannot be synchronized with the received signal, an out-of-frame signal is output to notify the abnormality of the high-speed line. The out-of-frame signal is used as a trigger for switching the abnormal high-speed line and the corresponding high-speed line termination circuit to the spare high-speed line and the corresponding spare high-speed line termination circuit.

[0005]

The above-mentioned conventional high-speed line termination circuit does not have a function of detecting its own abnormality. For this reason, the conventional high-speed line termination circuit may not be able to properly switch to the standby mode when the circuit itself is abnormal.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a high-speed line termination circuit capable of detecting not only an abnormality of a corresponding high-speed line but also its own abnormality.

[0007]

SUMMARY OF THE INVENTION A high-speed line termination circuit according to the present invention communicates data to be transmitted with a transmission frame synchronization signal and communicates the data to be transmitted with the transmission frame synchronization signal. Means for sending out to the line,
Means for receiving a signal from the communication line, means for multiplexing the received signal and the data to be transmitted provided with the transmission frame synchronization signal, and creating a multiplexed signal,
Means for processing the multiplexed signal to output data contained in the received signal; means for separating the data to be transmitted contained in the multiplexed signal from the multiplexed signal; Means for comparing the data to be transmitted and the data to be transmitted obtained from the separating means to detect a mismatch between the two data.

Further, the high-speed line termination circuit according to the present invention may include means for detecting a loss of frame synchronization in the data to be transmitted to which the transmission frame synchronization signal has been added from the multiplexed signal. Means for generating a signal indicating frame synchronization of the received signal from the multiplexed signal and supplying the signal to the processing means, and further comprising a frame synchronization in the received signal from the multiplexed signal. May include a means for detecting a deviation, furthermore, a means for generating data of a predetermined pattern, and providing the data of the pattern to the data to be transmitted provided with the transmission frame synchronization signal. Means for supplying to the means for creating the multiplexed signal in place of the data to be transmitted given the transmission frame synchronization signal Means for extracting the data of the pattern from the multiplexed signal to which the data of the pattern has been added, and comparing the data of the pattern from the means for generating with the data of the pattern from the means for extracting Means for detecting a mismatch between the two data.

[0009] The detecting means may include means for adjusting the phase of the two data, the detecting means may include means for adjusting the phase of the two data, and the sending means may be a line. The receiving means may include a driver, and the receiving means may include a line receiver.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1, in a high-speed line termination circuit 10 according to a first embodiment of the present invention, transmission data output by a multiplexing / demultiplexing circuit of a multiplexer of a data transmission system to be transmitted to a high-speed line is transmitted. The first multiplexing circuit 12 receives
The transmission frame synchronization signal F2 is multiplexed with the transmission data and transmitted to the high-speed line. The signal received from the high-speed line is received by the second multiplexing circuit 15, and the separation circuit 17 removes the reception frame synchronization signal from the reception signal and receives the signal. The data is output to the multiplexing / demultiplexing circuit of the multiplexer.

The transmission data input to the high-speed line termination circuit 10 is framed. The frame generation circuit 11
The transmission frame synchronization signal F2 at the frame period of the transmission data
Occurs. The first multiplexing circuit 12 multiplexes the transmission frame synchronization signal F2 generated by the frame generation circuit 11 into the input transmission data, and generates a line driver 1 as a transmission signal.
Output to 3. The line driver 13 is a known circuit that sends a transmission signal from the multiplexing circuit 12 to a high-speed line.

The line receiver 14 has a known circuit configuration, equalizes a signal from a high-speed line, and converts a signal (received signal) obtained by multiplexing a received frame synchronization signal into received data into a second signal.
Is output to the multiplexing circuit 15. The second multiplexing circuit 15 receives the transmission signal from the first multiplexing circuit 12 and the line receiver 14.
Are multiplexed with the received signal from the multiplexing circuit and output to the frame synchronization circuit 16 and the separation circuit 17.

The frame synchronization circuit 16 detects the transmission frame synchronization signal and the reception frame synchronization signal from the signal output from the multiplexing circuit 15 and synchronizes the frame with the transmission signal frame and the reception signal frame. , And outputs the timing signal A of the received frame synchronization signal to the separation circuit 17. Also, the frame synchronization circuit 16
Outputs the out-of-synchronization signal B to the failure notification circuit 20 when the reception frame synchronization signal cannot be detected, and outputs the out-of-synchronization signal C to the failure notification circuit 20 when the transmission frame synchronization signal F2 cannot be detected. The separation circuit 17 receives the reception signal and the transmission signal from the multiplexing circuit 15, the timing signal A from the frame synchronization circuit 16, respectively, and receives the reception data D obtained by removing the reception frame synchronization signal from the reception signal, and the transmission signal from the transmission signal. The signal F2 is separated and output as transmission data E from which the signal F2 has been removed. The separation circuit 17 detects the position of the received frame synchronization signal to be removed from the received signal.
Is used. The transmission data D output from the separation circuit 17 is sent to the multiplexing / separating circuit of the multiplexer.

The transmission data E output from the separation circuit 17 is input to a pattern matching circuit 18. The multiplexing circuit 12
Is delayed by the buffer 19,
The phase is matched with the transmission data E from the separation circuit 17 and input to the pattern matching circuit 18. Pattern matching circuit 18
Compares the two input transmission data and outputs a transmission data mismatch signal N to the failure notification circuit 20 when a mismatch is detected. The failure notification circuit 20 outputs an alarm signal when the transmission data mismatch signal N from the pattern matching circuit 18 and the received frame out-of-sync signal B or the out-of-sync frame signal C from the frame synchronization circuit 16 are input.

If an abnormality occurs in the high-speed line, the received frame synchronization signal disappears from the received signal, so that the frame synchronization circuit 16 cannot perform frame synchronization with the received signal in the signal from the multiplexing circuit 15, and the received frame synchronization signal is lost. B is output. As a result, the failure notification circuit 20 outputs an alarm signal. Further, when the transmission frame synchronization signal F2 disappears from the transmission signal due to, for example, an abnormality in the frame generation circuit 11, the frame synchronization circuit 16 outputs the transmission frame synchronization loss signal C. During the transmission signal, the transmission frame synchronization signal F
2 is normally multiplexed but the transmission data is lost. If an error occurs in the multiplexing circuit 12, the pattern matching circuit 18 outputs a transmission data mismatch signal N. If an abnormality occurs in any part of the high-speed line termination circuit 10 except the line driver 13 and the failure notification circuit 20, at least one of the received frame out-of-synchronization signal B, the transmission frame out-of-synchronization signal C, or the transmission data mismatch signal N is output. Are output, and as a result, the failure notification circuit 20 outputs an alarm signal. Therefore, the output of the alarm signal from the failure notification circuit 20 causes the high-speed line or the high-speed line
It can detect that an abnormality has occurred in itself.

The alarm signal output from the fault notifying circuit 20 is used as a trigger for requesting that one or both of the high-speed line termination circuit 10 and the corresponding high-speed line be switched to standby.

It is to be noted that, based on information on which of the received frame out-of-synchronization signal B, transmission frame out-of-synchronization signal C, and transmission data inconsistency signal N has occurred at the time of occurrence of an abnormality, it is possible to determine to what extent the abnormality has occurred to some extent. Can be estimated.

Referring to FIG. 2, the received signal input from line receiver 14 to multiplexing circuit 15 is a signal in which received frame synchronization signal F1 and received data are multiplexed.
The transmission signal input from the multiplexing circuit 12 to the multiplexing circuit 15 is a signal in which the transmission frame synchronization signal F2 and the transmission data are multiplexed. The reception signal and the transmission signal have the same frame period, but the frame phases are not synchronized. The multiplexing circuit 15 multiplexes the input received signal and transmitted signal without matching the frame phases of these two signals. That is, the multiplexing circuit 15 multiplexes the reception signal and the transmission signal such that the reception signal input in each frame period of the transmission signal is arranged before each corresponding frame of the transmission signal. Therefore, the timing of the boundary between the reception signal and the transmission signal in the signal output from the multiplexing circuit 15 to the frame synchronization circuit 16 and the separation circuit 17 is known.
Also, the insertion position of the transmission frame synchronization signal F2 in the transmission signal is known because the transmission frame synchronization signal F2 is multiplexed with the transmission data by the multiplexing circuit 12. However, the insertion position of the reception frame synchronization signal F1 in the reception signal is unknown to the multiplexing circuit 15.

Referring to FIG. 3, the signal output from multiplexing circuit 15 is input to frame synchronization circuit 16 and applied to first and second pattern matching circuits 161 and 162, respectively. The frame synchronization circuit 16 includes a frame generation circuit 163. Referring also to FIG. 1, a transmission frame synchronization signal F generated by frame generation circuit 11 and input to frame synchronization circuit 16 through multiplexing circuits 12 and 15 is transmitted.
At a phase coincident with 2, the frame generation circuit 163 generates a transmission frame synchronization signal F2. Frame generation circuit 16
The transmission frame synchronization signal F2 in which the signal No. 3 has been generated is input to the first pattern matching circuit 161 through the variable buffer 164, and is also directly input to the second pattern matching circuit 162.

The second pattern matching circuit 162 compares the signal from the multiplexing circuit 15 with the transmission frame synchronization signal F2 from the frame generation circuit 163 at the timing of the transmission frame synchronization signal F2 from the frame generation circuit 163. As a result, the transmission frame synchronization signal F2 is detected from the signal output by the multiplexing circuit 15, and the frame is synchronized with the frame of the transmission signal. The second pattern matching circuit 162 generates a transmission frame out-of-synchronization signal C if there is a mismatch in the result of the matching, in other words, if the transmission frame synchronization signal F2 cannot be detected from the signal output from the multiplexing circuit 15. Output to the fault notification circuit 20.

The transmission frame synchronization signal F2 and the reception frame synchronization signal F1 included in the signal from the multiplexing circuit 15 have different phases, but have the same pattern repeated in a plurality of frame periods, for example, 24 frame periods. Variable buffer 1
The phase of the transmission frame synchronizing signal F2 that has passed through 64 can be matched with the phase of any time slot of the reception signal for 24 frames in the signal from the multiplexing circuit 15 (see FIG. 2). The variable delay range of the variable buffer 164 is set so as not to match the phase of any time slot of the signal. First pattern matching circuit 16
1 collates the signal from the multiplexing circuit 15 with the transmission frame synchronization signal F2 from the variable buffer 164 at the timing of the transmission frame synchronization signal F2 from the variable buffer 164. The outgoing signal B is transmitted to the variable buffer 164 and the failure notifying circuit 20.
Output to Upon receiving the out-of-sync signal B, the variable buffer 164 changes the delay time by one time slot of the signal from the multiplexing circuit 15. When the variable buffer 164 changes the delay time, the pattern matching circuit 161 compares the two input signals again. If the received frame synchronization signal F1 is correctly included in the signal from the multiplexing circuit 15, while the variable buffer 164 is sequentially changing the delay time within the variable range, the result of the comparison by the first pattern matching circuit 161 is They always match. The first pattern matching circuit 161 outputs the timing signal A of the received frame synchronization signal F1 to the separation circuit 1 each time the matching result matches.
7 is output. If the matching result of the first pattern matching circuit 161 does not match even if the delay time of the variable buffer 164 changes over the entire range of the variable range, the first pattern matching circuit 161 will continuously synchronize the received frame. It outputs an outlier signal B.

Referring to FIG. 4, the signal output from multiplexing circuit 15 and timing signal A output from first pattern matching circuit 161 of frame synchronization circuit 16 are separated by separation circuit 1
7 is input to the selector 171. The selector 171 is
Of the signal (see FIG. 2) input from the multiplexing circuit 15, only the received data is separated and output to the buffer 172, and only the transmission data is separated and output to the buffer 173. The timing of the boundary between the reception signal and the transmission signal in the signal from the multiplexing circuit 15 and the insertion position of the transmission frame synchronization signal F2 are known as already described, and the insertion position of the reception frame synchronization signal F1 is The selector 171 performs the above-described separation operation using the timing information.
The received data D for one frame is sequentially read from the buffer 172 over one frame period and sent to the multiplexing / demultiplexing circuit of the multiplexer. Further, one frame of transmission data E is sequentially read from the buffer 173 over one frame period,
Output to the pattern matching circuit 18.

By the way, if the multiplexing circuit 15 or the selector 171 in the separation circuit 17 fails, the separation circuit 1
7 may be fixed to “1” or “0” regardless of the transmission data E to the pattern matching circuit 18 regardless of the transmission data input to the multiplexing circuit 12. Such an abnormality occurs in the multiplexing circuit 15 or the separation circuit 17, and the transmission data input to the multiplexing circuit 12 is "1" or "0".
Although the probability of occurrence is small,
It can happen. The high-speed line termination circuit 10 cannot detect such an abnormality. Referring to FIG. 5, a second embodiment of the present invention is shown.
The high-speed line termination circuit 30 of the embodiment can detect such an abnormality.

The high-speed line termination circuit 30 includes, in addition to the high-speed line termination circuit 10 of the first embodiment shown in FIG. 1, a pattern generation circuit 31, a third multiplexing circuit 32, a second pattern matching circuit 33, and a second Buffer 34 is provided. The pattern generation circuit 31 generates an additional pattern with a high randomness, for example, a pseudo random pattern, in which the frame period of the transmission data is a repetition period.

Referring to FIG. 6, the third multiplexing circuit 32
Multiplexes the transmission signal from the first multiplexing circuit 12 with the additional pattern from the pattern generation circuit 31 and outputs the multiplexed signal. The second multiplexing circuit 15A multiplexes the signal output from the third multiplexing circuit 32 and the received signal from the line receiver 14 without matching the frame phases of these two signals.
That is, the second multiplexing circuit 15A is
The two signals are multiplexed such that the received signal input in each frame period of the signal from the second multiplexing circuit is arranged before each corresponding frame of the signal from the third multiplexing circuit 32. The frame synchronization circuit 16 detects the transmission frame synchronization signal F2 and the reception frame synchronization signal F1 from the signal output by the second multiplexing circuit 15A, and outputs a timing signal A of the reception frame synchronization signal F1. The frame synchronization circuit 16A
Outputs the out-of-synchronization signal B when the reception frame synchronization signal cannot be detected, and outputs the out-of-synchronization signal C when the transmission frame synchronization signal cannot be detected.

The separation circuit 17A is provided with the separation circuit 17 (FIG. 4).
And a buffer corresponding to the selector 171,
2, 173 and another buffer for additional patterns. The selector separates the received data, the transmitted data, and the additional pattern from the signal output from the second multiplexing circuit 15A using the timing signal A from the frame synchronization circuit 16, and outputs each of them to the corresponding buffer. The reception data D read from the buffer to which the reception data is input is sent to the multiplexing / demultiplexing circuit of the multiplexer, and the transmission data E read from the buffer to which the transmission data is input is output to the pattern matching circuit 18. The additional bit G read from the buffer to which the additional bit has been input is input to the second pattern matching circuit 33. The additional pattern generated by the pattern generating circuit 31 is also sent to the buffer 34, which delays the additional pattern and matches the phase with the additional pattern G from the separation circuit 17A and inputs it to the second pattern matching circuit 33. The second pattern matching circuit 33 compares the two input additional patterns, and outputs an additional pattern mismatch signal M when a mismatch is detected.

The additional pattern mismatch signal M output by the second pattern matching circuit 33, the out-of-synchronization signal B and the out-of-synchronization signal C output by the frame synchronization circuit 16, and the transmission signal output by the pattern matching circuit 18 are output. The data mismatch signal N is output from the failure notification circuit 20A.
Sent to The failure notification circuit 20A outputs an alarm signal when the received frame out-of-synchronization signal B, the transmission frame out-of-synchronization signal C, the transmission data mismatch signal N, or the additional pattern mismatch signal M is input.

The high-speed line termination circuit 30 shown in FIG. 5 includes, in addition to the circuits described above, a pattern generation circuit 11 and a multiplexing circuit 1.
2, a line driver 13, a line receiver 14, a pattern matching circuit 18 and a buffer 19,
It has all the functions of the high-speed line termination circuit 10 of FIG.

The transmission data input to the first multiplexing circuit 12 is multiplexed with the transmission frame synchronizing signal F2 in the multiplexing circuit 12, multiplexed with the additional pattern in the third multiplexing circuit 32, and multiplexed with the second multiplexing circuit 15A. Are multiplexed with the received signal, separated by the separation circuit 17A, and input to the pattern matching circuit 18. Second multiplexing circuit 15A
The transmission data E from the separation circuit 17A to the pattern matching circuit 18 is fixed at "1" or "0" irrespective of the transmission data input to the first multiplexing circuit 12 due to the abnormality of the selector or the abnormality of the selector in the separation circuit 17A. If the transmission data input to the first multiplexing circuit 12 is a series of "1" or "0", the pattern matching circuit 18
Since the two input transmission data match, the transmission data mismatch signal N is not output in spite of the occurrence of the abnormality.

However, in this case, the additional pattern G separated by the separation circuit 17A and input to the second pattern matching circuit 33 is also fixed to "1" or "0". On the other hand, since the additional pattern input from the pattern generation circuit 31 to the second pattern matching circuit 33 through the buffer 34 is a pattern rich in randomness, in this case, the two input signals to the second pattern matching circuit 33 are Additional patterns do not match,
The second pattern matching circuit 33 outputs an additional pattern mismatch signal M. As a result, the failure notification circuit 20A outputs an alarm signal. The output of the alarm signal can detect the occurrence of the above-described abnormality.

[0032]

As described above, the high-speed line termination circuit according to the present invention multiplexes a transmission signal with a reception signal and synchronizes the frame with the multiplexed signal. Also, by checking the frame synchronization with respect to, and by checking the coincidence between the transmission data separated from the multiplexed signal and the original transmission data, it is possible to detect not only the abnormality of the high-speed line but also the abnormality of itself.

Further, if not only the transmission signal but also the additional pattern is multiplexed into the reception signal and the coincidence between the additional pattern separated from the multiplexed signal and the original additional pattern is checked, it is possible to prevent the abnormality of the signal itself. Detection can be performed more reliably.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation of the multiplexing circuit 15 in FIG.

FIG. 3 is a block diagram of a frame synchronization circuit 16 in FIG. 1;

FIG. 4 is a block diagram of a separation circuit 17 in FIG.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 shows a multiplexing circuit 32 and a multiplexing circuit 15 in FIG.
6 is a timing chart for explaining the operation of A.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Frame generation circuit 12, 15, 15A, 32 Multiplexing circuit 13 Line driver 14 Line receiver 16 Frame synchronization circuit 17, 17A Separation circuit 18, 33 Pattern matching circuit 19, 34 Buffer 20, 20A Failure notification circuit 31 Pattern generation circuit

Claims (20)

(57) [Claims] 1. A means for providing a transmission frame synchronization signal to data to be transmitted, a means for sending data to be transmitted to which the transmission frame synchronization signal has been added to a communication line, and receiving a signal from the communication line Means for multiplexing a received signal and data to be transmitted to which the transmission frame synchronization signal has been added to create a multiplexed signal; and the multiplexing means for outputting data included in the received signal. Means for processing the multiplexed signal, means for separating the data to be transmitted contained in the multiplexed signal from the multiplexed signal, and the data to be transmitted and the transmitted data obtained from the means for separating. Means for comparing the data to be detected with the data to be detected to detect a mismatch between the two data. 2. The high-speed line termination circuit according to claim 1, further comprising means for detecting a loss of frame synchronization in data to be transmitted to which the transmission frame synchronization signal has been added from the multiplexed signal. 3. The high-speed line termination circuit according to claim 1, further comprising means for generating a signal indicating frame synchronization of the received signal from the multiplexed signal and supplying the signal to the processing means. 4. The high-speed line termination circuit according to claim 2, further comprising means for detecting a loss of frame synchronization in said received signal from said multiplexed signal. 5. A means for generating data of a predetermined pattern, and transmission to which data of the pattern is added to data to be transmitted to which the transmission frame synchronization signal is added and to which the transmission frame synchronization signal is added. Means for supplying to the means for creating the multiplexed signal in place of the data to be performed, and means for extracting the data of the pattern from the multiplexed signal to which the data of the pattern has been added,
The data of the pattern from the means for generating is compared with the data of the pattern from the means for extracting.
2. A high-speed line termination circuit according to claim 1, further comprising means for detecting a mismatch between the two data. 6. The high-speed line termination circuit according to claim 1, wherein said detecting means includes means for adjusting a phase of said two data. 7. The high-speed line termination circuit according to claim 5, wherein said detecting means includes means for adjusting the phase of said two data. 8. The high-speed line termination circuit according to claim 1, wherein said sending means includes a line driver. 9. The high-speed line termination circuit according to claim 1, wherein said receiving means includes a line receiver. 10. A first means for receiving transmission data to be sent out to a high-speed line, a frame generation circuit for generating a transmission frame synchronization signal to be added to the transmission data, and coupled to the first means and the frame generation circuit. The first means for inputting the transmission data from the first means, inputting the transmission frame synchronization signal from the frame generation circuit, multiplexing the transmission data and the transmission frame synchronization signal, and outputting the multiplexed transmission signal as a transmission signal. A multiplex circuit;
Second means for sending the transmission signal to the high-speed line;
A third means for receiving a received signal from the high-speed line, a first multiplexing circuit and a third means for coupling the transmission signal from the first multiplexing circuit to the third multiplexing circuit; A second multiplexing circuit that receives the received signal, multiplexes the two input signals, and outputs the multiplexed signal;
The multiplexing circuit outputs the timing signal of the detected reception frame synchronization signal by detecting the transmission frame synchronization signal and the reception frame synchronization signal included in the reception signal from the multiplexed signal output from the multiplexed signal, and outputs the transmission frame synchronization signal or the When a received frame synchronization signal cannot be detected, a frame synchronization circuit that outputs a frame synchronization loss signal, receives the multiplexed signal output by the second multiplexing circuit and the timing signal output by the frame synchronization circuit, A multiplexed signal is processed based on the timing signal to output received data obtained by removing the received frame synchronization signal from the received signal included in the multiplexed signal, and to output the transmission data included in the multiplexed signal. A separating circuit, and transmitting the transmission data output by the separating circuit to the first
A high-speed line termination circuit comprising pattern matching means for checking the transmission data from the first means input to the multiplexing circuit and detecting a mismatch, and outputting a mismatch signal. 11. The high-speed apparatus according to claim 10, wherein said pattern matching means includes a buffer for delaying said transmission data from said first means and adjusting a phase with said transmission data output from said separation circuit. Line termination circuit. 12. The high-speed line termination circuit according to claim 10, wherein said second means includes a line driver which receives said transmission signal from said first multiplexing circuit and sends out said transmission signal to said high-speed line. 13. The high-speed line termination circuit according to claim 12, wherein said third means includes a line receiver for receiving said reception signal from said high-speed line and outputting said signal to said second multiplexing circuit. 14. A failure notification circuit for receiving at least one of the frame synchronization loss signal from the frame synchronization circuit and the mismatch signal from the pattern matching circuit and outputting an alarm signal. Item 1
0. High-speed line termination circuit. 15. The frame synchronization circuit outputs a transmission frame synchronization loss signal when the transmission frame synchronization signal cannot be detected, and outputs a reception frame synchronization loss signal when the reception frame synchronization signal cannot be detected. The high-speed line termination circuit according to claim 10. 16. A frame generating circuit for generating a transmission frame synchronization signal, receiving transmission data to be sent out to a high-speed line and the transmission frame synchronization signal, multiplexing the transmission data and the transmission frame synchronization signal, and outputting the result as a transmission signal. A first multiplexing circuit, a pattern generating circuit for generating a predetermined pattern, and a second multiplexing circuit for multiplexing the pattern from the pattern generating circuit and the transmission signal from the first multiplexing circuit A third multiplexing circuit for multiplexing a signal from the second multiplexing circuit into a reception signal received from the high-speed line, and a transmission frame synchronization signal and the reception from the signal output by the third multiplexing circuit. Detects a received frame synchronization signal included in the signal and outputs a timing signal of the received frame synchronization signal, and outputs the transmission frame synchronization signal or When the received frame synchronization signal cannot be detected, a frame synchronization circuit that outputs a frame synchronization loss signal, and processes the signal output by the third multiplexing circuit based on the timing signal output by the frame synchronization circuit, A separation circuit that separates the reception frame synchronization signal from the reception signal into the transmission data and the pattern, and outputs the transmission data and the pattern; and inputs the transmission data output by the separation circuit to the first multiplexing circuit. A first pattern matching unit that outputs a transmission data mismatch signal when a mismatch is detected by comparing the transmission data with the transmission data; and a mismatch is detected by comparing the pattern output by the separation circuit with the pattern from the pattern generation circuit. And a second pattern matching means for outputting a pattern mismatch signal. Line termination circuit. 17. The first pattern matching means includes a first buffer for delaying the transmission data input to the first multiplexing circuit and adjusting the phase to the transmission data output from the separation circuit, 17. The apparatus according to claim 16, wherein the second pattern matching means includes a second buffer for delaying the pattern output from the pattern generation means and adjusting the phase to the pattern output from the separation circuit.
A high-speed line termination circuit as described. 18. A line driver that receives the transmission signal from the first multiplexing circuit and sends out the transmission signal to the high-speed line.
18. The high-speed line termination circuit according to claim 17, further comprising: a line receiver that receives the reception signal from the high-speed line and outputs the received signal to the second multiplexing circuit. 19. At least one of the frame synchronization loss signal from the frame synchronization circuit, the transmission data mismatch signal from the first pattern matching circuit, and the pattern mismatch signal from the second pattern matching circuit.
19. The high-speed line termination circuit according to claim 18, further comprising a failure notification circuit that outputs an alarm signal in response to the failure. 20. The frame synchronization circuit outputs a transmission frame synchronization loss signal when the transmission frame synchronization signal cannot be detected, and outputs a reception frame synchronization loss signal when the reception frame synchronization signal cannot be detected. 17. The high-speed line termination circuit according to claim 16, wherein