JPS63229928A - Synchronizing protection circuit - Google Patents

Abstract

PURPOSE:To attain the protection of plural reception data without increasing the circuit scale by storing the count of a frame counter with respect to the received data and the history of the result of detection of a frame pattern. CONSTITUTION:A detection pulse generated by a frame pattern detection circuit 6 is sent as a timing pulse via a select means 7 and the count of a frame counter 5 is written in a storage/frame alarm means 71 by using the detection pulse. If no frame pattern is detected by the frame pattern detection circuit 6, when the count written precedingly in the storage frame alarm means 71 and the count of the frame counter 5 are coincident, a coincident pulse outputted from a comparison means 72 is outputted as a timing pulse via a select means 73. The history of the result of frame pattern detection is also written in the storage/frame alarm means 71 and the establishment of synchronization is discriminated based thereupon.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] In a synchronization protection circuit, a selection means controlled by a selection signal outputs either a detection pulse from a frame pattern detection circuit or a coincidence pulse from a comparison means as a timing pulse.

In addition, by updating the history of frame pattern detection results written in the memory/frame alarm means and sending the frame alarm signal and select signal using the updated history, multiple bursts can be generated without increasing the circuit scale. This allows for synchronization protection of received data.

[Industrial application field]

The present invention relates to an improvement of a synchronization protection circuit 9 used, for example, in a demand assignment time division multiplex radio transmission system.

For example, when communicating between a master station and multiple slave stations using a time-division multiplexing wireless transmission method, the master station uses time slot -1 (hereinafter referred to as
(abbreviated as TS-1) receives data from slave station-1,
In the TS-2, after taking out the received data from the slave station-2, frame patterns are detected from the received data, frame synchronization is established for each TS, and the data is taken out.

However, since the distances between the master station and the slave station are different, the phase of the received data shifts, and this phase shift must be absorbed individually in accordance with the reference timing within the receiving device.

Here, in response to the trend of miniaturization of devices, it is necessary that the size of the synchronization protection circuit does not increase even if the number of TSOs increases.

Note that the guard pits in FIG. 4 are provided to prevent signals from adjacent TSs from being affected even if a signal that should enter a predetermined TS protrudes to some extent.

[Conventional technology]

FIG. 5 is a block diagram of a conventional example, and FIG. 6 is an explanatory diagram of the operation of FIG. 5. In addition, 2 is a synchronization protection circuit.

It consists of 21 TS-1 phase protection circuits, 22 TS-2 phase protection circuits, etc. Below, synchronization protection circuit 2
The operation of FIG. 5 will be explained using FIG. 1 as an example and referring to FIG.

First, radio waves from the slave station-1 are received by a master station receiver (not shown), and the received data and received clock are extracted and added to the clock transfer circuit 1, where they are converted into received data synchronized with the internal clock. After that (this is called Cronk transfer), it is added to the TS-1 cycle protection circuit 21 (Fig. 6~
(See ■, ■).

Therefore, when the frame pattern generated internally in the frame pattern detecting section 211 matches the frame pattern in the received data, it is assumed that a frame pattern is detected.
Detection pulse -1 shown in the figure is applied to the synchronization protection section 212.

On the other hand, the frame counter 213 repeatedly counts one frame as shown in Figure 6-○, but after counting one frame (corresponding to FFF) it should be able to detect a frame pattern as shown in Figure 6-■. A window signal indicating timing is applied to the synchronization protection section 212, and a carry shown in FIG. 6-- is output.

If the detection pulse -1 is input while the window signal is being input, the synchronization protection unit 212 sends out the load pulse shown in FIG. Let it restart. Then, when the detection pulse -1 is detected while the window signal is being continuously input a predetermined number of times, synchronization is established, and from then on, the detection pulse -1 is sent to the selector 3.

Also, the frame pattern detection section 221 in the TS-2 cycle protection circuit 22. Synchronization protection unit 222. The frame counter 223 also operates in the same way as above to establish synchronization, but after synchronization is established, even if the detection pulse -2 is not sent once as shown in Figure 6--, synchronization is continued to be established by forward protection operation. Detection pulse -2 is sent to the selector 3 from the synchronization protection section at the timing of the window signal (see Figure 6--).

These detection pulses -1, detection pulse -2, etc. are applied to the selector, and depending on the select signal shown in Fig. 6-■, detection pulse -1 is applied when TS-1 is selected, and detection pulse -2 is applied when TS-2 is selected. is selected and the timing (hereinafter referred to as write reset pulse, W-Rese
(abbreviated as t)) is added to the frame aligner 4.

Therefore, the received data from each slave station sent out from the clock transfer circuit 1 is written to the frame aligner 4 with the beginning aligned by -Re5et, but these data are read out using the output of the frame counter 5. At reset (hereinafter abbreviated as +R-Reset), the data is read out at equal intervals and becomes output data (see FIG. 6 - [Phase]).

[Problem that the invention seeks to solve]

Here, the synchronization protection of the reception data received via TS-1 is performed by the TS-1 period protection circuit, and the synchronization protection of the reception data received through TS-2 is performed by the TS-2 synchronization protection circuit. Since each TS has a TS synchronization protection circuit, as the number of TSs increases, the scale of the TS synchronization protection circuit increases accordingly.

[Means for solving problems]

The above problem can be solved by a synchronization protection circuit as shown in FIG.

Here, 71 writes the count value of the frame counter with the detection pulse, reads out the previously written count value, and adds the latest frame pattern detection result to the written history of frame pattern detection results up to the previous time. Update.

A memory/frame alarm means 72 sends out a frame alarm signal and a selection signal using the updated history, and 72 is a memory/frame alarm means that sends out a frame alarm signal and a selection signal. This is a comparison means that outputs a defeat pulse.

Further, 73 is a selection means for selecting either the detection pulse or the coincidence pulse in response to the input selection signal and outputting the selected pulse as the timing pulse.

[Effect]

In the present invention, when a frame pattern is detected from received data, a detection pulse generated by the frame pattern detection circuit 6 is sent out as a timing pulse via the selection means 73, and the count value of the frame counter 5 is stored using this detection pulse. -Write to frame alarm means 71.

However, if the detection is not possible, the matching pulse outputted from the comparison means 72 when the count value written in the memory/frame alarm means last time matches the count value of the frame counter is sent to the selection means 73 as a timing pulse. is output.

Furthermore, the history of frame pattern detection results is also written in the memory/frame alarm means 7, and the history is updated by adding the latest frame pattern detection results to this, and frame synchronization is established based on this. After determining this, a selection signal corresponding to the frame pattern detection result is sent to the selection means 73.

That is, by storing the frame counter count value and the history of frame pattern detection results for data received using each time slot in the storage/frame alarm means, multiple pieces of received data can be protected without increasing the circuit size. I can do it.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of FIG. 2. The symbols on the left are the waveforms of the portions with the same symbols in FIG. The same reference numerals indicate the same objects throughout the drawings. Hereinafter, the operation of FIG. 2 will be explained with reference to FIG. 3 assuming that data is received via TS-1.

First, the received data is transferred from the received clock to the internal clock by the clock transfer circuit 1, and then the frame pattern in the received data is detected by the frame pattern detection circuit 6, and a detected pulse is sent from there to the RAM 711. It is sent to the status register 712 and the selector 731 (see FIG. 3 - ■ to ■).

Therefore, with this detection pulse, frame 11 is stored in RAM 711.
The count value of the counter 5 is written, and the count value of the frame counter written last time is written to the comparator 72.
Added to 1. The count value from the frame counter is also added here, so 2
When the two count values match, a match pulse is sent to selector 7.
31 (see Figure 3-■, ■-■).

On the other hand, the status register 712 updates the history by adding the current frame pattern detection result to the history of the previous frame pattern detection results read from the RAM 721, and writes it to the RAM again. (See Figure 3-■).

After the frame alarm detection circuit determines that frame synchronization has been established based on the updated history, when a detection pulse is sent out, the signal goes to the L level, for example, as shown in Figure 3-■, and when the detection pulse is not sent out, it goes to the H level. selector 73
Send to 1. Note that when it is determined that frame synchronization has been lost, a frame alarm is sent out and the select signal is fixed at level 11.

The selector 73 applies a detection pulse in the former case and a coincidence pulse as W-Reset in the latter case to the frame aligner.

Therefore, the received data that has undergone clock transfer is WR
-The beginning is aligned by eset and the frame aligner 4
The data is read out at regular intervals using the R-Reset generated using the frame counter 5, and becomes output data (see FIG. 3-2).

That is, by writing the count value of the frame counter when the detection pulse for each slave station was sent and the history of frame pattern detection results in RAM and updating these, multiple Since synchronization protection for data received via TS can be achieved with the same circuit, the circuit size does not increase even if the number of TS increases.

〔Effect of the invention〕

As described in detail above, according to the present invention, there is an effect that the circuit scale does not increase even if the TS increases.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is an explanatory diagram of the operation of Fig. 2, Fig. 4 is a frame formant example, and Fig. 5 is a conventional example. Example block diagram FIG. 6 is an explanatory diagram of the operation of FIG. 5. In the figure, 5 is a frame counter, 6 is a frame pattern detection circuit, 7 is a synchronization protection circuit, 71 is a storage/frame alarm means, 72 is a comparison means, and 73 is a selection means. Mizukin “Soil Principle Block 1st Threshold”

Claims (1)

[Claims] A frame pattern detection circuit (6) that sends out a detection pulse when a frame pattern is detected from received data transmitted using a time division multiplex transmission method, and a frame counter (5) that counts one frame. , a frame synchronization circuit including a synchronization protection circuit (7) that transmits a timing pulse for absorbing synchronization protection and a phase shift of the received data using the frame pattern detection circuit and the output of a frame counter; Writes the count value of the frame counter (5) with a pulse, reads the previously written count value, and updates the history by adding the latest frame pattern detection result to the history of frame pattern detection results written up to the previous time. and a storage/frame alarm means (71) that sends out a frame alarm signal and a selection signal using the updated history; Comparing means (72) that outputs a matching pulse when the count value matches; and Selecting means (72) that selects either the detection pulse or the matching pulse in response to the input select signal and outputs it as the timing pulse. 73) A synchronization protection circuit comprising: