JP3107995B2 - Synchronizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing device for synchronizing a receiver with a transmitter in digital radio communication.

[0002]

2. Description of the Related Art When performing wireless communication, it is necessary to synchronize between a transmitter and a receiver. Therefore, the transmitting side inserts a known pattern into the transmission sequence, obtains a correlation on the receiving side, and determines a time having a high correlation as a known pattern reception time, thereby acquiring synchronization.

FIG. 5 shows a configuration of a conventional synchronizer.
1 is a correlator, 502 is a synchronization determination circuit , and 503 is a memory . 504 is an orthogonal component of the received wave, and 505 is
It has the same phase component of the received wave.

FIG. 6 shows a frame format of a transmission signal, where 601 is data, 602 is a synchronization word, and 603 is data. Here, a synchronization word 602, which is a known pattern for achieving synchronization, is arranged at the center of the transmission signal. The symbol length is M symbols, where M = 10
It is. Usually, this known pattern is sometimes called a synchronization symbol in addition to the synchronization word.

[0005] The memory 503 stores a synchronization word s of a desired wave.
wl₁, Swl_Two, ..., swl _MIs saved. s
wl_XIs the in-phase component of the sync word of the desired wave of the x symbol
And a set of orthogonal components, represented here as complex numbers
You.

FIG. 7 shows a configuration example of the correlator 501. The correlator 501 outputs the quadrature component 504 of the A / D-converted received wave.
And a shift register 701 in which the in-phase component 505 is stored by the synchronization word length. At time T, the shift register 701 stores N pieces of received data r _{T-N + 1} , r _{T-N + 2} , r _T from time T−N + 1 to T. r _T is the quadrature component 504 and the in-phase component 505 of the received wave at time T
Are represented here as complex numbers. The complex multiplier 702 stores the content of the shift register 701 (the synchronization word of the received desired wave) and the content of the memory 703 (the memory 50).
3) and the result is input to an adder 704, which outputs a correlation value s.

[0007]

(Equation 1)

The correlation value s indicates how similar the waveform of the synchronization word for M symbols is to the waveform of the received signal. The more similar the waveforms are, the closer to 1 becomes, and when they completely match, 1 become. Conversely, if the waveforms are not similar, the closer they are, the closer to zero. By processing to correlate with the received waveform,
If the correlation value is high, it can be determined that the synchronization word has been received.

The synchronization determination circuit 502 determines whether or not it is a synchronization pulse reception time based on the output of the correlator 501. FIG.
Shows the output waveform of the correlator 501, and the horizontal axis indicates time, indicating the reception time of the synchronization word in one frame. Here, it is the time at which the synchronization word is received at time kT. T is a sampling interval. The vertical axis represents the correlation value, and the correlation value is high near the synchronization word. Thereafter, there is a method of not accumulating the correlation values, or a method of accumulating the correlation values. Here, the method of accumulating the correlation values will be described as an example. Since the correlation value may be high even at times other than the synchronization word reception time due to the influence of noise and fading, it is determined by the threshold value th1. The error is averaged out by adding. FIG.
Indicates the cumulative addition result. The horizontal axis represents time in one frame. When the accumulated value exceeds the threshold value th2, it is determined that the synchronization word has been received at this time.

[0010]

SUMMARY OF THE INVENTION In a digital radio communication system to which the present invention is applied, a known pattern is inserted into a transmission signal for transmission, and a cell adjacent to a base station or a mobile station for transmitting a desired signal is transmitted. In the case where the desired signal is transmitted at the same frequency by inserting a known pattern different from the desired signal, an interference wave exists. From the viewpoint of frequency utilization efficiency, it is desirable that the same frequency can be used in adjacent cells. However, in the above-described conventional configuration, there is a problem that it takes a long time to acquire correct synchronization when the influence of the interference wave is large.

The present invention solves such a conventional problem, in which signals are transmitted from different transmitters at the same timing and at the same frequency, and different known patterns are included in the transmission signals to synchronize each other. It is an object of the present invention to provide a synchronizing device that can correctly and quickly synchronize at a receiving side even in the presence of an interference wave in a wireless system that inserts and transmits.

[0012]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a first correlation means for correlating a received signal with a known pattern of a desired wave; Second correlation means for correlating the wave with a known pattern;
To synchronize determined from the correlation values output from the first and second correlation means, synchronization is detected in any preceding
And a synchronization determining means for determining that synchronization has been established in such a case .

[0013]

According to the present invention, according to the above configuration, when sampling is performed at a frequency higher than the symbol rate and a correlation with a known pattern stored in the receiver in advance is obtained,
By taking advantage of the fact that the correlation is highest at the optimal sampling point, by correlating with both the desired wave and the interference wave patterns, even if either the desired wave or the interference wave is affected by fading, The correlation can be obtained by one of the waves, and the time until synchronization is obtained can be reduced.

[0014]

【Example】

(Embodiment 1) FIG. 1 shows the configuration of a synchronization apparatus according to a first embodiment of the present invention. A and B are two different transmitters that transmit signals at the same timing and at the same frequency and insert a known pattern into the transmission signal for synchronization, and transmit signals A and B, respectively. wave,
The signal transmitted from the transmitter B is an interference wave. In FIG. 1, reference numeral 101 denotes a correlator A for correlating with the synchronization word from the transmitter A, and reference numeral 102 denotes a memory A for storing the synchronization word of the transmitter A. Reference numeral 103 denotes a correlator B for correlating with the synchronization word from the transmitter B, and reference numeral 104 denotes a memory B for storing the synchronization word from the correlator B. A synchronization determination unit 105 performs synchronization determination based on a correlation value with the synchronization word of the transmitter A, and performs synchronization determination based on a correlation value with the synchronization word of the transmitter B, and determines a synchronization detection first as synchronization establishment. It is a determination circuit. Reference numeral 106 denotes a clock pulse serving as a reference for operating the correlators 101 and 103 and the synchronization determination circuit 105; 107, a quadrature component of the received wave; and 108, an in-phase component of the received wave.

The operation of the synchronizer configured as described above will be described below with reference to the block diagram of FIG. 1 and the frame format diagram of FIG. The frame format of the transmission signal in this embodiment is the same as that of the conventional example shown in FIG. 6, and a synchronization word 602, which is a known pattern for achieving synchronization, is arranged at the center of the transmission signal. Before or after the data 603.

The memories 102 and 104 store synchronization words (here, M symbols) sw1 ₁ , sw1 ₂ ,..., Sw1 _M , and sw2 of the desired wave and the interference wave, respectively.
₁ , sw2 ₂ ,..., Sw2 _M are stored. sw1
_X and sw2 _X are sets of the in-phase component and the quadrature component of the synchronization word of the desired wave and the interference wave of the x-th symbol, respectively, and are expressed here as complex numbers.

The configuration of the correlator 101 is the same as the configuration of the conventional correlator shown in FIG. The correlator 101 has an A / D
It has a shift register 701 that stores the quadrature component and the in-phase component of the converted received wave by the synchronization word length. This shift register 701 can be shared with the correlator 103. At time T, the shift register 701 stores N pieces of received data r from time T−N + 1 to T.
_{T-N + 1} , r _{T-N + 2} , r _T are stored. r _T is a set of the in-phase component and the quadrature component of the received signal at time T, and is represented here as a complex number. The complex multiplier 702 is
A complex operation is performed on the contents of the shift register 701 (the received synchronization word of the desired wave) and the contents of the memory 703 (the synchronization word of the desired wave transferred from the memory 102), and the result is input to the adder 704. 704 outputs a correlation value s1.

[0018]

(Equation 2) The correlation value s1 indicates how similar the waveform of the synchronization word of the desired signal of M symbols is to the waveform of the received signal. The more similar the waveforms are, the closer to 1 becomes, and when they completely match, 1 become. Conversely, if the waveforms are not similar, the closer they are, the closer to zero. By performing the correlation with the received waveform, if the time has a high correlation value, it can be determined that the synchronization word has been received.

The configuration of the correlator 103 is the same as that of the conventional correlator shown in FIG. The correlator 103 has a shift register 701 in which the quadrature component and the in-phase component of the A / D converted received wave are stored for a synchronization word length. This shift register 701 can be shared with the correlator 101. At time T, the shift register 701 stores N pieces of received data r _{T-N + 1} , r _T from time T−N + 1 to T.
_{T-N + 2,} r _T is stored. r _T is a set of the in-phase component and the quadrature component of the received signal at time T, and is represented here as a complex number. The complex multiplier 702 performs a complex operation on the content of the shift register 701 (the synchronization word of the received interference wave) and the content of the memory 703 (the synchronization word of the interference wave transferred from the memory 104), and adds the result to an adder 704.
, And the adder 704 outputs a correlation value s2.

[0020]

(Equation 3)

The synchronization determination circuit 105 determines whether or not it is the synchronization word reception time based on the inputs from the correlators 101 and 103. For example, when a high correlation value is obtained early from either the correlator 101 or the correlator 103, it is determined to be the synchronization word reception time.

FIG. 2 shows a synchronization judgment circuit 10 in this embodiment.
5 shows the configuration of FIG. 2, reference numeral 201 denotes an OR circuit; 202, an address counter; 203, a latch circuit; and 204, a comparator.

Next, the operation of the synchronization determination circuit in this embodiment will be described. The inputs from the correlator 101 and the correlator 103 are supplied to the input of the OR circuit 201, and the sampling clock is supplied to the address counter 202. The latch circuit 203 stores the value of the address counter 202 when the output of the OR circuit 201 becomes 1 for the first time. Then, the comparator 204 compares the value of the address counter 202 with the value stored in the latch circuit 203. If the values match, the comparator 204 determines 1 as the synchronization establishment time, and outputs 0 if they do not match.

As described above, according to the present embodiment, the synchronization can be determined at higher speed by correlating not only the synchronization word of the desired wave but also the synchronization word of the interference wave.

(Embodiment 2) Next, a second embodiment of the present invention will be described. The synchronization determination circuit in the first embodiment may erroneously determine the synchronization word reception time due to the effects of fading and noise. In this embodiment, the effects of noise and fading are averaged and eliminated by accumulative addition. The overall configuration of the synchronization device according to the present embodiment is the same as the configuration of the synchronization device according to the first embodiment shown in FIG. 1, and the difference is the configuration of the synchronization determination circuit.

Hereinafter, only a synchronization determination circuit different from the first embodiment will be described. FIG. 3 shows the configuration of the synchronization determination circuit in the present embodiment.
3 to determine whether or not it is the synchronization word reception time,
When the time is determined to be the synchronization word reception time, 1 is output, and when it is determined that the time is not the synchronization word reception time, 0 is output.

In FIG. 3, reference numeral 301 denotes a memory A, 302
Is a memory B, 303 is an adder A, 304 is an adder B, 3
05 is a threshold value judgment circuit A, 306 is a threshold value judgment circuit B, 307 is an address counter, 308 is a logical sum circuit,
309 is a latch circuit, and 310 is a comparator.

Next, the operation of the synchronization determination circuit in this embodiment will be described. Memory 301 and memory 302
Saves a frame period when the synchronization word has one frame period, and stores a cumulative value of correlation values for each sampling time during the slot period when the synchronization word is for each slot. At this time, there are various methods such as directly accumulating the correlation value, accumulating by threshold value judgment as shown in FIG. 8, and accumulating through a limiter assuming that a certain value or less is regarded as 0. Here, the threshold value is determined and accumulated. The adder 303 adds the value of the memory 301 and the input from the correlator 101 that has been newly input, and stores it in the memory 301 again.
Output to the threshold determination circuit 305. The adder 304
The value of the memory 302 and the newly input input from the correlator 103 are added and stored in the memory 302 again, and output to the threshold value determination circuit 306.

The threshold value judgment circuit 305 and the threshold value judgment circuit 306 output 1 when the accumulated value is equal to or larger than the threshold value th2 of FIG.
If it is smaller than 0, it outputs 0.

The address counter 307 changes at each sampling clock timing, and is reset every frame period when the synchronization word is one frame period, and is reset every slot period when the synchronization word is one slot. The OR circuit 308 outputs 1 when the value of the threshold value judgment circuit 305 is 1 and the value of the threshold value judgment circuit 306 is 1, and the value of the threshold value judgment circuit 305 is 0 or the threshold value. When the value of the value determination circuit 306 is 0, 0 is output. Latch circuit 30
Reference numeral 9 stores the value of the address counter when the input from the OR circuit 308 becomes 1 for the first time. Comparator 310
Compares the value of the address counter 307 representing the current time with the output of the latch circuit 309 storing the time determined to be the synchronization word reception time, and outputs 1 if they match and 0 if they do not match .

As described above, according to the present embodiment, the effect of noise and fading is reduced, but the synchronization is correctly determined, although the speed is slightly reduced by cumulatively adding the correlation values of the desired wave and the interference wave. be able to.

(Embodiment 3) Next, a third embodiment of the present invention will be described. The configuration of the synchronizer in the present embodiment is the same as that of the synchronizer in the first embodiment shown in FIG. 1, and the difference lies in the configuration of the synchronization determination circuit.

Hereinafter, a synchronization determination circuit different from the first embodiment will be described. FIG. 4 shows the configuration of the synchronization determination circuit in this embodiment. 4, reference numeral 401 denotes a memory, 402 denotes an OR circuit, 403 denotes an adder, 404 denotes a threshold value determination circuit, 405 denotes an address counter, 406 denotes a latch circuit, and 407 denotes a comparator.

Next, the operation of the synchronization determination circuit in this embodiment will be described. The memory 401 has a synchronization word of 1
In the case of the frame period, the frame period is stored. When the synchronization word is for each slot, the accumulated value of the correlation value threshold value determination result for each sample time in the slot period is stored. The OR circuit 402 receives the input from the correlator 101 or the correlator 10
When any of the inputs from 3 is 1, 1 is output, and when the input from the correlator 101 is 0 or the input from the correlator 102 is 0, 0 is output. The adder 403 accumulatively adds the value of the memory 401 and the newly inputted input from the OR circuit 402, stores the result again in the memory 401, and outputs the result to the threshold value determination circuit 404.

The threshold value judging circuit 404 outputs 1 when the accumulated value is equal to or larger than the threshold value th2 in FIG. 9, and outputs 0 when the accumulated value is smaller than the threshold value th2 in FIG.
The address counter 405 changes every timing of the sampling clock, and is reset every frame period when the synchronization word is one frame period, and is reset every slot period when the synchronization word is one slot. Latch circuit 406
Stores the value of the address counter 405 when the input from the threshold determination circuit 404 becomes 1 for the first time. The comparator 407 compares the value of the address counter 405 indicating the current time with the output of the latch circuit 406 storing the time determined as the synchronization word reception time.
If they do not match, 0 is output.

As described above, according to the present embodiment, the same effect as that of the second embodiment can be obtained by a smaller circuit by accumulating the correlation value of the desired wave and the interference wave based on the synchronization word as a logical sum. .

[0037]

According to the present invention, as is apparent from the above embodiment, the first correlation means for correlating a received signal with a known pattern of a desired wave, and the known correlation of an interference wave with the received signal. and second correlation means for correlating the in pattern, performs synchronous determined from the correlation values output from the first and second correlation means, determines that the establishment of synchronization when synchronization to any previously has been detected Since the synchronization determination means is provided, even if one of the desired wave and the interference wave is affected by fading, it is possible to reduce the time until synchronization is obtained by obtaining correlation with the other wave. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram of a synchronization device according to each embodiment of the present invention.

FIG. 2 is a block diagram of a synchronization determination circuit according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a synchronization determination circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a synchronization determination circuit according to a third embodiment of the present invention.

FIG. 5 is a block diagram of a synchronization device in a conventional example.

FIG. 6 is a diagram illustrating a frame format of a transmission signal.

FIG. 7 is a block diagram of a correlator.

FIG. 8 is an output characteristic diagram of a correlator.

FIG. 9 is an output characteristic diagram of a cumulative result of correlator output.

[Explanation of symbols]

 101 Correlator A 102 Memory A 103 Correlator B 104 Memory B 105 Synchronization determination circuit 106 Clock pulse 107 Quadrature component of received wave 108 In-phase component of received wave 201 OR circuit 202 Latch circuit 203 Address counter 204 Comparator 301 Memory A 302 Memory B 303 Adder A 304 Adder B 305 Threshold judgment circuit A 306 Threshold judgment circuit B 307 Address counter 308 OR circuit 309 Latch circuit 310 Comparator 401 Memory 402 OR circuit 403 Adder 404 Threshold value Judgment circuit 405 Address counter 406 Latch circuit 407 Comparator

Claims (4)

(57) [Claims] 1. A synchronizer on a receiving side in a wireless system that transmits signals from different transmitters at the same timing and the same frequency, and inserts different known patterns into a transmission signal for synchronization. Is the first to correlate the received signal with the known pattern of the desired wave.
And correlation means, a second correlation means for correlating the known pattern of interference to the received signal, performs synchronization determination from the correlation values output from the first and second correlation means, either synchronization device and a synchronization determination means determines that the establishment of synchronization when it is detected synchronized to the pressurized destination. 2. A synchronization determination means ORs correlation values output from the first and second correlation means, have
2. The synchronizing device according to claim 1, further comprising: means for judging a synchronization establishment time when synchronization can be obtained earlier. 3. The synchronization judging means for accumulating the first correlation value outputted from the first correlating means for each frame or slot time, and the synchronizing judging means for outputting the first correlation value outputted from the second correlating means. A second adding means for cumulatively adding the second correlation value for each frame or slot time, and a first threshold value determining means for determining a synchronization acquisition by threshold value determination for the first correlation value. a second threshold determining means for determining synchronization acquisition by the threshold determination with respect to the second correlation value, a logical oR of the outputs of the first and second threshold determination means, either 2. The synchronizing device according to claim 1, further comprising: means for judging the synchronization establishment time when the synchronization has been obtained earlier. 4. A synchronization determining means for cumulatively adding the logical sum of the correlation values output from the first and second correlation means for each frame or slot time, and a threshold value for the cumulative addition result. and threshold determining means for determining synchronization acquisition by determining, could any previously synchronization acquisition place
2. The synchronizing device according to claim 1, further comprising: means for judging a synchronization establishment time.