JP2001119368A - Receiver, receiving method and medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speedily and surely detect a synchronizing signal when detecting the initial synchronizing signal and to highly accurately hold detected synchronizing timing. SOLUTION: A threshold value for detecting the synchronizing signal is set to a default value, the width of a window for detecting the synchronizing signal is set to a default value, the detecting state of the synchronizing signal is detected and corresponding to the detected result, the default value of the threshold value and the default value of the window width are controlled until they reach optimal values. Besides, cyclic estimate synchronizing timing is generated from acquired initial synchronism, the synchronizing signal is detected at such estimate synchronizing timing, the error of estimate synchronizing timing is corrected, demodulation is performed synchronously with synchronizing timing, an error rate at the time of that demodulation is calculated, it is discriminated corresponding to the error rate whether estimate synchronizing timing is correct or not and when the discrimination shows an error, execution is started from a procedure for acquiring initial synchronism while in the other case, procedures after the cyclic generation of estimate synchronizing timing are repeated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a receiving apparatus having a function of detecting or holding a synchronization signal periodically included in a transmission signal, a receiving method thereof, and a program for applying the receiving method. Regarding the medium.

[0002]

2. Description of the Related Art Conventionally, in a communication device constituting a communication network such as wireless communication, it has been important to acquire synchronization in order to accurately demodulate received information on a receiving side.

For this reason, the communication apparatus always includes a synchronization processing unit for acquiring the synchronization in this way and holding the synchronization thereafter. A general synchronization processing unit detects a synchronization signal at the start of communication and acquires synchronization. The acquired synchronization is held by the synchronization holding unit, and a synchronization timing is generated. The synchronization holding unit performs a process of holding the synchronization based on the feedback information of the synchronization timing. A demodulation timing is generated from the synchronization timing, and demodulation processing is performed in the reception data demodulation unit after the synchronization processing unit based on the demodulation timing.

[0004]

However, the conventional signal receiving apparatus has a problem that synchronization cannot be quickly maintained at the time of initial synchronization.

[0005] Further, in the conventional receiving apparatus, there is a problem that once synchronization is maintained by the synchronization processing section, it is difficult to correct the synchronization timing.

[0006] In the synchronization processing section of the conventional receiving apparatus, synchronization is maintained by feedback information of only synchronization timing. For this reason, there is no means for reflecting the demodulation result by the processing unit after the synchronization processing unit, for example, the demodulation unit.

For example, if instantaneous interruption occurs in a wireless propagation environment during wireless communication and synchronization is maintained at a certain wrong timing, the demodulation result in the subsequent demodulation circuit will deteriorate. However, in the conventional communication device, since there is no means for reflecting the demodulation result by the demodulation unit, the synchronization timing cannot be corrected, and the synchronization holding function may not function correctly.

Thus, in a radio wave propagation environment,
If the radio wave is cut off for a certain period of time, it is necessary to use the synchronization holding function by some method, and the synchronization holding function needs to correct the synchronization timing according to the fluctuation of the propagation situation.

The present invention has been made in view of such circumstances, and a first object of the present invention is to detect a synchronization signal quickly and reliably when an initial synchronization signal is detected. .

A second object of the present invention is to maintain the detected synchronization timing with high accuracy.

[0011]

According to a first aspect of the present invention, there is provided a receiving apparatus comprising: a threshold setting unit for setting a threshold for detecting a synchronization signal included in a transmission signal to a default value; and a threshold setting unit for detecting the synchronization signal. A window setting means for setting the width of the window to a default value, a detection means for detecting a detection state of the synchronization signal, and a default threshold value set by the threshold setting means in accordance with a detection result of the detection means. And control means for controlling the value of the default window width set by the window setting means until the value becomes an optimum value.

According to the receiving apparatus having such a configuration, the threshold value and the width of the window are set for detecting the synchronization signal included in the transmission signal, the detection state of the synchronization signal is detected, and
According to the detection result, a receiving apparatus in which the threshold value and the width of the window are controlled until the optimum value is obtained is obtained.

In the signal receiving method of the first invention, a threshold value for detecting a synchronization signal included in a transmission signal is set to a default value, and a width of a window for detecting the synchronization signal is set to a default value. Then, the detection state of the synchronization signal is detected, and the control of controlling the default threshold value and the default window width value to the optimum value is performed in accordance with the detection result. Features.

According to the receiving method of such a procedure, a threshold value and a width of a window are set for detecting a synchronization signal included in a transmission signal, a detection state of the synchronization signal is detected, and a detection result corresponding to the detection result is obtained. Then, the threshold value and the width of the window are controlled until the optimum values are obtained.

According to a first aspect of the present invention, there is provided a medium program comprising: a threshold setting step of setting a threshold for detecting a synchronization signal included in a transmission signal to a default value; and a default width of a window for detecting the synchronization signal. A window setting step for setting a value of the threshold value, a detection step for detecting a detection state of the synchronization signal, and a default threshold value set by the processing of the threshold setting step in accordance with a detection result in the detection step; A control step of controlling the value of the default window width set by the processing of the setting step until the value becomes an optimum value.

By executing a program including such steps, a threshold value and a window width are set for detecting a synchronization signal included in a transmission signal, a detection state of the synchronization signal is detected, and the detection is performed. According to the result, the threshold value and the width of the window are controlled until the optimum value is obtained.

A receiving apparatus according to a second aspect of the present invention is a receiving apparatus having a function of detecting a synchronization signal included in a transmission signal in a predetermined synchronization and holding the synchronization signal, for a predetermined time for detecting the synchronization signal. When the width of the synchronization signal detection window is open, the synchronization signal detection means for detecting the synchronization signal from the received signal, the synchronization holding means for holding the synchronization acquired and generating the synchronization timing, and performing the demodulation Demodulation timing generation means for generating a demodulation timing from the synchronization timing, demodulation means for performing data demodulation at the demodulation timing and calculating an error rate indicating whether or not demodulation was correctly performed; and And a synchronization judging means for judging whether or not is correct and performing the behavior of the synchronization timing according to the judgment result. It is.

According to the receiver having the above configuration, when the synchronization signal detecting means detects the synchronization signal from the received OFDM signal when the synchronization signal detection window of a predetermined time width for performing the synchronization signal detection is opened, the synchronization signal is detected. The holding unit generates a synchronization timing based on the detected synchronization signal and holds the synchronization. The demodulation timing generation means generates a demodulation timing based on the synchronization timing output from the synchronization holding means, and sends it to the demodulation means. The demodulation means demodulates the data at the demodulation timing and calculates an error rate at the time of demodulation. The judging means calculates the error rate at the time of demodulation,
It is determined whether the synchronization timing is correct. If it is determined that the synchronization timing is incorrect, a process for correcting the synchronization timing is performed.

According to a second aspect of the present invention, in the receiving method for detecting and holding a synchronization signal generated at a predetermined cycle, a step of detecting a synchronization signal from a received signal to obtain an initial synchronization; A periodic estimated synchronization timing is generated from the initial synchronization, a synchronization signal is detected at the periodic estimated synchronization timing, an error of the estimated synchronization timing is corrected from the detected synchronization timing, and a demodulation timing is generated at the synchronization timing. Then, demodulation is performed at the demodulation timing, an error rate at the time of demodulation is calculated, and it is determined whether or not the estimated synchronization timing is a normal timing according to the error rate. From the step of acquiring the initial synchronization when the
In other cases, a procedure of repeating the procedure after generation of the periodic estimated synchronization timing is executed.

According to the receiving method of such a procedure, when the initial synchronization is obtained from the synchronization signal detected from the received OFDM signal, a periodic estimated synchronization timing is generated based on the initial synchronization. A synchronization signal is detected at a periodic estimated synchronization timing, and an error in the estimated synchronization timing is corrected based on the detection. Further, a demodulation timing is generated from the synchronization timing, and demodulation is performed in accordance with the demodulation timing. At the time of demodulation, the demodulation error rate is calculated. It is determined whether or not the estimated synchronization timing is a regular timing according to the error rate. When it is determined that the estimated synchronization timing is the normal timing, the estimated synchronization timing is held as it is, and the processing after the generation of the estimated synchronization timing is repeated. When it is determined that the estimated synchronization is incorrect, an initial synchronization acquisition unit for the synchronization signal is performed, and a new synchronization signal is acquired.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram of a receiving apparatus according to this embodiment. The receiving device here is used for, for example, terrestrial digital television broadcasting and mobile communication, and
This is a receiving apparatus that receives a transmission signal of the DM (Orthogonal Frequency Division Multiplex) method. Further, the modulation method of the transmission signal (OFDM segment) includes a differential QPSK (DQPSK (Differential
Quadrature Phase Shift Keying)) method is used. In the following description, the term “OFDM signal” indicates a signal modulated by the OFDM method.

A low noise amplifier (LNA)
ier) 2 amplifies the signal received via antenna 1;
This is supplied to the frequency conversion unit 3. The frequency conversion unit 3 is a DLL
(Delay Locked Loop) 11 multiplies the internal timing signal received from the low noise amplifier 2 by the received signal from the low noise amplifier 2 to convert the frequency of the received signal into a baseband signal. To supply.

The serial / parallel converter 4 converts the received signal from serial to parallel, and converts the signal into a fast Fourier transform (FFT).
er Transform)) 5. Fast Fourier transform unit 5
In order to demodulate the subcarrier symbols of the received signal, the received signal is Fourier-transformed in accordance with the demodulation timing signal input from the timing control unit 10, and the demodulated signal is supplied to the parallel / serial conversion unit 6. Serial converter 6
Converts the input signal into a serial signal and supplies the serial signal to the DQPSK demodulation unit 7. The DQPSK demodulation unit 7 demodulates a signal of each carrier modulated by the DQPSK method.

The correlation detection unit 8 calculates a cross-correlation value between the signal input from the frequency conversion unit 3 and a pattern of a synchronization signal stored in advance, and calculates the calculated cross-correlation threshold value.
A synchronization detection signal is generated in comparison with a preset threshold. The synchronization signal detected by the correlation detector 8 is OFD
This is a synchronization signal arranged in a predetermined section of a signal transmitted in the M system. The configuration of the correlation detection unit 8 will be described later.

The timer 9 generates a frame synchronization detection timing signal based on the synchronization detection signal and supplies it to the timing control unit 10. The timing control unit 10 supplies a frame synchronization detection timing signal to the DLL 11, generates a demodulation timing signal indicating the start timing of the fast Fourier transform, and supplies the demodulated timing signal to the fast Fourier transform unit 5. The DLL 11 generates an internal timing signal synchronized with the frame synchronization detection timing signal and supplies it to the frequency conversion unit 3.

FIG. 2 is a diagram showing an example of a configuration in which the correlation detecting section 8 detects a synchronization signal. An input terminal 201 has an OFD for frame synchronization detection prepared in advance in the receiving apparatus.
The real part of the M code is supplied to the shift register 202.
Also, the real part of the received signal obtained at the input terminal 211 is
The data is supplied to the shift register 212. This input terminal 211
Is supplied with a real component of the received signal frequency-converted by the frequency conversion unit 3.

Then, both shift registers 202 and 212
Is set to the multipliers 203a, 203b,.
n are multiplied individually by the respective multipliers 203a to 203
n is integrated by the integrator 204, and the correlation value Rx of the real part is
Get re Sum. The correlation value Rx re Sum of the real part is set as a value squared by the squaring circuit 205, and the square value is supplied to the adder 206.

Further, the imaginary part of the OFDM signal for frame synchronization detection prepared in the receiving apparatus obtained at the input terminal 231 is supplied to the shift register 232. Also,
The imaginary part of the received signal obtained at the input terminal 221 is supplied to the shift register 222. This input terminal 211 has
An imaginary component of the received signal that has been frequency-converted by the frequency converter 3 is supplied.

Then, both shift registers 222 and 232
Are set to the multipliers 225a, 225b,...
n, and each of the multipliers 225a to 225
n is integrated by the integrator 226, and the correlation value Rx of the imaginary part is obtained.
Get im Sum. The correlation value Rx im Sum of the imaginary part is set as a value squared by the squaring circuit 227, and the square value is supplied to the adder 206. The OFDM signals for frame synchronization detection obtained at the input terminals 201 and 231 are prepared in advance in storage means (not shown) in the receiving apparatus.
The synchronization signal transmitted as an OFDM signal from a base station or the like is the same data as the data before demodulation from the OFDM signal.

In the adder 206, the supplied correlation value of the real part and the correlation value of the imaginary part are added, and the correlation value Su of the received signal is added.
Get m Store. The correlation value Sum St obtained by the adder 206
ore supplies the divider 207.

The received data of the real part set in each stage of the shift register 212 is multiplied by the multipliers 213a to 213a.
3n and the adder 21 via the squaring circuits 214a to 214n.
5a to 215n, and receives the imaginary part received data set in each stage of the shift register 222 and converts the data into a multiplier 223a.
223n and squaring circuits 224a to 224n to adders 215a to 215n to add the real part received data and the imaginary part received data. And each adder 2
15a to 215n are added to the integrator 2
16 and integrated to obtain the received power RSSI Sum. The received power RSSI Sum obtained by the integrator 216 is divided by the divider 20
7

In the divider 207, the correlation value Su of the received signal is
m Store divided by the received power RSSI Sum and the solution CorF
(n) is obtained. That is, the CorF
Find (n).

[0034]

[Equation 1] CorF (n) = Sum Store / RSSI Sum

The obtained value CorF (n) is calculated by the comparator 20
8 and is compared with a threshold value TH which is preset and stored in the receiving device and obtained at the terminal 209.
Here, CorF (n) ≧ threshold value TH and CorF
When the maximum value of (n) is detected, the frame synchronization output POFD
“H” data is output from the terminal 210 as M Cor OUT. If CorF (n) <threshold value TH, “L” data is output from terminal 210. The frame synchronization output obtained at the terminal 210 is supplied as a synchronization detection signal to a subsequent circuit (in this case, DLL 11).

FIG. 3 is a block diagram showing the configuration of the DLL 11.

The frame synchronization detection timing signal supplied from the timing control unit 10 is input to the frame period error calculation unit 21 of the DLL 11, and the phase difference from the internal timing signal generated by the numerical control unit 24 is measured. The weighting unit 22 performs weighting by multiplying the phase difference input from the numerical control unit 21 by a predetermined coefficient. The loop filter 23 extracts a low-frequency component of the signal output by the weighting unit 22 and outputs the extracted low-frequency component to the numerical control unit 24. The numerical controller 24 generates a pulse having a phase corresponding to the signal from the loop filter 23, supplies the pulse to the frequency converter 3 in FIG. 1, and feeds it back to the frame period error calculator 21.

Next, referring to the flowchart of FIG.
The operation of the receiving device of the present example will be described.

First, in step S1, the correlation detector 8 sets a default value L1 as a threshold for detecting a synchronization signal. This value L1 corresponds to the threshold value TH obtained at the terminal 209 of the frame correlation detector shown in FIG. The reception signal received by the antenna 1 and amplified by the low noise amplifier 2 is frequency-converted by the frequency conversion unit 3 and input to the correlation detection unit 8. The correlation detection unit 8 calculates a cross-correlation value V between the input signal and a previously stored synchronization signal pattern. This cross-correlation value V corresponds to the frame synchronization output obtained at the terminal 210 of the frame correlation detector shown in FIG. The cross-correlation value V increases when the input signal includes a synchronization signal, and decreases when the input signal does not include a synchronization signal. As a result, the cross-correlation value V calculated by the correlation detection unit 8 changes over time, for example, as shown in FIG.

The synchronization signal is a unique signal, and there is no signal having the same pattern as the synchronization signal in the data signal. In the data signal, a signal having a pattern similar to the synchronization signal exists, but the cross-correlation value V2 of the signal with the pattern of the synchronization signal indicates the cross-correlation value V2 when the data signal contains the true synchronization signal. It becomes smaller than the correlation value V1. Therefore, the correlation detection unit 8 compares the cross-correlation value V with a predetermined threshold L, and outputs a synchronization signal detection signal to the timer 9 when the cross-correlation value V is larger than the threshold L.

If the value of the threshold value L is increased, the synchronization signal can be detected more accurately. However, since the received signal is affected by noise, the synchronization signal in the received signal may not always exactly match the pattern of the true synchronization signal. If the value of the threshold value L is too large, it becomes impossible to detect such a synchronization signal affected by noise.

Conversely, if the value of the threshold value L is too small, if a data signal different from the synchronization signal has a pattern similar to the synchronization signal due to noise, this is erroneously detected as a synchronization signal. become.

In the initial stage of synchronization signal detection, the threshold L
Is set to a small value, for example, a value L2 shown in FIG. 5, a cross-correlation value V2 at a timing that is not a true synchronization signal is erroneously detected as a synchronization signal, and
It takes time for L11 to lock to the synchronization signal. Therefore, the threshold value set as the default is set to a large value like the value L1.

In step S2, the correlation detecting section 8
It is determined whether or not the synchronization signal has been detected continuously for a predetermined number of times (for example, 250 times), and the detection of the synchronization signal is repeated until it is determined that the detection has been continuously performed 250 times. 25
If the synchronization signal is detected 0 times consecutively, the current threshold value L1 and the synchronization signal detection window width τ1 are set to DLL11.
Is a value sufficient to lock to the synchronization signal, so that step S7 for further improving the synchronization holding accuracy
Processing.

In step S7, the correlation detecting section 8
It is determined whether the current threshold value L1 and the synchronization signal detection window width τ1 are optimal values (for example, the threshold value L is 60% of the initial threshold value L1 and the synchronization signal detection width τ is 30 ppm). Default values L1 and τ1 of the threshold value L and the synchronization signal detection window width τ are set to large values in advance in order to improve the detection accuracy of the initial synchronization. Therefore, in order to improve the synchronization holding accuracy, it is necessary to optimize the threshold value L and the synchronization signal detection window width τ.

In step S7, the correlation detector 8 determines
If it is determined that the current threshold L and the synchronization signal detection window width τ are not optimal values, in step S8, the value of the threshold L is reduced to a smaller value, and the value of the synchronization signal detection window width τ is set to a smaller value. Then, the value of the damping factor that determines the response time of the loop filter 23 is set to a value that converges faster. Thereafter, the process returns to step S5, and the subsequent processes are repeated.

In order to maintain the synchronization signal detection accuracy while improving the synchronization holding accuracy, the correlation detection unit 8 decreases the threshold value L step by step and narrows the synchronization signal detection window width. The synchronization signal detection window width τ is 240 pp of the default value τ1.
m, for example, by 30 ppm,
It is narrowed to the optimum value of 30 ppm. As the threshold value L, a value (0.6L1) of 60% of the default value L1 is set as the optimum value, and is reduced until the threshold value L finally becomes the optimum value. When the threshold value L and the synchronization detection window width τ have reached the optimum values, the process is terminated. FIG. 6 shows an example of a relationship between a synchronization signal transmitted in a frame period (A in FIG. 6) and a synchronization signal detection window width τ (B in FIG. 6) set for detecting the synchronization signal. FIG.

FIG. 7 shows the relationship between the cross-correlation value V calculated by the correlation detector 8 and the threshold value L, and the relationship between the opening / closing timing of the synchronization signal detection window and the complementation of the synchronization signal.

Since the correlation detector 8 performs the process of detecting the synchronization signal only at the timing when the synchronization signal detection window is opened, the cross-correlation value V is set to a value V13 larger than the threshold L at the timing when the window is not opened. In such a case, erroneous detection can be avoided. Furthermore, since the numerical control unit 24 estimates the timing of the synchronization signal, even when the cross-correlation value V is a value V11 smaller than the threshold value L, the synchronization signal that should be undetected is complemented and the internal timing is corrected. A signal (synchronous signal) can be generated.

The series of processes described above can be executed by hardware, but can also be executed by software. When a series of processing is executed by software, a program constituting the software is executed by a computer incorporated in a signal receiving device as dedicated hardware, or various programs are installed by installing various programs. For example, it is installed in a general-purpose personal computer or the like that can execute the functions described above.

Next, referring to FIG. 8, a program for executing the above-described series of processes is installed in a computer, and a computer used for making the computer executable is a general-purpose personal computer. The following is an example of the case.

The program is, as shown in FIG.
Hard disk 102 or semiconductor memory 103 as a recording medium built in personal computer 101
Can be provided to the user in a state where it is installed in advance.

Alternatively, the program is as shown in FIG.
As shown in FIG.
1. CD-ROM (Compact Disk-Read Only Memory)
112, Magneto-Optical Disk (MO)
Disc 113, DVD (Digital VideoDisc or Dig)
ital Versatile Disc) 114, magnetic disk 115,
It can be temporarily or permanently stored in a recording medium such as the semiconductor memory 116 and provided as package software.

Further, as shown in FIG. 8C, the program is wirelessly transferred from the download site 121 to the personal computer 101 via the artificial satellite 122 for digital satellite broadcasting, a local area network, the Internet, or the like. Via the network 131 to the personal computer 101 by wire, and the personal computer 101 can store the data in a built-in hard disk or the like.

The medium in the present specification means a broad concept including all these media.

The personal computer 101 has, for example, a central control unit (CPU) 14 as shown in FIG.
1 is built in. The CPU 141 is connected to an input / output interface 145 via a bus 144. The CPU 141 receives a command from a user via an input unit 147 including a keyboard, a mouse, etc., via the input / output interface 145. And a ROM corresponding to the semiconductor memory 103 shown in FIG.
(Read Only Memory) 142 is executed. Alternatively, the CPU 141 may transfer the program stored in the hard disk 102 in advance from the satellite 122 or the network 131, receive the program by the communication unit 148, and
Programs installed on the drive or drive 14
9, floppy disk 111, CD-RO
The program read from the M112, the MO disk 113, the DVD 114, or the magnetic disk 115 and installed on the hard disk 102 is stored in a RAM.
(Random Access Memory) 143 and executed. Further, the CPU 141 outputs the processing result to a display unit 146 such as a liquid crystal display panel via the input / output interface 345 as necessary.

In this specification, the step of describing a program provided by a medium is not limited to processing performed in a time-series manner in the order described, but is not necessarily performed in a time-series manner. It also includes processes that are executed individually or individually.

In the above-described embodiment, the OFDM
As shown in FIG. 2, as a detection processing configuration of the synchronization signal transmitted as a signal in the correlation detection unit 8, each of a real component and an imaginary component of the received signal includes data prepared in advance in the receiving device. Although the correlation is detected by comparison, the correlation may be detected from only one of the components.

FIG. 10 is a diagram showing an example of a configuration in which the correlation detector 8 detects a frame correlation only from the correlation of the real component of the received signal. A real part of a previously prepared OFDM code for frame synchronization detection obtained at an input terminal 201 is supplied to a shift register 202. The real part of the received signal obtained at the input terminal 211 is supplied to the shift register 212. Then, the data set in each stage of both shift registers 202 and 212 is converted into multipliers 203a, 203b,.
, And the respective multipliers 203a to 203n
Is integrated by an integrator 204, and the correlation value Rx r of the real part is
Get e Sum. The correlation value Rx re Sum of the real part is defined as the value squared by the squaring circuit 205, and the correlation value Sum of the received signal is calculated.
Store is obtained, and the correlation value is supplied to the divider 207.

The received data of the real part set in each stage of the shift register 212 is multiplied by the multipliers 213a to 213a.
The signal is supplied to the squaring circuits 214a to 214n via 3n.
Then, the reception data output from each of the squaring circuits 214a to 214n is supplied to an integrator 216 to be integrated, and the reception power RS
Get SI Sum. The received power RSSISu obtained by the integrator 216
m is supplied to the divider 207.

In the divider 207, the correlation value Su of the received signal is
m Store divided by the received power RSSI Sum and the solution CorF
(n) is obtained. The obtained value CorF (n) is supplied to the comparator 208, which is set and stored in the terminal in advance and is supplied to the terminal 209.
, And a frame synchronization output POFDM Cor OUT as a comparison result is supplied from a terminal 210 to a subsequent circuit (DLL 11 in this example) as a synchronization detection signal.

As shown in FIG. 10, by adopting a configuration in which the frame correlation is detected from the processing of only the real components, the frame correlation can be detected more easily than in the configuration of FIG. 2 which also processes the imaginary components. become. However, as for the detection accuracy of the frame correlation, as shown in FIG. 2, when the detection is performed from both the real component and the imaginary component of the received signal, the frame correlation can be detected with higher accuracy.

In the above description, a signal modulated by the OFDM system is detected and processed as a synchronization signal included in the received signal. In the case of this signal, the processing can be performed by detecting the frame correlation in the same manner. For example, when the modulation scheme of the signal to be transmitted is the OFDM scheme, only the section of the synchronization signal is not an OFDM signal,
Even in the case of an M-sequence (Maximum Length Code) code, which is a pseudo-randomly set PN code sequence, frame correlation can be detected and processed in the same manner.

FIG. 11 shows a configuration example of a frame correlator that detects a synchronization signal (M-sequence data) from a received signal when the synchronization signal is M-sequence data. In the receiving device, the same data (PN code) as the M-sequence data to be transmitted is prepared in advance, and the real part of the prepared PN code for frame synchronization is input to the shift register 902 via the input terminal 901. To supply. Also, the input terminal 91
1 is converted to a shift register 91
Feed to 2. Then, both shift registers 902 and 91
2, the data set in each stage of the shift register is multiplied by multipliers 903a, 903b,.
3n, and the respective multipliers 903a to 903
3n is integrated by the integrator 904, and the correlation value of the real part is
Get Rx re Sum. The correlation value Rx re Sum of the real part is set as a value squared by the squaring circuit 905, and the square value is supplied to the adder 906.

The imaginary part of the PN code for frame synchronization prepared in advance in the receiving apparatus is supplied to the shift register 932 via the input terminal 931. Also, the input terminal 9
The imaginary part of the received signal obtained by the shift register 9
22. Then, both shift registers 922, 9
The data set in each of the 32 stages is multiplied by multipliers 925a, 925b,.
25n, and each multiplier 925a-9
The multiplied value of 25n is integrated by the integrator 926 to obtain a correlation value Rx im Sum of the imaginary part. The imaginary part correlation value Rx im Sum is supplied to the adder 906 as a value squared by the squaring circuit 927.

The adder 906 adds the supplied correlation value of the real part and the supplied correlation value of the imaginary part to obtain the correlation value Su of the received signal.
Get m Store. The correlation value Sum St obtained by the adder 906
ore supplies the divider 907.

The received data of the real part set in each stage of the shift register 912 is multiplied by the multipliers 913a to 913a.
3n and adders 91 via squaring circuits 914a to 914n.
5a to 915n, and receives the imaginary part of the received data set in each stage of the shift register 922 by using the multiplier 923a.
To 923n and squaring circuits 924a to 924n to adders 915a to 915n to add the real part received data and the imaginary part received data. And each adder 9
15a to 915n, and adds the received data to the integrator 9
16 and integrated to obtain the received power RSSI Sum. The received power RSSI Sum obtained by the integrator 916 is divided by the divider 90
7

In the divider 907, the correlation value Su of the received signal is
m Store divided by the received power RSSI Sum, and the solution Cor1
(n) is obtained. The equation for obtaining the solution Cor1 (n) is the operation of the equation (1) described above.

Then, the obtained value Cor1 (n) is supplied to a comparator 908 and compared with a threshold value TH which is preset and stored in the receiving device and obtained at a terminal 909. Here, Cor1 (n) ≧ threshold value TH and Co
When the maximum value of r1 (n) is detected, the frame synchronization output PP
“H” data is output from the terminal 910 as N Cor OUT. If Cor1 (n) <threshold value TH, “L” data is output from terminal 910. This frame synchronization output PPN Cor OUT is supplied as a synchronization detection signal to a subsequent circuit (DLL 11 in this example).

Next, a second embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIGS.

FIG. 12 is a block diagram of the receiving apparatus of this embodiment. The receiving device here is an OFDM (Orthogonal Frequ
This is a receiving apparatus that receives a transmission signal of the ency division multiplex (orthogonal frequency division multiplex) system. As a modulation method of a received signal (OFDM segment),
For example, differential QPSK (DQPSK (Differential Quadr
ature Phase Shift Keying)) method is used. Further, a signal transmitted by the OFDM method includes a synchronization signal according to a specific pattern in a frame cycle.

FIG. 12 is a block diagram showing an example of the configuration of the synchronization processing section of the receiving apparatus according to this embodiment. This receiving device includes a synchronization processing unit 300 that detects synchronization and maintains synchronization, and a demodulation unit 350 that performs demodulation and generates demodulation result information.

The synchronization processing section 300 detects a synchronization signal from a received signal, generates a synchronization timing and a demodulation timing, and performs processing for maintaining synchronization. Synchronization processing unit 30
0 indicates a synchronization signal detecting means 310 for detecting a synchronization signal from a received signal, a synchronization holding means 320 for holding the detected synchronization and generating a holding timing, a demodulation timing generating means 330 for generating a demodulation timing, And synchronization determination means 340 for determining whether or not is correct.

The synchronization signal detection means 310 has a synchronization signal detection window (hereinafter, referred to as a window) having a predetermined time width. This window is opened in accordance with the estimated synchronization timing generated by the synchronization holding unit 320, and a synchronization signal is detected while the window is open. In addition, when detecting that the synchronization timing is erroneous at the time of starting, the window width is infinite, or the window width is ignored, the initial synchronization is detected, and the synchronization is obtained.

The synchronization holding unit 320 performs a process of holding the synchronization acquired by the synchronization signal detecting unit 310 and generates a synchronization timing, for example, a delay lock loop (hereinafter, referred to as a delay lock loop).
DDL). The synchronization holding unit 320 estimates the next synchronization timing based on the periodicity of the synchronization signal. Further, the synchronization timing error is detected and corrected. Hereinafter, the synchronization timing estimated by the synchronization holding unit 320 is referred to as an estimated synchronization timing. Synchronization holding means 320
The estimated synchronization timing of the
Output to 0.

The demodulation timing generating means 330 generates a demodulation timing based on the synchronization timing.
Output to 50. The synchronization reverse unit 340 includes a demodulation unit 350
It is determined whether or not the synchronization timing is correct in accordance with the result of the demodulation error input, and predetermined processing is performed in accordance with the determination result. For example, the value of the demodulation error is smaller than a certain reference value,
And if it continues for a certain period of time, the synchronization timing is determined to be normal, and the value of the demodulation error exceeds a certain reference value.
And when it continues for a certain period, it is determined that the synchronization timing is wrong. In this way, when it is determined that the synchronization timing is normal, the set time of the window for detecting the synchronization signal is shortened. If it is determined that the synchronization timing is incorrect, the synchronization signal detection means 310 performs initial synchronization acquisition.

The demodulation 350 performs demodulation at a timing based on the demodulation timing signal generated by the synchronization processing section 300, and an error rate thereof, for example, a bit error rate (hereinafter referred to as BER)
Bit Error Data) is calculated.
The calculated RER is sent to the synchronization determination unit 340 of the synchronization processing unit 300.

As a configuration for detecting a synchronization signal in the synchronization signal detection means 310, for example, the frame correlator already described as the first embodiment can be applied. That is, when the synchronization signal is transmitted as an OFDM signal modulated by the OFDM method, the configuration shown in FIG. 2 (example of detecting from both the real component and the imaginary component) or the configuration shown in FIG. Example in which detection is performed only from components) can be applied. When only the section of the synchronization signal is transmitted as specific data (eg, M-sequence data) not modulated by the OFDM scheme, the configuration shown in FIG. 11 described above can be applied.

Next, the operation of the receiving apparatus of this embodiment will be described. When the device is started, an initial synchronization acquisition process is performed by the synchronization signal detecting means 310. At this time, the window is infinite or ignored, and a synchronization signal detection process is performed until initial synchronization is obtained. When a synchronization signal is detected, a synchronization detection signal is sent to the synchronization holding unit 320, and the window width is set to an initial value. The synchronization holding unit 320 pulls in the acquired synchronization timing. Using the periodicity of the synchronization signal,
Generate an estimated synchronization timing for the next cycle. At the estimated synchronization timing, a window having a predetermined window width is opened, a synchronization signal is detected by the synchronization signal detection unit 310, and is input to the synchronization holding unit 320. Based on this, the error of the synchronization timing is corrected. The generated synchronization timing is output to the demodulation timing generation means 330. Demodulation timing generation means 33
0 generates a demodulation timing and outputs it to the demodulation section 350.

The demodulation section 350 performs demodulation in accordance with the demodulation timing, and performs BER which is a data error rate.
(Bit error rate) is calculated, and synchronization determination means 340 is calculated.
Send to The synchronization determination means 340 determines whether the synchronization timing is correct based on the BER. When it is determined that the synchronization timing is correct for a predetermined period, the window width is reduced, that is, the set time for opening the window is shortened. If it is determined that the synchronization signal is incorrect, the synchronization holding unit 320
Is stopped, and the synchronization signal detecting means 310 is set to operate from the initial synchronization acquisition.

Further, a method for maintaining synchronization of the receiving apparatus of this embodiment will be described in detail. FIG. 13 is a flowchart showing the synchronization holding processing of the receiving apparatus of the present example. When the synchronization signal detection is started (step S310), an initial synchronization acquisition process is performed first (step S320). The initial synchronization acquisition process is performed until a synchronization signal is detected, a synchronization timing is generated based on the detected initial synchronization signal (step S460), and synchronization is maintained. Subsequently, a demodulation timing is generated from the synchronization timing (step S4).
70). In synchronization with the demodulation timing, demodulation and synchronization determination processing according to the error rate at the time of demodulation are performed (step S48).
0).

Thereafter, the result of the synchronization determination is checked (step S490). If it is determined that the synchronization timing is incorrect, the held synchronization timing is discarded and the processing from the initial synchronization acquisition processing (step S320) is started. Is performed. If the synchronization timing is determined to be correct, the held synchronization timing is continued. If continued, it is checked whether the estimated synchronization timing, which is the next synchronization timing calculated from the held synchronization timing, has been reached (step S410), and if not, the process S410 is repeated again. When the estimated synchronization timing is reached, a window having a predetermined window width opens,
A synchronization signal is detected (Step S420). Based on the detected synchronization signal, a synchronization timing error is detected (step S430), weighted according to the error (step S440), and a loop filter is set (step S450).

The adjustment of the synchronization timing is performed in this way, and the control waits for the next estimated synchronization timing again. At the same time, a synchronization timing is generated from the detected synchronization signal (step S460), and the synchronization is maintained. Subsequently, a demodulation timing is generated from the synchronization timing (Step S).
470). In synchronization with the demodulation timing, demodulation and synchronization determination processing according to the error rate at the time of demodulation are performed (step S4).
80). The synchronization determination result is checked (step S49)
0), if it is determined that the synchronization timing is incorrect, the held synchronization timing is discarded, and the processing from the initial synchronization acquisition processing (step S320) is performed. If it is determined that the synchronization timing is correct, the held synchronization timing is continued, and the process waits for the next estimated synchronization timing again.

Next, the initial synchronization acquisition processing will be described in detail. FIG. 14 is a flowchart of the initial synchronization acquisition procedure of the receiving apparatus of this example. When the initial synchronization acquisition process is started (step S321), the window width is set to the maximum value (step S322). Alternatively, the window width may be ignored or set to infinity. Sync signal is detected,
When initial synchronization is obtained (step S323), a window is set (step S324), the window width is set to an initial value (step S325), and the process ends (step S3).
26).

Next, the demodulation / synchronization determination processing will be described in detail. FIG. 15 is a flowchart of the demodulation / synchronization determination procedure of the receiving apparatus of this example. When demodulation / synchronization determination processing is started at the demodulation timing (step S481),
Demodulation is performed, and a data error rate (BER) at the time of demodulation is calculated (step S482). The calculated BER is a predetermined reference value (hereinafter referred to as BER). Is determined (step S48).
3).

BER is BER If TH or less, B
A counter that counts the event that the ER is below the reference value (hereinafter, referred to as Nok) is counted up by the following equation. Here, k is an integer representing an arbitrary period.

[0087]

## EQU2 ## Nok [k] = Nok [k-1] +1

A counter for counting the event that the BER exceeds the reference value (hereinafter referred to as Nber)
Is counted down as in the following equation.

[0089]

Nber [k] = Nok [k-1] -1

Subsequently, it is determined whether or not Nok exceeds a predetermined number (hereinafter, referred to as Nwin) representing window width adjustment synchronization for determining that the synchronization timing is correct and adjusting the window width (step S485). ). If not, the process ends (step S48B). Nok is N
If it exceeds win, that is, if it is determined that the synchronization timing is normal during the window width adjustment period, the window width is adjusted (step S486), and the window width is reduced. Subsequently, the synchronization timing normal status is output (step S487), and the process ends (step S48B).

BER is BER If it exceeds TH,
Nber is counted up as in the following equation.

[0092]

## EQU4 ## Nber [k] = Nok [k-1] +1

Also, Nok is cleared as in the following equation.

[0094]

[Equation 5] Nok = 0

Subsequently, Nber is a predetermined number (hereinafter referred to as Nber) for which it is determined that the synchronization timing error continues and it is necessary to acquire a new synchronization timing. TH)
Is checked (step S48).
8). If not, the process ends (step S
48B). Nber is Nber If TH has been exceeded, that is, if it is determined that the synchronization timing error has occurred a predetermined number of times, an initial synchronization acquisition request is made. In this case, a synchronization timing error status is output (step S48A), and the process ends (step S48B).
As a result, processing for detecting a new initial synchronization signal is performed in the subsequent processing.

As described above, a certain synchronization detection accuracy is compensated by the DDL or the like estimating the next synchronization timing based on the feedback information of the synchronization signal. further,
For example, if instantaneous interruptions occur frequently and the demodulation result deteriorates, it is possible to once return to the initial synchronization acquisition state based on the feedback information of the demodulation result and detect the correct synchronization timing again.

Next, a specific example of the operation of the receiving apparatus of this embodiment and a method of maintaining the synchronization will be described with reference to a synchronization detection state diagram.

First, complementation of the synchronization signal will be described.
FIG. 16 is a synchronization detection state diagram when the synchronization signal is supplemented by the receiving apparatus of this example. Usually, when the cross-correlation value exceeds the optimum correlation value, it is determined that a synchronization signal has been detected. A window opens in synchronization with the estimated synchronization timing of the synchronization holding unit (for example, DLL). At this time, if the cross-correlation value exceeds the optimum correlation value, it is determined that a synchronization signal has been detected. Further, even when the cross-correlation value falls below the optimum correlation value, it is determined that a synchronization signal has been detected by complementing the DLL, and the processing is continued. As described above, even when the synchronization signal falls below the optimum correlation value, the processing can be performed at a predetermined cycle. Of course, since the BER at the time of demodulation is ignored, if the synchronization signal is erroneous, it can be detected.

Next, prevention of erroneous detection by a window will be described. FIG. 17 is a synchronization detection state diagram of the receiving apparatus of the present example for preventing false detection of a synchronization signal. It is assumed that the cross-correlation value exceeds the optimum correlation value at a place other than the original synchronization signal. In the communication device according to the present invention, since the synchronization signal is detected in synchronization with the estimated synchronization timing calculated by the DLL, a frame exceeding the optimum correlation value that appears at a position where no synchronization signal is generated is not originally detected. . In this way, the detection window can prevent erroneous detection of the synchronization signal.

Next, a case where the synchronization is lost due to an instantaneous interruption will be described. FIG. 18 is a diagram illustrating the state of synchronization detection performed by the receiving apparatus of this example when a synchronization signal error occurs. An instantaneous interruption occurs, causing a difference between the synchronization timing of the partner apparatus and the synchronization timing of the own apparatus. At this time, if demodulation is performed based on the synchronization signal detected within the estimated synchronization timing window calculated by the DLL, the BER as a result of the demodulation deteriorates. Thus, a determination is made that a synchronization error has occurred, the window is expanded to a maximum value, and initial synchronization is obtained. When the initial synchronization is obtained, the synchronization timings match, and the demodulation result becomes good.

As described above, in order to determine that the synchronization timing detected within the estimated synchronization timing window by the synchronization holding means is not a regular synchronization timing, the value of the BER, which is information on the demodulation result, is used for the determination. If the demodulation result is good, the synchronization timing detected within the estimated synchronization timing window from the synchronization holding means is treated as normal synchronization timing. If the demodulation result continuously deteriorates a certain number of times from the certain value, it is assumed that the estimated synchronization timing from the synchronization holding means is incorrect, and the normal synchronization timing is detected again, starting from the initial synchronization detection procedure again. Correct the synchronization timing.

The above processing functions can be realized by a computer. In this case, the processing content of the function that the communication device should have is described in a program recorded on a computer-readable recording medium. Then, by executing this program on a computer, the above processing is realized on the computer. Examples of the computer-readable recording medium include a magnetic recording device and a semiconductor memory. If you want to distribute the market,
The program is stored and distributed in a portable recording medium such as a CD-ROM (Compact Disc Read Only Memory) or a floppy disk, or stored in a storage device of a computer connected via a network. It can also be transferred to a computer. When the program is executed by the computer, the program is stored in a hard disk device or the like in the computer, loaded into the main memory, and executed.

[0103]

The first invention (corresponding to the first embodiment)
According to the method, the threshold value and the width of the window for detecting the transmitted synchronization signal are controlled until the optimum value is obtained in accordance with the detection result of the synchronization signal. The synchronization signal can be detected, and the synchronization holding accuracy can be improved.

According to the second invention (corresponding to the second embodiment), when a synchronization signal included in a received signal is detected, a synchronization timing is generated from the detected synchronization signal, and synchronization is maintained. Data demodulation is performed at a demodulation timing based on the synchronization timing, and an error rate at the time of demodulation is calculated. Based on the error rate at the time of demodulation, it is determined whether or not the synchronization timing is correct. If it is determined that the synchronization timing is not correct, a process of correcting the synchronization timing is performed. As described above, according to the present invention, the correction processing of the synchronization timing is performed according to the demodulation result. Therefore, for example, even when an instantaneous interruption or the like occurs, it is possible to correct the synchronization to be accurately maintained. As a result, more accurate synchronization can be maintained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a signal receiving device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a frame correlation detection unit according to the first embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration example of a DLL according to the first embodiment of the present invention.

FIG. 4 is a flowchart for explaining an example of a synchronization signal detection procedure according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a synchronization signal and a cross-correlation value detected by a correlation detection unit in FIG. 2;

FIG. 6 is a diagram illustrating a synchronization signal detection window width.

FIG. 7 is a timing chart for explaining a detection result of a synchronization signal.

FIG. 8 is a diagram illustrating a medium.

FIG. 9 is a block diagram illustrating an example of a configuration of a personal computer.

FIG. 10 is a block diagram illustrating another configuration example of the frame correlation detection unit according to the first embodiment of the present invention.

FIG. 11 is a block diagram showing still another configuration example of the frame correlation detection unit according to the first embodiment of the present invention.

FIG. 12 is a block diagram of a synchronization processing unit of the receiving device according to the second embodiment of the present invention.

FIG. 13 is a flowchart of a synchronization holding unit of the receiving apparatus according to the second embodiment of the present invention.

FIG. 14 is a flowchart of an initial synchronization acquisition procedure of the receiving device according to the second embodiment of the present invention.

FIG. 15 is a flowchart of a demodulation / synchronization determination procedure of the receiving device according to the second embodiment of the present invention.

FIG. 16 is a diagram illustrating a state of synchronization detection at the time of complementing a synchronization signal in the receiving apparatus according to the second embodiment of the present invention.

FIG. 17 is a diagram illustrating a state of synchronization detection for preventing erroneous detection of a synchronization signal of the receiving apparatus according to the second embodiment of the present invention.

FIG. 18 is a diagram illustrating a synchronization detection state when a synchronization signal error occurs in the receiving device according to the second embodiment of the present invention.

[Explanation of symbols]

8 correlation detector, 9 timer, 10 timing controller, 11 DLL, 21 ‥‥ frame period error calculator,
22 ° weighting unit, 23 ° loop filter, 24 °
‥ Numerical control unit, 300: synchronization processing unit, 310: synchronization signal detection unit, 320: synchronization holding unit, 330: demodulation timing generation unit, 340: synchronization determination unit, 350: demodulation unit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Jun Iwasaki 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Sony Corporation F-term (reference) 5K014 AA01 BA01 EA07 EA08 GA02 HA05 HA10 5K022 DD01 DD13 DD17 DD19 DD33 DD42 5K047 AA02 AA03 BB01 GG34 HH15 HH21 KK04 LL15 MM12

Claims (22)

[Claims] 1. A threshold setting means for setting a threshold for detecting a synchronization signal included in a transmission signal to a default value, and a window setting for setting a width of a window for detecting the synchronization signal to a default value. Means, a detecting means for detecting a detection state of the synchronization signal, and a value of a default threshold value set by the threshold value setting means, and a value set by the window setting means, corresponding to a detection result of the detecting means. Control means for controlling a default window width value to an optimum value. 2. A synchronizing signal included in the transmission signal is O
The receiving device according to claim 1, wherein the receiving device is a signal modulated by an FDM method. 3. The synchronization signal included in the transmission signal is M
The receiving device according to claim 1, wherein the receiving device is a sequence signal. 4. The apparatus according to claim 1, wherein the control means controls the threshold value and the width of the window when a synchronization signal included in the transmission signal is continuously detected a predetermined number of times. Receiving device. 5. A method for setting a threshold value for detecting a synchronization signal included in a transmission signal to a default value, setting a width of a window for detecting the synchronization signal to a default value, and detecting the synchronization signal. A receiving method comprising: detecting a state; and controlling a value of the default threshold value and a value of a width of the default window in accordance with a result of the detection of the synchronization signal until an optimum value is obtained. 6. A synchronizing signal included in the transmission signal is O
The receiving method according to claim 5, wherein the signal is a signal modulated by the FDM method. 7. The synchronization signal included in the transmission signal is M
The reception method according to claim 5, wherein the reception method is a sequence signal. 8. A threshold setting step for setting a threshold for detecting a synchronization signal included in a transmission signal to a default value, and a window setting for setting a width of a window for detecting the synchronization signal to a default value. A detection step of detecting a detection state of the synchronization signal; a default threshold value set by the processing of the threshold setting step, in accordance with a detection result in the detection step; A control step of controlling a default window width value set by the processing until the window width value reaches an optimum value. 9. A receiving apparatus having a function of detecting a synchronization signal included in a transmission signal at a predetermined cycle and holding the synchronization signal, wherein a synchronization signal detection window having a predetermined time width for detecting the synchronization signal is provided. A synchronization signal detection unit for detecting a synchronization signal from a received signal when the synchronization signal is opened; a synchronization holding unit for generating synchronization timing while maintaining synchronization acquired by the synchronization signal detection unit; and a demodulation for demodulation Demodulation timing generation means for generating a timing from the synchronization timing, demodulation of data at the demodulation timing, and demodulation means for calculating an error rate indicating whether the demodulation has been correctly performed; and the synchronization timing from the error rate. And a synchronization determining means for determining whether or not is correct and correcting the synchronization timing according to the determination result. Characteristic receiving device. 10. The synchronization signal included in the transmission signal,
The receiving device according to claim 9, wherein the signal is a signal modulated by an OFDM method. 11. The synchronization detecting means receives the OFD signal
11. The synchronizing signal is detected from only one of a real component and an imaginary component of an M-system signal.
The communication device as described. 12. The synchronization signal included in the transmission signal,
The receiving apparatus according to claim 9, wherein the receiving apparatus is an M-sequence signal. 13. The synchronization signal detecting means detects a synchronization signal by setting the width of the synchronization signal detection window to a maximum value or ignoring the synchronization signal detection window at the time of initial synchronization acquisition for newly detecting synchronization. The receiving device according to claim 9, wherein: 14. The synchronous holding means estimates a next synchronization timing from an acquired synchronization signal, generates an estimated synchronization timing, and constitutes a delay lock loop for detecting and adjusting an error in the synchronization timing. The receiving device according to claim 9, wherein 15. The receiving apparatus according to claim 9, wherein said demodulation means calculates a bit error rate at the time of demodulation. 16. The synchronization determining means determines that the synchronization timing is incorrect when the error rate exceeds a predetermined value for a predetermined period, and shifts the apparatus to an initial synchronization acquisition operation. The receiving device according to claim 9. 17. The synchronization determining means further determines that the synchronization timing is normal when the error rate falls below a predetermined value for a predetermined period, and reduces the synchronization signal detection window width. The receiving device according to claim 9. 18. A receiving method for detecting a synchronization signal included in a transmission signal at a predetermined cycle and holding the synchronization signal, wherein a step of detecting the synchronization signal from the received signal to obtain initial synchronization; Generating a periodic estimated synchronization timing from the initial synchronization, detecting a synchronization signal at the periodic estimated synchronization timing, correcting an error of the estimated synchronization timing from the detected synchronization timing, and generating a demodulation timing at the synchronization timing. Performing demodulation at the demodulation timing and calculating an error rate at the time of demodulation; determining whether the estimated synchronization timing is a normal timing according to the error rate; Is executed from the means for acquiring the initial synchronization in the case of Receiving method is characterized in that so as to repeat the procedure. 19. The synchronization signal included in the transmission signal,
19. The receiving method according to claim 18, wherein the signal is a signal modulated by an OFDM method. 20. The detection method according to claim 19, wherein the detection of the synchronization signal from the received OFDM signal is performed by detecting only one of a real component and an imaginary component of the received OFDM signal. Receiving method. 21. A synchronization signal included in the transmission signal,
The receiving method according to claim 18, wherein the signal is an M-sequence signal. 22. A step of detecting a synchronization signal from a received signal to obtain an initial synchronization, a step of generating a periodic estimated synchronization timing based on the obtained initial synchronization, and a step of generating a synchronization signal based on the periodic estimated synchronization timing. Detecting; correcting the error of the estimated synchronization timing from the detected synchronization timing; generating demodulation timing at the synchronization timing; performing demodulation at the demodulation timing and calculating an error rate during demodulation Determining whether or not the estimated synchronization timing is the normal timing according to the error rate; and executing the initial synchronization when the determination is an estimated synchronization timing error, In other cases, the procedure after the generation processing of the periodic estimated synchronization timing is repeated. Medium to be executed by the processing means a program which comprises the steps.