JPH03143124A - Reference signal generator - Google Patents

Abstract

PURPOSE:To easily generate a reference signal corresponding to a change in a radio wave propagation delay time and hand-over required for the transmission/reception control of a TDMA system automobile telephone mobile equipment by providing two counters having a same period and utilizing the relation of lag/lead of a coincidence signal outputted from each counter. CONSTITUTION:The generator consists of a counter 103 counting a clock signal 101 inputted externally and outputting the result of count of 0-(n-1) repetitively, a register 104 writing a data of 0-(n-1) with an external write signal 105, a coincidence detection section 106 outputting a coincidence signal 107 when an output of the counter 103 is coincident with the content of the register 104, a counter 108 counting the clock signal 101, outputting repetitively the count result of 0-(n-1), outputting a coincidence signal 110 when the result of count reaches (n-1) and clearing the count content when a reset signal 111 is set, and a control section 112 receiving the write signal 105, the coincidence signals 107 and 110 and outputting the reset signal 111, and generates a reference signal from the counter 108.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention is directed to time-based multichannel access.
ltichannel, Access; Hereinafter,
This invention relates to a reference signal generating device used in a mobile phone using a TDMA (TDMA) system.

A conventional car telephone system generally consists of a base station 21a (21b) and a mobile station 22, as shown in FIG.
For mobile station communication (radio waves for mobile station transmission (radio waves for base station reception) 23, radio waves for mobile station reception (radio waves for base station transmission) 2
Use 2 waves of 4. As an example of applying TDMA to a car phone, an example of applying TDMA to a car phone is as follows.
7 “Rosite Inc.”
Cellular Reteio Con Ellen 7, (October 1988), (Proceedings of
Digital Cellular Radio.

Conference (0ctober 1988
)) There is one shown on page 3a/3.

Figure 3 simply shows the time-division use of radio waves described in this publication.

As shown in the figure, the transmitting and receiving radio wave i is TDMA frame 3.
1 and is divided into units each having a length of 4,615 m5. Then, the TDMA frame (called slot 32, which is divided into 8 units with a length of 0.577 m5) is divided into 8 units, each having a length of 0.577 m5, and the communication between the base station and the mobile station (each mobile station uses the slot designated by the base station to use). This is achieved by performing a transmission (H reception operation).For example, if the image is received in slot 1,
The mobile station designated to transmit in slot 4 uses an I TDMA frame as a periodicity, as shown in Figure 4, and transmits data every slot 1.
A reception operation is performed in every slot 4, and a transmission operation is performed in every slot 4.

However, in order to realize such communication between the base station and the mobile station, it is necessary to synchronize the transmitting and receiving operations of both the base station and the mobile station. be.

The reference signal shown in FIG. 4 is the output of this reference signal generator. For example, if the resolution of the output of the reference signal generator is 5,000, as shown in Figure 4, when the reference signal is 625 to 1,249, the mobile station reception operation (base station transmission operation) is 2,500 to 3 degrees 124. By performing a mobile station transmission operation (base station reception operation) at , synchronous communication between the base station and the mobile station is realized.

The basics of the TDMA system are as described above, but in reality
It must be noted that there is a radio wave propagation delay between the base station and the mobile station. In other words, the distance between base station and mobile station is L
If slot 1 is assigned to receive (i) and slot 4 is assigned to transmit, then L is assigned as shown in Figure 5.
The actual mobile station reception operation must be performed as slow as LL, T=L/radio wave propagation speed, and the mobile station transmission operation must be performed as fast as T.

Moreover, since L is the distance between the base station and the mobile station, the delay time also changes moment by moment according to the movement ΔL of the mobile station at ΔT=ΔL/radio wave propagation speed. Therefore, the ever-changing delay time △T
It must be able to respond to

Also, consider dealing with a process called handover.
I need to keep it down. When the mobile station moves, the electric field strength of the base station A21a with which it is currently communicating has weakened, as shown in Figure 2. Refers to the switching action. However, the slot positions of base station A21a and base station 821b do not match as shown in Figure 6. Even if the same slots are used before and after handover, the actual transmitting and receiving positions must be changed as shown in Figure 6. As mentioned above, a reference signal generator used in a TDMA car phone mobile device must be capable of handling this handover process. It is necessary to be able to handle handovers, and conventional simple counters (for example, Texas Instruments 5
N74161) alone cannot handle this.

Problems to be Solved by the Invention As mentioned above, the reference signal generator used in a TDMA mobile phone has a problem that cannot be solved using only a conventional simple counter.

In view of the above, an object of the present invention is to provide a reference signal generation device suitable for a TDMA mobile phone mobile device.

Means for Solving the Problems According to the present invention ζ A first counter that repeatedly outputs the count results of L 0-n-1 counts clock signals input from the outside, and a write signal from the outside.
- a register into which n -1 data is written;
When the counter output matches the contents of the register, the first
a coincidence detection section that outputs a coincidence signal of L'0-n-1 by counting the clock signal inputted from the outside;
When it becomes 1, it outputs the second coincidence signal, and when the reset signal given from the control section, which will be described later, becomes active,
a second counter that sets the count to 0, a write signal to the register, the first coincidence signal, and the second counter;
The reference signal generating device is provided with a control section that receives a coincidence signal of the above as an input and outputs the second counter reset signal.

Operation The present invention has the above-described configuration, and the control unit force exchanges the first
The second counter output matches the contents of the register, the second counter output becomes nl, and data is written to the register.
By controlling the reset operation of the counter, the second
It is possible to generate a reference signal corresponding to radio wave propagation delay and handover.

Embodiment FIG. 1 shows a block diagram of an embodiment corresponding to the invention as claimed in claim 1.

In Fig. 1, 101, 102i1 are clock signals given from the outside, and their relationship is shown in Fig. 7.
This is an up counter that repeatedly counts within the range of 9, and the count result is output to the match detection section 106, which will be described later.

I 04 it register, O~4 from outside
, 999 is written by the write signal 105. i for I Q f3, is a coincidence detection part,
When the outputs of the counter 103 and the register 104 match, a match signal 107 is output. 108 (yo clock 101
It is an up counter that repeatedly counts in the range of 0 to 4,999, and the reference signal 109 is 0 to 4,999.
Output the count result. Furthermore, the count result is 4, 9.
It also outputs a match signal 110 that notifies when it matches 99. Further, the counter 108 is reset in synchronization with the clock signal 101 when the reset signal 111 is active. 112<& Write signal 105, match signal 107
, the control unit 112! is a control unit that outputs a reset signal 111 in synchronization with the clock signal 102 based on the coincidence signal 110. i It consists of the state machine shown in FIG.

In FIG. 8, 801 is a flip-flop that detects and outputs the falling edge of the write signal 105, 802 is a flip-flop 801 output, coincidence signal lO7, coincidence signal 110.
, and the next state signals 803, 804, 805 as clock 1
Sample write detection signal 806, coincidence signal 8 at 02
07, - match signal 808, and status signals 809, 810,
This is a register that outputs 811. Further, the flip-flop 801 and the register 802 are reset by an external reset signal 812 applied from the outside. 813ζ
It is a combinational circuit, and the output from the register 802 is the state signal 803, 804, 805, and reset signal 1.
FIG. 9 shows the input/output relationship of the combinational circuit 813.

Further, FIG. 10 shows a state transition diagram of a state machine consisting of a register 802 and a combinational circuit 813.

The operation of the reference signal generating device configured as above will be explained with reference to FIGS. 9 and 10, focusing on the transition relationship. 802 remains reset, so the state machine (
9th plate The state becomes 0 as shown in Figure 10. In state 0, the reset signal 111 is always output, so the counter 10
8 remains reset and the reference signal 1 which is 0
09 is output.

(1b) Release of external reset signal 812 When the external reset signal 812 is released, the reset of the flip-flop 801 and the register 802 is released, so that the state becomes state 1 in synchronization with the clock signal 102 according to FIG. However, since state 1 also always outputs the reset signal 111,
The counter 108 remains reset and the reference signal 109, which is O, is output. Further, state 1 is maintained as long as the write detection signal 806 does not become active.

(1c) In write state l to register 104, when an appropriate value N is written to register 104, flip-flop 801 is set, write detection signal 806 becomes active in synchronization with clock signal 102, and further according to FIG. State 2 is entered in synchronization with the clock signal 102. However, since state 2 also always outputs the reset signal 111, the counter 108 remains reset and the output
A reference signal 109 is output. Further, state 2 remains as long as the match signal 807 does not become active.

(1d) When the match signal 807 is in the active state 2, when the output of the counter 103 whose contents are constantly incremented by the clock signal 101 reaches N, the match signal 107 is output from the match detecting section 106. Therefore, the coincidence signal 80 is synchronized with the clock signal 102.
7 also becomes active and the state machine of FIG. 8 goes to state 3 according to FIG.

In state 3, the reset signal 111 is released, so the counter 108 resets its contents to 0 by the clock signal 101.
, 1, 2, and the count result is n.
When it becomes -1, a match signal 110 is output.

In state 3 (unless write detect signal 806 is active), match signal 110 is clocked 102 as shown in FIG.
Since the reset signal 111 is activated every time the coincidence signal 808 synchronized with
A value of -1 is repeatedly output as the reference signal 109.

(1e) When writing a new value M to the register 104 in state 3 of writing to the register 104, the flip-flop 801 is set and the next clock 102
The write detection signal 806 becomes active in synchronization with the clock signal 102, and transitions to state 4 in synchronization with the clock signal 102 according to FIG. 9 (1f). If 807 becomes active before the match signal 808, that is, the output of the counter 103 becomes M before the output of the counter 108 becomes n-1 (reset signal 111 is output and the state changes to state 3. In other words, the reference signal 109 becomes It is reset to O before reaching n-1.

(1g) The match signal 808 is in active state 4 before the match signal 807, and the match signal 808 becomes active before the match signal 807 (i.e., the output of the counter 108 becomes n-1 before the output of the counter 103 becomes M). (f) Outputs the reset signal 111 and transitions to state 2. In other words, after the reference signal 109 becomes n-1, the reference signal 109 outputs O until the output of the counter 103 becomes M. An example of the signal 109 is shown in FIG. 11. The states l, 2, and
3 and 4 correspond to the states described above.

When the value N is written to the register 104 in state 1, the state transitions to state 2.When the counter 103 output becomes N in state 2, the reset of the counter 108 is immediately released and the state 3 is entered. Since the reset signal 111 is output in accordance with the match signal 110 that is output when the value becomes -1, the counter 108 repeats counting 0- n -1. When the value M is written to the register 104 in state 3, the state transitions to state 4. do.

When the output of the counter 103 becomes M in state 4, the counter 108 is immediately reset and the state returns to state 3, where a waveform like 1101 in FIG. 11 is generated.

On the other hand, a value is written to the register 104 in state 3.
If the output of the counter lO8 becomes n, -1 before the output of the register 104 and the output of the counter 103 match, the counter 108 is reset and the state transits to state 2. and Ci in state 2.

The counter lO8 continues to be reset until the output of the counter 103 becomes L. When the output of the counter 103 becomes L, a transition is made to state 3. Therefore, a waveform like 1102 in FIG. 11 is generated.

The waveform of the reference signal 109 in FIG. 11 generated by the above operation corresponds to the change in delay time ΔT caused by the movement of the mobile station mentioned earlier.
When the mobile station approaches the base station, the period of the reference signal 109 is transiently shortened by ΔT as shown in 1101, and when the mobile station moves away from the base station, the period of the reference signal 109 is shortened transiently by ΔT as shown in 1102. It's just longer.

As described above, according to the embodiment of the present invention, in the steady state, by generating the reset signal 111 based on the coincidence signal 110 that is output when the content of the counter 108 becomes n-1, a reference having a period of H is generated. A signal 109 is generated. Furthermore, for changes in the distance between base station and mobile station (Yo counter 1
By writing the value at which the counter 108 is reset and started again into the register 104, the cycle of the counter 108 output can be temporarily lengthened or shortened and adjusted.

FIG. 12 is a diagram showing another input/output relationship of the combinational circuit 813. Input/output related combinational circuit 81 shown in FIG.
A state transition diagram of a state machine with 3 is shown in FIG.

Next, the operation of the reference signal generator when the input/output relationship of the combinational circuit 813 is changed to that shown in FIG. 12 is as follows.
The state transition relationship will be mainly explained using FIG. 12@FIG. 13.

(2a) External reset signal 812 active state In this state, the flip-flop 801 and register 802 remain reset, so the state machine of FIG. Since the reset signal 111 is always outputted at O, the counter 108 remains reset and the reference signal 109 which is 0 is outputted.

Although the above operation is the same as that described in section 1a above, (2b) External reset signal 812 release When the external reset signal 812 is released, the reset of the flip-flop 801 and register 802 is released. According to FIG. 12 (＼ State 1 is entered in synchronization with the clock signal 102. However, since state 1 also always outputs the reset signal 111, the counter 108 remains reset,
A reference signal 109 that is 0 is output. Further, state 1 is maintained as state 1 unless the write detection signal 806 becomes active.

The above operation (same as the operation described in section lb of the friend).

(2c) In write state l to register 104, when an appropriate value N is written to register 104, flip-flop 801 is set and clock signal 102
The write detection signal 806 becomes active in synchronization with
becomes.

However, since state 2 also always outputs the reset signal 111, the counter 108 remains reset, and even if the reference signal 109 which is O is output, state 2 will also remain in state 2 unless the match signal 807 becomes active. .

The above operation (although it is the same as the operation described in the previous section 1c (2d)) When the coincidence signal 807 is in the active state 2, the output of the counter 103 whose contents are constantly incremented by the clock signal 101 becomes N. Then, the coincidence signal 107 is output from the coincidence detection section 106, and the coincidence signal 80 is synchronized with the clock signal 102.
7 also becomes active, and the state machine of FIG. 8 goes to state 3 according to FIG. Then, when the count result reaches n-1, a match signal 110 is output.

In state 3, unless the write detect signal 806 is active,
The match signal 110 is clocked 102 as shown in FIG.
Since the reset signal 111 is activated every time the coincidence signal 808 synchronized with
A value of -1 is repeatedly output as the reference signal 109.

The above operation is the same as the operation described in the ld section above.

(2e) Writing to the register 104 In state 3, when a new value M is written to the register 104, the flip-flop 801 is set and the write detection signal 806 becomes active in synchronization with the next clock 102, and according to FIG. Transition to state 5 occurs in synchronization with clock signal 102.

(2f) If the coincidence signal 808 is in the active state 5 and the coincidence signal 808 becomes active, that is, the counter 108 output becomes n-1 (Shibu reset signal 1
After outputting 11, it transitions to state 2. In state 2, as described in section 2d above, the reset signal 111 continues to be output until the match signal 807 becomes active. In other words, after the counter 108 output reaches n-1 (friend counter 103
The counter 108 continues to be reset until the output of M becomes M.

FIG. 14 shows an example of the reference signal 109 output by the operation described above. Conditions 1, 2, and 3 shown in Figure 14
, 5 correspond to the conditions described above.

In FIG. 14, there is a transition from state 1 to state 2 and then to state 3 (as shown in FIG. 11).

In state 3 (1.X, the counter 108
The power exchange repeats the count from 0 to n-1. Here, when a new value M is written to the register 104, a transition is made to state 5.

In state 5, when the output of the counter 108 becomes n, -1, the counter 108 is reset and the state transits to state 2.

In state 2, the counter 108 continues to be reset until the output of the 4i counter 103 becomes M. Therefore, a waveform like 1401 in FIG. 14 is generated.

The waveform of the reference signal 109 in FIG. 14 generated by the above operation corresponds to the handover described earlier. Even if the same slot is used, the actual transmission and reception positions must be changed before and after the overload, and therefore the reference signal generation start position must be changed.

The waveform of the reference signal 109 shown in FIG. 14 is smoothly changed from N to M based on the output of the reference signal generation start position counter 103.
As described above, according to the embodiment of the present invention, in the steady state, the reset signal 111 is raised to the upper base based on the coincidence signal 110 output when the content of the counter 108 reaches n-1, so that the reset signal 111 has a cycle of n. A reference signal 109 is generated. Furthermore, in response to handover (to reset and start the friend counter 108, by writing the value to the register 104 again, the output becomes O during the handover period,
Before and after that, a reference signal with a period of n is sent to the counter 108.
It can be generated from

FIG. 15 shows a block diagram of an embodiment corresponding to the invention as claimed in claim 2.

FIG. 15 (In the block diagram of the embodiment shown in FIG. 1, the power allowance for the mode register 1501 is changed from the control unit 112 to the control unit 1502 due to this addition, and the other configuration is It is exactly the same as that shown in Fig. 1.The control unit 15021t is composed of the state machine shown in Fig. 16. FIG. 17 shows the input/output relationship of the combinational circuit 1601 corresponding to this.

The operation of the reference signal generating device configured as above will be explained next.

3a) When the mode signal 1601 is ○ In this case, the input/output relationship of the combinational circuit 1602 shown in FIG.
This is exactly the same as the human output relationship of the combinational circuit 813 shown in FIG. Therefore, the operation in this mode is exactly the same as that described in terms la to 1g, and the reference signal 109 corrected for the change in propagation delay time shown in FIG. 11 can be output.

3b) When the mode signal 1601 is 1 In this case, the input/output relationship of the combinational circuit 1602 shown in FIG.
The human output relationship is exactly the same as that of the combinational circuit 813 shown in FIG. Therefore, the operation in this mode is exactly the same as that described in sections 2a to 2e above, and the reference signal 109 corresponding to the handover shown in FIG. 14 can be output.

As described in Section 2, according to the embodiment of the present invention, by simply changing the contents of the mode register 1501, the cycle of the counter 108 can be changed in response to a change in the distance between the base station and the mobile station, and the output control of the counter 108 can be controlled in response to a handover. It is possible to handle both.

As described in detail, according to the present invention, by providing two counters having the same period and utilizing the context of the matching signals output from each counter, transmission/reception control of a TDMA car phone mobile device can be performed. Necessary equipment It is possible to easily generate a reference signal that corresponds to changes in radio wave propagation delay time and handover, and its practical value is significant (1

[Brief explanation of the drawing]

Fig. 1 shows a block diagram of a reference signal generating device in an embodiment of the invention as claimed in claim 1. Fig. 2 shows a car telephone system. Fig. 3 shows a radio wave time division using TDMA method. Figure 5 shows the timing of transmitting and receiving operations depending on the system. Figure 6 shows the timing of transmitting and receiving operations during handover. Figure 7 shows the clock signal used in the present invention. Figure 8 shows the detailed structure of the control section shown in Figure 1. Figure 9 @ Figure 12 shows the human output relationship of the combinational circuit shown in Figure 8. Figure 1 shows the state transition of the control unit shown in Figure 1.
The figure shows an example of a signal generated by the reference time development generator of the present invention.
FIG. 17 is a diagram showing the detailed structure of the control section shown in FIG. 5. FIG. 17 is a diagram showing the input/output relationship of the combinational circuit shown in FIG. 101, 102... Clock signal 103, 108...
...Karan Hisashi 104-...Regis Hisashi 105...Write signal, 106...Concordance detection K 107, 11
0... Match signal, 109... Reference signal ull...
・Reset signal 112, 1502...Control ability 81
3, 1601...Combination output 1501...Mode register 1503...Mode signal.

Claims (2)

[Claims] (1) Count clock signals input from the outside,
The first counter repeatedly outputs the count results of 0 to n-1, and the external write signal causes the count results of 0 to n-1 to be output.
a register into which data is written; a coincidence detection section which outputs a first coincidence signal when the first counter output matches the contents of the register; -1 count result is repeatedly output, and when the count result becomes n-1, a second coincidence signal is output, and when the reset signal given from the control section (described later) becomes active, the count result is a second counter whose contents are set to 0; and a control unit that receives a write signal to the register, the first match signal, and the second match signal and outputs a reset signal to the second counter. A reference signal generating device comprising: (2) Count clock signals input from the outside,
The first counter repeatedly outputs the count results of 0 to n-1, and the external write signal causes the count results of 0 to n-1 to be output.
a register into which data is written; a coincidence detection section which outputs a first coincidence signal when the first counter output matches the contents of the register; -1 count result is repeatedly output, and when the count result becomes n-1, a second coincidence signal is output, and when the reset signal given from the control section (described later) becomes active, the count result is A second counter whose contents are set to 0, a write signal to the register, the first match signal, the second match signal, and a mode register output to be described later are input, and a reset signal is sent to the second counter. 1. A reference signal generating device, comprising: a control section that outputs a signal; and a mode register that specifies an operation mode of the control section.