JPH0352068B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a test method for CRT display control circuits that tests the CRT display control circuits on the computer main body side without using a CRT display unit. It is related to.

[Conventional technology and problems]

In computer testing, there are many areas where functional checks and abnormality detection for CRT display control circuit tests can only be confirmed by visually checking the CRT screen. Furthermore, it is impossible to visually monitor the CRT screen all the time.

[Purpose of the invention]

The present invention is based on the above considerations, and includes:
The purpose of this paper is to provide a test method for CRT display control circuits that allows computers to self-diagnose the functions of CRT display control circuits.

[Means to achieve the purpose]

Therefore, the test method for a CRT display control circuit according to the present invention includes a CRT display control circuit, a parity bit generation circuit that generates parity bits for a plurality of signals output from the CRT display control circuit, and a parity bit generation circuit as described above.
A synchronous clock generation circuit generates a clock synchronized with the clock of the CRT display control circuit, and a CRC operation is performed on the parity bit string output from the above parity bit generation circuit according to the synchronous clock.
A CRC calculation circuit, a counter that counts the synchronous clocks from the synchronous clock generation circuit and detects that synchronous clocks equal to the number of dots for one raster have been output, and a CRC calculation circuit that calculates the CRC based on the horizontal synchronization signal and the detection output of the counter. The computer is characterized by comprising an operation start/stop circuit for starting/stopping the arithmetic circuit, and an operation result control circuit for sending the operation result of the CRC operation circuit to the computer main body.

[Embodiments of the invention]

Hereinafter, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. In Fig. 1, 1 is the computer main body, 2 is the CRT display control circuit, 3 is the keyboard control circuit, 4 is the buffer, 5 is the synchronous clock generation circuit, and 6 is the parity circuit.
A bit generation circuit, 7 a CRC arithmetic circuit, 8 a counter, 9 an arithmetic result control circuit, and 10 an arithmetic start/stop circuit, respectively.

The CRT display control circuit 2 outputs a red video signal, a blue video signal, a green video signal, a horizontal synchronization signal, and a vertical synchronization signal. These signals are all synchronized with the basic oscillation clock of the CRT display control circuit 2 inside the computer. Keyboard control circuit 3
outputs the KB control signal to control the keyboard and receives data from the keyboard. The buffer 4 is composed of a gate and is used for signal level conversion and the like. The synchronous clock generating circuit 5 generates a clock synchronized with the clock of the CRT display control circuit 2, and synchronizes the synchronous clock with the first rise of the video signal for each raster. The parity bit generation circuit 6 generates parity bits of the red video signal, blue video signal, green video signal, horizontal synchronization signal, vertical synchronization signal, etc. output from the CRT display control circuit 2. The CRC calculation circuit 7 processes the parity bit string output from the parity bit generation circuit 6.
It creates a CRC. The counter 8 counts the clocks from the synchronous clock generation circuit 5,
When the value is equal to the number of dots for one raster,
Outputs a stop signal. Operation result control circuit 9
When the KB control signal indicates a transmission request, it sends the held CRC calculation result to the computer main body via the KB data line. The calculation start/stop circuit 10 puts the CRC calculation circuit 7 into operation when the horizontal synchronization signal is sent, and activates the CRC calculation circuit 7 when the stop signal is sent from the counter 8.
The CRC arithmetic circuit 7 is rendered inactive, and when a vertical synchronization signal is sent, the arithmetic result of the CRC arithmetic circuit is transferred to the arithmetic result control circuit 9, and the CRC arithmetic circuit 7 is returned to its initial state.

FIG. 2 is a diagram illustrating the operation of the embodiment of FIG. 1. When there is a horizontal synchronization signal, the CRC calculation circuit 7
is brought into operation, and the counter 8 is initialized. The synchronization clock generating circuit 5 performs synchronization processing so that the rise of the video signal coincides with the rise of the synchronization pulse at the first rise of the video signal after generation of the horizontal synchronization signal pulse. This synchronized clock is input to the CRC calculation circuit 9, and the CRC
The arithmetic circuit 9 executes a CRC operation on the pulse train output from the parity bit generating circuit 6 in synchronization with the synchronous clock. Note that the width of the previous synchronous clock and the next synchronous clock correspond to the width of one dot on the screen. When the value of the counter 8 for counting the synchronous clock becomes equal to the number of dots in one raster, the CRC calculation of the CRC calculation circuit 7 is stopped. but,
At this time, the CRC calculation value is not cleared. When the next horizontal synchronization signal pulse is detected, synchronous operation occurs. When a vertical synchronization signal is sent,
The CRC calculation result is transferred to the calculation result control circuit 9,
The CRC calculation circuit 7 is returned to its initial state. As described above, the CRC calculation results held by the calculation result control circuit 9 are sent to the computer main body when a request is received from the computer main body. Calculator 1 was sent
Compare the CRC calculation result with the expected value using a program.

FIG. 3 is a diagram for explaining a synchronous clock generation circuit, in which FIG. 3a shows an example of the synchronous clock generation circuit, and FIG. 3b shows a four-phase clock. In the figure, 11 is a four-phase clock oscillation circuit, 12 is a flip-flop, 13 is a decoder, and 14 is a synchronous clock select circuit. The phase changes by 90° at the same frequency as the basic oscillation clock in the CRT display control circuit 2 4
The 4-phase oscillation clock (φ1 to φ4) is oscillated in the 4-phase clock oscillation circuit 11, and this clock is converted to the 4-phase clock using the 4 flip-flops 12 at the first rise of the video signal after the horizontal synchronizing signal pulse is generated. By latching the high/low state of CRT display control circuit 2 during 4-phase clock
The basic oscillation clock in the CRT display control circuit 2 is decoded by the decoder 13 from the outputs of the four flip-flops 12, and is added to the synchronous clock select circuit 14. This method generates a synchronous clock with the smallest phase difference.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, it is possible to reliably test a CRT display control circuit without using a CRT display unit.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
The figure is a diagram for explaining its operation, and FIG. 3 is a diagram for explaining the synchronous clock generation circuit. 1... Computer main body, 2... CRT display control circuit,
3...keyboard control circuit, 4...buffer, 5
... Synchronous clock generation circuit, 6 ... Parity bit generation circuit, 7 ... CRC calculation circuit, 8 ... Counter, 9 ... calculation result control circuit, 10 ... calculation start/stop circuit, 11 ... 4-phase Clock oscillation circuit, 12...Flip-flop, 13...
...decoder, 14...synchronous clock select circuit.

Claims (1)

[Claims] 1 A CRT display control circuit, a parity bit generation circuit that generates parity bits for a plurality of signals output from the CRT display control circuit, and a synchronous clock generation circuit that generates a clock synchronized with the clock of the CRT display control circuit. and the parity bit string output from the above parity bit generation circuit.
A CRC calculation circuit that performs CRC calculation according to a synchronous clock, a counter that counts the synchronous clocks from the synchronous clock generation circuit and detects when a synchronous clock equal to the number of dots for one raster is output, and a horizontal synchronous signal. and an arithmetic start/stop circuit that starts/stops the CRC arithmetic circuit based on the detection output of the counter;
A CRT characterized by comprising a calculation result control circuit that sends the calculation results of the calculation circuit to the computer main body side.
Test method for display control circuits.