JPS5977745A - Transmission control system - Google Patents

Abstract

PURPOSE:To reduce the reduction in unnoticed rate by means of a frame check sequence, by making a bit pattern frame representing the start of the frame effective only when a specific pattern continues for a prescribed number or over. CONSTITUTION:A frame and a time fill pattern are applied from a terminal A to a shift register SR1. DFF3-5 invert an output Q in synchronizing with a clock from a terminal C, each output of exclusive OR circuis 6, 7, and an AND circuit 8 goes to ''1'', the counter 10 keeps advancing and a JKFF11 is set. Further, the frame is transmitted from an SR1 to a comparator 2, and compared 2 with an FS pattern from a terminal B. When the result of comparison is coincident, ''1'' is given to an AND circuit 12 to inform the detection of FS. Thus, ''1'' is transmitted from the FF11 so as to inform that the FS is effective.

Description

[Detailed description of the invention] (a) Technical field of the invention The present invention transmits data using a frame structure.

The present invention also relates to a transmission method for serially transmitting the focus forming the frame, and particularly to a transmission control method for recognizing a bit pattern indicating the beginning of a frame.

(b) Prior art and problems Conventionally, when data is transmitted using a frame structure, the frame generally consists of an integral multiple of a byte consisting of 8 bits, and a byte indicating the beginning of the frame (hereinafter abbreviated as FS)
and a byte indicating the end of the frame (hereinafter abbreviated as FB) contain bytes and data such as control, address, and error check functions, and the data is usually formed of a large number of bytes. Furthermore, in order to efficiently transmit data, the code conversion KNRZ method is used, but depending on the content of the data, "0" or "1" may be consecutive, which poses a problem. In particular, recently, data transmission using light has become more common, so when "0" continues, the automatic gain control circuit that constitutes the receiving circuit may not operate properly and "1" may not be recognized. To prevent this, distinguish between the FS and FE frame separation patterns and other patterns, and keep the number of consecutive "O" or "l" characters below a certain number, no matter what pattern the data takes. is being carried out. For this purpose, the frame is converted from a logical level frame to a physical level frame as shown in FIG. In other words, the logical level of FS shown in 15 is changed to the physical level shown in 16, and the logical level of patterns and data other than FS and FE shown in 17 is changed to 1.
The logical level of the FE shown at 19 is converted to the physical level shown at 8, and the logical level of the FE shown at 19 is converted to the physical level shown at 20, respectively. This adds 1 bit to each byte consisting of 8 bits to make 9 bits, and for FS and FE, the added bit is the same as the 7th bit.
1”, and the other bytes are represented as data, and each bit is a + b + Cr
If d + e * f + g + h, then if the seventh bit g is, for example, 11111, "θ", which is its inverted bit i, is added. A repeating pattern different from FS and FE is played between frames. For example, “01” repeating pattern “01”
0101''. These repeated patterns are called time fill patterns. If the time fill pattern changes to an FS pattern due to noise, frame abnormalities are detected by a frame check sequence at the physical level.

However, when the FS pattern is destroyed by noise.

When the data part is searched and an FS pattern is detected, it is treated as a frame, and abnormalities are checked using a frame check sequence. However, if the frame is long, there is a drawback that the miss rate due to the frame check sequence increases.

(C) Object of the Invention In order to eliminate the above-mentioned drawbacks, it is an object of the present invention to provide a transmission control method that makes recognition of an FS pattern effective only after repeating a time fill pattern a certain number of times or more.

(d) Structure of the Invention The structure of the present invention transmits data using a frame structure,
In addition, in a transmission system that serially transmits the bits forming the frame, a specific pattern is repeated between the frames.

The bit pattern indicating the beginning of a frame is made valid only when the specific pattern continues for a certain number of times or more.

<e> Embodiment of the invention FIG. 2 is a block diagram of a circuit showing an embodiment of the invention. A frame and a time fill pattern are input to the terminal and input to the shift register 1.

In this embodiment, the shift register is composed of 11 pins. When a time fill pattern is flowing on the line, the last focus of shift register l is a repetition of 0101''. Therefore, D flip-flops 3, 4 and 5 are connected to terminal C.
In order to invert the output terminal Q in synchronization with the input clock, the outputs of the exclusive OR circuits 6 and 7 become 1'', and the output of the AND circuit 8 becomes 1''. Therefore, the counter 10 continues to increment and sets the JK flip-flop 11. In this embodiment, the counter 10 is in base 32. Frame enters from terminal A, comparator 2 from shift register 1
The signal is sent to the comparator 2 and compared with the FS pattern provided from the terminal B. If they match, "1" is sent to the AND circuit 12 to notify that the FS has been detected. Since JK flip-flop 11 is set, AND circuit 12
sends "1" from the terminal to notify that the FS is valid.

Since the FS pattern has been destroyed by noise, when the data part is searched and the FS pattern is detected in comparator 2, the data part has the inverted pitch t-g of the 7th bit g as described above. Because this is a bit, "0101" will not be repeated, but "11" or "00" will always continue, and for this reason, D flip-flops 3, 4, and 5 have timings that do not invert their output terminals Q. Yes, exclusive O
There is a timing when the output of the R circuit 6 or 7 does not become "1". Therefore, the counter 10 is reset by the output of the NOT circuit 9. Since the JK flip-flop 11 is also reset, the AND circuit 12 sends "0" to the terminal to notify that the FS is invalid.

(f) Detailed Description of the Invention As described above, the present invention can reduce the miss rate due to the frame check sequence when the FS pattern is destroyed by noise, and has a significant effect.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating a method of converting a frame from a logical level frame to a physical level frame. FIG. 2 is a block diagram of a circuit showing one embodiment of the present invention. 2 is a shift register, 2 is a comparator, 3 and 4.5 are D flip-flops, 10 is a counter, and 11 is a JK flip-flop.

Claims (1)

[Claims] In a transmission method in which data is transmitted using a frame structure, and there is a repetition of a specific pattern between the frames, and the data is transmitted in series with the bits forming the frame, the repetition of the specific pattern is detected. 1. A transmission control system, comprising means for making a bit pattern indicating the beginning of a frame valid only when the specific pattern continues for a certain number of times or more.