JP3063433B2 - Microprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a microprocessor having a data output circuit for transmitting serially output data.

[0002]

2. Description of the Related Art In recent years, there has been remarkable progress in LSI-related technology, and higher speed and higher performance of microprocessors, especially digital signal processors (hereinafter referred to as DSPs), have led to advances in voice compression technology. In the early days of the audio compression technology, as represented by waveform encoding, a method of outputting one code for one sampled audio data was mainly used.

[0003] When performing such a decoding process, 1
A decoding process for one code data must be performed during the sampling period. That is, the decoding of the input code data is completed within a period of one sampling cycle, and the output of the decoded audio data is waited until the output of the decoded audio data in the previous sampling cycle is completed. Need function. In general, the sampling frequency is very slow as compared to the machine cycle of the microprocessor, so that the decoded audio data is output as serial data. The serial data output circuit of the conventional DSP has a configuration as shown in FIG. 3, and it is very convenient to perform such processing.

As shown in FIG. 3, a conventional serial data output circuit of a microprocessor includes a register 22 for holding audio data received via a data bus 21;
The parallel data received from the register 22 is converted into serial data 24, and the externally connected D /
Serial output control signal 23 such as shift clock and strobe supplied from the interface circuit with the A converter
Outputs serial data 24 in accordance with, the shift circuit has a shift circuit 26 which outputs an ack signal 25 indicating that empty.

As described above, when decoding coded audio data, a program for executing a decoding algorithm starts in synchronization with the ack signal 25 in order to adjust the output timing of the audio data. The processing is completed within the sampling period, and the audio data is output after the input of the next ack signal. In order to realize such processing, the serial data output circuit of FIG. 3 has a suitable configuration.

[0006] However, an audio coding system with a very high compression rate that has recently attracted attention compresses audio information to a bit rate lower than the sampling frequency. For this reason, the coding unit is a data group called a frame (usually 2).
One frame is composed of 160 samples at 0 msec)
And decodes the coded data for one frame collectively. In practice, it is necessary to simultaneously execute a process of decoding one frame of encoded audio data and a process of outputting the stored one frame of audio data in accordance with a sampling period.

[0007]

However, when a conventional data output circuit implements a high-efficiency speech coding algorithm, the decoding process is interrupted at each data sampling timing to stop the previous frame decoding process. However, there is a problem that the output processing of the audio data decoded in step (1) must be performed.

An object of the present invention is to provide a microprocessor having a data output circuit which solves the above-mentioned problem and eliminates interruption of decoding processing by data output processing.

[0009]

According to the present invention, there is provided a microprocessor comprising:
The server decodes the compressed data and outputs it serially to the outside
In a microprocessor having the function of performing
Input one frame of decoded data via bus
And a memory for writing and holding the
Holds a value indicating the read address of the memory and reads the memory.
Each time the read is executed, 1 is added to the value indicating the read address.
A memory pointer to be added;
Input the parallel data every time the data is read out
Convert to data, output to outside and serial conversion
Outputs an empty signal indicating that the operation has been completed and has become empty
A shift circuit, and the memory point receiving the empty signal.
If the value stored in the data is compared with the specified value and they do not match
Is stored at the address indicated by the value of the memory pointer.
Reading of the data is permitted.
Reset memory pointer and decode for next frame
Outputs an interrupt signal instructing execution of the processing program
And a data output circuit including a control circuit that performs the control .

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a data output circuit of a microprocessor according to a first embodiment of the present invention.

In FIG. 1, this embodiment is a memory for storing voice data received by a memory 12 via a data bus 21.
Is a pointer pointing to the output address of the memory 12, and the value is incremented (+
1) Yes.

The control circuit 18 reads the data 51 of the memory pointer 17 every time the ack signal 25 is input, and outputs an interrupt signal 19 when the value of the memory pointer 17 reaches the number of data of one frame (160). And 1
The completion of the data output for the frame is notified, and the memory pointer 17 is cleared. In FIG. 1, FIG.
Components having the same number as have the same function.

When a speech code is decoded using the output circuit of this embodiment, a program for executing a decoding algorithm starts running in synchronization with the interrupt signal 19. First, after one frame of audio data (for example, 160 samples) decoded in the previous frame is transferred to the memory 12 at a time, until the next interrupt signal 19 is input,
Only the decoding process of the code for the next one frame needs to be performed. In the meantime, the data output circuit in FIG. 1 executes a process of outputting one frame of audio data stored in the memory 12 in synchronization with the sampling frequency.

FIG. 2 is a block diagram showing a data output circuit of a microprocessor according to a second embodiment of the present invention. In FIG. 2, in this embodiment, a register 311 is a register for storing the number of data for one frame, and can set and read a value via a data bus 21.

The control circuit 308 reads out the data 61 of the memory pointer 17 and the data 71 of the register 311 every time the ack signal 25 is input, and outputs an interrupt signal 19 when the values match each other. That the output of the audio data of the
Clear In FIG. 2, components having the same numbers as those in FIGS. 1 and 3 have the same functions.

In the second embodiment, when decoding an audio code using an output circuit, first, the number of data for one frame is set in the register 311. The program that executes the decoding algorithm starts operating in synchronization with the interrupt signal 19 and decodes one frame of data until the next interrupt signal 19 is input. In the meantime, the data output circuit of FIG. 2 executes a process of outputting one frame of audio data stored in the memory 12 in synchronization with the sampling frequency. In the present embodiment, by setting the number of data for one frame in the register 311 via the data bus 21, the number of data constituting the frame becomes variable, so that a wider range of applications can be supported.

[0017]

As described above, the present invention has an effect of completely eliminating interruption of decoding processing due to data output processing by making data output processing into a dedicated block.

The data output circuit shown in FIGS. 1 and 2 can be used not only for a microprocessor but also for a wide range of digital electronic circuits.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a data output circuit of a microprocessor according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a data output circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional data output circuit.

[Explanation of symbols]

 Reference Signs List 21 data bus 22, 311 register 23 serial data control signal 24 serial data 25 ack signal 26 shift circuit 12 memory 17 memory pointer 18, 308 control circuit 19 interrupt signal 51, 61, 62 data 50, 60 control signal

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H04B 14/00-14/06 H03M 9/00 G06F 13/38 310 G06F 13/38 350

Claims (2)

(57) [Claims] 1. A method of decoding compressed data and serially outputting the decoded data to an external device
A microprocessor having a function of outputting one frame of decoded data through a data bus
A memory for writing and holding over a plurality of addresses, and a memory for holding a value indicating a read address of the memory.
The read address is indicated every time the memory is read.
A memory pointer for adding 1 to the value, and a parallel pointer each time parallel data is read from the memory.
Input data, convert it to serial data, and output to external
And the serial conversion is completed and it becomes empty
A shift circuit that outputs a vacant signal indicating the value, and a value held by the memory pointer in response to the vacant signal.
And a predetermined value.
Reading data stored at the address indicated by the pointer value
Is permitted, and if they match, the memory pointer
Reset and decryption processing program for next frame
And a control circuit for outputting an interrupt signal for instructing execution of the microprocessor. 2. The method according to claim 1, wherein the predetermined value is the number of data for one frame.
In the register provided connected to the data bus with a value indicating
2. The microprocessor according to claim 1, wherein the microprocessor stores the information.