JP2518387B2 - Serial data transmission circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device, and more particularly to an audio data transmission circuit for serially transmitting data.

[Conventional technology]

Conventionally, this type of serial data transmission circuit has a configuration having a data shift circuit for each of the input and the output. A schematic block diagram is shown in FIG.

The conventional example of FIG. 6 is a serial data input circuit 602, a serial data output circuit 603, a serial data input terminal 604, a serial data output terminal 605, a serial data transmission clock input terminal 606, a serial data transmission clock output terminal 607, a processing block 608. Further, it has a timing control circuit 609, the serial data input terminal 604 is connected to the input of the serial data input circuit 602, and the output of the serial data input circuit is connected to the internal data bus 610. The input data is processed by the processing block connected to the internal data bus 610 and output again to the internal data bus 610.
Input to the serial data output circuit connected to 10.
The output of the serial data output circuit is connected to the serial data output terminal 605. On the other hand, the serial data transmission clock composed of the transmission clock and the word period signal is
A serial data transmission timing of the serial data input circuit 602 and the serial data output circuit 603 is controlled by a timing control circuit 609 which is input from the serial data transmission clock input terminal 606 and connected to the serial data transmission clock input terminal 606.

For example, the transmission of voice data is usually shown in FIG.
Serial data transmission is performed in the format shown. At this time, the transmission clock is a bit clock,
The signal indicating the transfer cycle for words is the LR clock. This LR clock matches the sampling cycle of audio data, and the audio data sampled at each sampling cycle is transferred word by word in synchronization with this LR clock, and finally an analog signal synchronized with this LR clock. Is converted to. Audio data is input from the serial data input terminal.

In the midway audio signal processing device, the audio data transmitted serially is converted into parallel data, extracted, multiplied,
An operation is performed in which filtering processing such as addition is performed, conversion to serial again and transmission in synchronization with the LR clock are performed.

As the transmission clock, the frequency of 48 times the word period signal corresponding to 201, 202 in FIG. 2 is used, the frequency of 32 times corresponding to 203 is used, or when there is no special designation as shown in FIG. There is. Also, the data length to be transmitted is 18 bits 201,501 and 16 bits 202,2.
There are 03,502 etc. These transmission clock rate and transmission data length depend on the audio data output device connected to the serial data input terminal. Therefore, in order to support various data transmission formats, it is necessary to support various audio data output devices.

[Problems to be Solved by the Invention]

The above-described conventional serial data transmission circuit has a data shift circuit on each of the input side and the output side, which increases the circuit scale and further increases the number of clocks and the number of data bits for serial data transmission. If it is designed to be compatible with the above, it is necessary to configure each circuit with the data shift circuit on the input side and the data shift circuit on the output side, which has the drawback of increasing the circuit scale. .

Further, when the input serial data is output as it is in order to eliminate the interruption of data when changing the operation mode of the signal processing device, that is, when the digital signal processing device outputs the data without any processing. In addition, it is necessary to execute the data transfer processing from the data shift circuit on the input side to the data shift circuit on the output side, which occupies the internal data bus, and the processing block performs other processing independently of the data transfer. There is a drawback that the processing speed when executing is reduced.

Further, since the input circuit and the output circuit are independent, there is a drawback that jitter occurs in the transmission clock on the input circuit side and the transmission clock on the output circuit side.

[Means for solving the problem]

The serial data transmission circuit of the present invention includes a serial data input terminal, a serial data output terminal, a transmission clock input terminal, a word period signal input terminal, a parallel input terminal, a parallel output terminal, a data shift means, and a bit. It has a position conversion means, a first data holding means, a second data holding means, and a selection means.

That is, in the present invention, the data shift circuit for inputting and outputting serial data is provided as one system, and the data input from the serial input terminal is read out from the parallel output terminal in synchronization with the transfer cycle of the serial data of one word to input data. , And the output of the data holding means that holds the output data at the same time is fetched from the parallel input terminal and output in synchronization with the serial data transfer clock. In the present invention,
Since the input / output data shift circuit has only one system, if the input serial data is output as it is and no processing is performed on the data in the digital signal processing device, the data is not passed through the internal bus. Transferring.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram of an embodiment of the present invention.

In this embodiment, the shift register 101, barrel shifter 102, data latches 103, 104, selection circuit 105, serial data input terminal 106, serial data output terminal 107, internal data bus 121,
Data line 122,123,124,125,126,127,128,129,130,131,13
2, 133, a data shift signal 141, a data latch signal 142, a shift amount control signal 143, and a selection signal 144.

The shift register 101 is a 26-bit wide shift register having a serial input / parallel input / parallel output function, a serial data input is connected to a data line 122, a data shift timing is given by a data shift signal 141, and a data latch signal. Parallel data is captured in synchronization with 142. Further, in the shift register 101, if each bit is set to bit0, bit1, ..., Bit25 from the lower order, the parallel data input of bit0 to bit17 is connected to the data line 125, and bit18 to bit25
The parallel data inputs of are connected to data line 129. And b
The parallel data output of it0 to bit17 is connected to the data line 126, the output of bit23 is connected to the data line 132, and the output of bit25 is connected to the data line 133.

The barrel shifter 102 is an 18-bit width shifter, and depending on the value indicated by the shift amount control signal 143, outputs the 18-bit width data as it is, or shifts it by 2 bits in the upper direction, but the lower 2 bits are " Input 0 "and output. The data line 126 is connected to the input and the data line 127 is connected to the output.

The data latch 103 is an 18-bit wide data latch, and synchronizes with the data latch signal 142 which is a signal indicating the transfer end timing of the data of one word, and the data line 127.
Latch the input data. Data latch 103
Output is connected to data line 128. The data latch 104 is
18-bit wide data latch with data line 124 input
, And the output is connected to the data line 125.

The selection circuit 105 is a circuit that selects and outputs one of the four inputs according to the value indicated by the selection signal 144. The input is connected to the data lines 130, 131, 132, and 133, and the output is connected to the data line 123.

The serial data input terminal 106 is connected to the data line 122.

The serial data output terminal 107 is connected to the data line 123.

The internal data bus 121 is an 18-bit wide data bus.

The data lines 124, 125, 126, 127, 128 are 18-bit wide data lines.

Data line 129 is connected to the most significant bit of data line 125.

Data line 126 from bit 0, bit 1 to least significant bit
If bit17 is set, bit15 is connected to the data line 130 and bit17
Is connected to the data line 131.

 The operation of this embodiment will be described below.

The present embodiment is a data input / output circuit of an audio signal processing device for inputting / outputting audio data.

As a serial transmission format for audio data,
The format shown in FIG. 2 is used. Audio data is transferred in units of 16-bit or 18-bit words in synchronization with the LR clock indicating the attribute of the data word. Also, each bit is transferred in synchronism with a bit clock having a frequency of 32 times (16 bits only) or 48 times (16 bits or 18 bits) of the LR clock.

In the bit clocks shown in FIG. 2, those corresponding to 201 and 202 correspond to the LR clock and have a frequency of 48 times, and those corresponding to 203 have a frequency of 32 times. The bit clock is used as a data shift means. The LR clock is used as a data latch signal. Audio data is MSB
It is transmitted bit by bit in synchronism with the bit clock at the first, and is sent to the right with respect to the inverted edge of the LR clock. Audio data is input from the serial data input terminal. 16-bit or 18-bit audio data is input from the serial data input terminal 106 for each sampling period. The data latch signal 142 becomes active in synchronization with the edge of the LR clock indicating the word timing of data, and the bit clock is input to the data shift signal 141.

First, the operation when the bit clock is 32 times the LR clock will be described. At this time, the audio data length is 16 bits.

It is assumed that the 16-bit audio data is input to the internal data bus first.

The audio data input from the serial data input terminal 106 is taken into the shift register 101 in synchronization with the data shift signal 141, and when the 16-bit data transfer is completed, the data is held in bit15 to bit0 of the shift register 101. . Here, if the shift amount control signal 143 is used to designate the 2-bit shift to the higher order to the barrel shifter 102, the data latch signal 142 input in synchronization with the inversion of the LR clock causes the data latch 103 to output the upper 18 bits. Audio data is latched in 16 bits each. At the same time, the audio data held in the data latch 104 is input to the shift register 101. Data line 13 by selection circuit 105
When 1 is selected, the output audio data held in the shift register 101 is output from the serial data output terminal 107 in synchronization with the data shift signal 141, that is, the bit clock. In the audio signal processing device, input data is taken out of the data latch 103 and output data is written in the data latch 104 at an arbitrary timing until the next LR clock inversion.

 The state of internal data at each timing is shown in FIG.

Reference numerals 301, 302 and 303 show the internal data of each register and shifter at the timing shown in FIG.

At the timing 301, the data latch 104 outputs the data B ′, which is the data to be output in the next cycle, to the shift register 10.
In bits 0 to 14 of 1, the MSB to bit 1 of the data B that is the current input data are the bits 15 to bits of the shift register 101.
The data A ', which is the data currently being output, is held in 25, and the data A, which is the input data of the previous cycle shifted by 2 bits in the upper direction by the barrel shifter 102, is held in the data latch 103. At this time, “0” is set to the lower 2 bits of the data latch 103 by the barrel shifter 102.
Here, the data A'will be described. The data A ′ is data that has been input before the present time and has already been subjected to the desired processing, and like the data A at the present time, “0” is added to the lower 2 bits of the LSB. Further, since the data line 131 is selected by the selection circuit 105, the shift register 101 outputs bit 17 of the shift register 101. Therefore, at the present time, the LSB of data A ', that is, data A'
When viewed as an 18-bit width, bit2 is output from the serial data output terminal 107.

At timing 302, first, all bits of data B are input to the shift register 101 as shown in the upper diagram. Then LR
When the clock is generated, the data B in the shift register 101 is shifted by 2 bits in the upper direction by the barrel shifter 102 and latched in the data latch 103 as shown in the lower diagram. At the same time, the data B'held in the data latch 104 is taken into the shift register 101 for serial output. At this point, the MSB of the data B'is stored in the bit 17 of the shift register 101.

At the timing of 303, the MSB of the input data C is taken into the bit 0 of the shift register 101. Therefore, since the data B'is shifted by 1 bit in the upper direction, the serial data output terminal outputs bit14 of the data B ', that is, bit16 when the data B'is viewed as 18 bits wide.

In summary, the input serial data is first captured by the shift register 101 and sent to the internal data bus 121 through the barrel shifter 102 and the data latch 103.
Then, as in the conventional example, after the audio signal processing is performed by the processing block, it is stored in the data latch 104, fetched again in the shift register 101, and serially output.

Further, at this time, the data latch signal 142 is masked, and the selected circuit 105 selects the data line 130, whereby the input audio data can be output as it is.

Next, the operation when the bit clock is 48 times the LR clock and the audio data length is 16 bits will be described.

The audio data input from the serial data input terminal 106 is taken into the shift register 101 in synchronization with the data shift signal 141, and at the end of the data transfer of one word, 16-bit data from bit15 to bit0 of the shift register 101 Is retained. Here, the shift amount control signal 143
By designating a 2-bit shift to the high order to the barrel shifter 102, the data latch signal 142 input in synchronization with the inversion of the LR clock causes 18
Audio data is latched in the upper 16 bits of the bits. At the same time, the audio data held in the data latch 104 is input to the shift register 101. By selecting the data line 133 by the selection circuit 105, the output audio data held in the shift register 101 is output from the serial data output terminal 107 in the format shown in FIG.
In the audio signal processing device, input data is read from the data latch 103 and output data is written in the data latch 104 at any timing until the next LR clock inversion.

Further, at this time, the data latch signal 142 is masked and the selection circuit 105 selects the data line 132, whereby the input audio data can be output as it is.

Next, the operation when the bit clock is 48 times the LR clock and the audio data length is 18 bits will be described.

The audio data input from the serial data input terminal 106 is taken into the shift register 101 in synchronization with the data shift signal 141, and at the end of the data transfer for one word, the 18-bit data from bit17 to bit0 of the shift register 101 is output. Retained. Here, by designating the shift amount of the barrel shifter 102 to zero by the shift amount control signal 143, 18-bit audio data is latched in the data latch 103 by the data latch signal 142 input in synchronization with the inversion of the LR clock. . At the same time, the audio data held in the data latch 104 is input to the shift register 101. By selecting the data line 132 by the selection circuit 105, the shift register 101 is output from the serial data output terminal 107.
The output audio data held in the above is output in the format shown in FIG. In the audio signal processing device, input data is read from the data latch 103 and output audio data is written in the data latch 104 at an arbitrary timing until the next LRCK inversion.

Further, at this time, the data latch signal 142 is masked and the selection circuit 105 selects the data line 132, so that the input audio data can be output as it is.

The selection circuit 105 selects the data lines 130, 13 depending on the value of the selection signal 144.
One of 1,132,133 is connected to the data line 123.

When the value indicated by the selection means 144 is “0”, the data line 130 is connected to the data line 123. The data line 130 is connected to the output of bit 15 of the shift register 101, and at the same time, by masking the data latch signal 142, internal data transfer is performed when data transmission is performed according to the transmission format 203 shown in FIG. It is possible to output the input 16-bit data as it is in the next cycle without performing any operation.

When the value indicated by the selection signal 144 is “1”, the data line 131 is connected to the data line 123. The data line 131 is connected to the output of bit 17 of the shift register 101. At this time, in synchronization with the data shift signal 141, the upper 16 bits of the output data held in the data latch 104 are output, and the data transmission according to the data transmission format 203 shown in FIG. 2 becomes possible.

When the value indicated by the selection signal 144 is “2”, the data line 132 is connected to the data line 123. The data line 132 is connected to the output of bit 23 of the shift register 101. Data latch at this time
18-bit data is output following the expanded MSB 6 bits of the data held in 104, and data transmission becomes possible according to the data transmission format 201 shown in FIG. At this time, by masking the data latch signal 142 at the same time, the 24-bit data input from the serial input terminal can be output as it is in the next cycle, and data can be transferred without internal data transfer. It becomes possible to perform data transmission according to the transmission format of the transmission format 201 or 202.

When the value indicated by the selection signal 144 is “3”, the data line 133 is connected to the data line 123. The data line 133 is connected to the output of bit 25 of the shift register 101. Data latch at this time
The upper 16-bit data is continuously output after the expanded MSB 8 bits of the data held in 104, and data transmission according to the data transmission format 202 becomes possible.

 FIG. 4 is a block diagram of another embodiment of the present invention.

This embodiment has a shift register 401, a barrel shifter 402, data latches 403, 404, a selection circuit 405, a serial data input terminal.
406, serial data output terminal 407, counter 408, 2-input NAN
D gate 409, inverter 410, D type flip-flop 41
1, internal data bus 421, data line 422,423,424,425,426,42
7,428,429,430, Data shift signal 441, Data latch signal
442, shift amount control signal 443, selecting means 444, data length instruction signal 445, data shift enable signal 446, data shift signal 447, and data latch signal 448.

The shift register 401 is an 18-bit wide shift register having a parallel input and parallel output function. The serial data input is connected to the data line 422, the data shift timing is given by the data shift signal 447, and the parallel data fetch timing is provided. Are provided by the data latch signal 448. Further, the parallel data input of the shift register 401 is connected to the data line 425, and the parallel data output is connected to the data line 426.

The barrel shifter 402 is an 18-bit width shifter, and depending on the value indicated by the shift amount control signal 443, the 18-bit width data is output as it is or is shifted by 2 bits in the upper direction and output. However, at this time, data "0" is output to the lower 2 bits. The data line 426 is connected to the input of the barrel shifter 402, and the data line 427 is connected to the output.

The data latch 403 is a data latch having an 18-bit width, and captures the data input from the data line 427 at the timing of the data latch signal 448 which is a signal indicating the data transfer end timing for one word. The output is connected to the data line 428.

Data latch 404 is an 18-bit wide data latch whose input is connected to data line 424 and whose output is data line 425.
Connected to.

The selection circuit 405 is a circuit that selects and outputs one of the two inputs according to the value indicated by the selection means 144, and the input is connected to the data lines 429 and 430 and the output is connected to the data line 423.

The serial data input terminal 406 is connected to the data line 422.

The serial data output terminal 407 is connected to the data line 423.

The counter 408 detects 16 of the data shift signal 441 from the falling edge of the next data shift signal 441 when the data latch signal 442 becomes active according to the value indicated by the data length instruction signal.
Data shift enable signal 44 for 18 cycles or 18 cycles
Make 6 active.

The internal data bus 421 is an 18-bit wide data bus.

The data lines 424, 425, 426, 427, 428 are 18-bit wide data lines.

The data line 426 is bit0 to bit from the least significant bit.
If it is set to 17, bit15 is connected to the data line 429, and bit17 is connected to the data line 430.

 The operation of this embodiment will be described below.

This embodiment is a data input / output circuit of an audio signal processing device for inputting / outputting audio data.

An example of the serial transmission format of audio data is the Inter IC Sound (hereinafter abbreviated as I ² S) format shown in FIG.

L for audio data transmission in I ² S format
Serial data is transmitted in the MSB format after one cycle of the bit clock with respect to the inverted edge of the R clock.

The bit clock shown in FIG. 5 is input to the data shift signal 441 as the transmission clock, the LR clock is input to the data latch signal 442 as the word period signal, and the data is input to the serial data input terminal 406.

The audio data length is 16 bits or 18 bits, and the data is input to the internal bus first.

16-bit or 18-bit audio data is input from the serial data input terminal 406 every sampling period, the data latch signal 442 becomes active in synchronization with the edge of the LR clock indicating the word timing of the data, and the data shift signal 441. A bit clock is input to.

First, the case where the audio data length is 16 bits will be described.

The audio data input from the serial data input terminal 406 is loaded into the shift register 401 in synchronization with the data shift signal 447. At this time, the data shift means 447
16 bits are input while the output data shift enable signal 446 of the counter 408 is active, that is, from the next falling edge when the data latch signal 442 becomes active. Therefore, when the transfer of 16-bit data is completed, the data is held in bits 15 to 0 of the shift register 401. At this time, the barrel shifter 4 is driven by the shift amount control signal 443.
Specify the 2-bit shift to the higher order in 02. In this state, it waits for the next inverted edge of the LR clock, that is, for the data latch signal 442 to become active. Data latch signal 4
When 42 becomes active, the data latch signal 448 becomes active with a delay of one cycle of the data shift signal 441,
The 16-bit audio data held in the shift register 401 is taken into the data latch 403, and the output audio data held in the data latch 404 is input to the shift register 401 at the same time. At this time, if the input of the selection circuit 405 is selected to the data line 430 side by the selection signal 444,
Data shift signal 447 from serial data output terminal 407
16-bit output audio data is output in synchronization with.

At this time, the data latch signal 448 is masked and the selection circuit 405
By this, it becomes possible to output the input voice data as it is by selecting the data line 429.

Next, the operation when the audio data length is 18 bits will be described.

The audio data input from the serial data input terminal 406 is taken into the shift register 401 in synchronization with the data shift signal 447. At this time, the data shift signal 4
47 is the output of the counter 408, the data shift enable signal 4
18 bits are input while 46 is active, that is, from the next falling edge after the data latch signal 442 becomes active. When the 18-bit data transfer is completed, the data is held in bit17 to bit0 of the shift register 401. At this time, the shift prohibition of the barrel shifter 402 is designated by the shift amount control signal 443. In this state, wait for the next inversion of the LR clock, and if the data latch signal 448 becomes active subsequent to the data latch signal 442, the shift register 401
The 18-bit input voice data held in the data latch 403 is taken into the data latch 403, and at the same time, the output voice data held in the data latch 404 is input into the shift register 401. If the data line 430 is selected by the selection circuit 405,
Data shift signal 447 from serial data output terminal 407
The 18-bit output audio data is output in synchronization with.

At this time, the data latch signal 448 is masked and the selection circuit 4
By selecting the data line 430 with 05, the input voice data can be output as it is.

The selection circuit 405 selects one of the data lines 429 or 430 according to the value of the selection signal 444 and connects it to the data line 423.

When the selection signal 444 is “0”, the data line 429 is connected to the data line 423. Data line 429 is shift register 401
Connected to bit15. At this time, by simultaneously masking the data latch signal 442 and selecting the data length to 16 bits by the data length instruction signal 445, the serial data input 40
The 16-bit audio data input from 6 can be output without performing an internal transfer operation, and data transmission according to the transmission format 502 shown in FIG. 5 is possible.

When the selection signal 444 is “1”, the data line 430 is connected to the data line 423. Data line 430 is shift register 401
Connected to bit17 of. At this time, if the data length is set to 16 bits by the data length instruction signal 445, the data latch 404
The data held in the data is synchronized with the data shift signal 441, and the upper 16-bit data is output, and the data can be transmitted according to the data transmission format 502 shown in FIG.

Further, when the data length is selected to 18 bits by the data length instruction signal 445, the output data held in the data latch 404 is output in synchronization with the data shift signal 441, and the data transmission according to the data transmission format 501 becomes possible. Become.

At this time, the data length is set to 1 by the data length instruction signal 445.
By selecting 8 bits and masking the data latch signal 448 at the same time, it is possible to output the input 18-bit audio data in the next synchronization without performing the data transfer operation internally.

〔The invention's effect〕

As described above, according to the present invention, the data shift circuit on the input side of serial data and the data shift circuit on the output side are provided in one system, so that the circuit scale can be compared with the conventional two systems of shift registers.
It can be reduced to 1/2, and since the input and output clocks of serial data are the same, the jitter of the transmission clock during data transmission can be reduced, and no further processing is performed on the data in the digital signal processing device. When not processing, the input data can be output as it is without performing any special operation such as data transfer. Therefore, it is possible to perform other processing independently of the data transmission in the information processing device. There is an effect that the processing capacity can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a diagram showing a format of a serial data interface, FIG. 3 is a data timing chart of the present embodiment, and FIG. 4 is a second of the present invention. 5 is a block diagram of an embodiment of the present invention, FIG. 5 is a diagram showing a format of a serial data interface, and FIG. 6 is a block diagram of a conventional serial data transmission circuit. 101,401 ...... Shift register, 102,402 ...... Barrel shifter, 103,104,403,404 …… Data latch, 105,405 …… Selection circuit, 106,406,604 …… Serial data input terminal, 10
7,407,605 …… Serial data output terminal, 408 …… Counter, 409 …… 2-input NAND gate, 410 …… Inverter, 41
1 …… D type flip-flop, 121,421,610 …… Internal data bus, 122,123,124,125,126,127,128,129,130,13
1,132,133,422,423,424,425,426,427,428,429,430 ……
Data line, 141,441,447 ... Data shift signal, 142,44
2,448 …… Data latch signal, 143,443 …… Shift amount control signal, 144,444 …… Selection signal, 445 …… Data length instruction signal, 446 …… Data shift enable signal, 601 …… Signal processing device, 602 …… Serial data input Circuit, 603 ... serial data output circuit, 606 ... serial data transmission clock input terminal, 607 ... serial data transmission clock output terminal, 608 ... processing block, 609 ... timing control circuit.

Claims (6)

(57) [Claims] 1. A serial data input terminal, a serial data output terminal, a transmission clock input terminal, a word period signal input terminal, a data shift means having a parallel input terminal and a parallel output terminal, and a bit position conversion means. It has a first data holding means, a second data holding means, and a selection means. The serial data input terminal is connected to the serial input of the data shift means, and the serial input terminal is connected to the parallel input terminal of the data shift means. Is connected to the output of the second data holding means, the parallel output terminal of the data shift means is connected to the input of the bit position conversion means, and a specific terminal of the parallel output terminals of the data shift means is selected. Connected to the input of the means, the output of the bit position conversion means is connected to the input of the first data holding means, and the output of the selection means is the Serial data transfer circuit, characterized in that it is connected to the real data output terminal. 2. A serial data transmission circuit according to claim 1, wherein an input of said first data holding means and an output of said second data holding means are commonly connected to a data bus. A serial data transmission circuit characterized by the above. 3. The serial data transmission circuit according to claim 1, wherein when the bit position conversion means performs bit position conversion on the upper side, the converted bit number is set to "0" at the lower side. A serial data transmission circuit having a circuit to be added. 4. The serial data transmission circuit according to claim 1, wherein the first data holding means fetches input data from a parallel output terminal of the data shift means in synchronization with the word period signal. A serial data transmission circuit having a circuit. 5. The serial data transmission circuit according to claim 1, wherein the data shift means performs data shift in synchronization with the transmission clock, and the parallel input in synchronization with the word cycle signal. A serial data transmission circuit having a circuit for fetching parallel data from a terminal. 6. The serial data transmission circuit according to claim 1, wherein audio data is input to the serial data input terminal.